JPH04206753A - Semiconductor wafer and inspecting method for semiconductor element thereof - Google Patents

Abstract

PURPOSE:To enable electrical characteristics of a semiconductor element in a semiconductor wafer state to be inspected easily and an environmental test in a semiconductor wafer to be performed by forming an electrode for inspection which is connected to at least one semiconductor element at a region of the semiconductor wafer where no semiconductor elements are formed, etc. CONSTITUTION:A semiconductor wafer 1, a number of semiconductor elements 2 which are formed on the semiconductor wafer 1, and an electrode for inspection 4 which is connected to at least one above semiconductor element 2 which is formed at a region of the semiconductor wafer 1 where the semiconductor element 2 is not formed are provided. Also, when inspecting electrical characteristics of a plurality of semiconductor elements 2 which are formed on the semiconductor wafer 1, a plurality of electrode pads 4 are provided at an outer-periphery part of the semiconductor wafer 1 where no semiconductor element 2 is formed and a conductor pattern 5 for connecting those electrode pads 4 and the semiconductor element 2 electrically is provided, thus enabling electrical characteristics of the semiconductor element 2 to be inspected through the above electrode pad 4.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a method for testing semiconductor devices.

(Prior Art) Generally, a large number of semiconductor elements are simultaneously formed on a semiconductor wafer by precision phototransfer technology, etc., and then cut into individual semiconductor elements (semiconductor chips) along scribe lines.

In the manufacturing process of such semiconductor devices, the electrical characteristics of the semiconductor devices in the semiconductor wafer state (before cutting) have been inspected conventionally.

In this inspection of the semiconductor wafer, the semiconductor wafer is inspected using a probe card in which a row of probe needles with a microscopic diameter is implanted in correspondence with the rows of microelectrode pads formed in each semiconductor element, and a vacuum chuck. A probe device that holds the semiconductor wafer and moves the semiconductor wafer in the x-y-z directions, and a tester that is an electrical measuring device are used. The probe needle of the probe card is contacted to establish electrical continuity, and the electrical characteristics are measured using a tester.

(Problems to be Solved by the Invention) However, in the conventional semiconductor device testing method described above, it is necessary to bring the probe needle into precise contact with the minute electrode pads of each semiconductor device. High positional accuracy is required as devices become more highly integrated.

For this reason, high positional accuracy is required for probe devices, probe cards, etc., and there are problems in that alignment becomes complicated, and environments that require tens of hours in high or low temperature environments accompanied by thermal expansion, etc. There were problems such as the inability to conduct tests on semiconductor wafers.

Furthermore, depending on the mounting method, for example, when a chip is attached to a board, it is not in a packaged state, so environmental testing with a handler is not possible. There was also the problem of the board becoming defective.

The present invention has been made in response to such conventional circumstances, and it is possible to inspect the electrical characteristics of semiconductor elements in the state of semiconductor wafers more easily than in the past, and it is possible to conduct environmental tests in the state of semiconductor wafers. The present invention aims to provide a semiconductor wafer and a method for inspecting semiconductor elements of this semiconductor wafer, which enable this.

[Structure of the Invention] (Means for Solving the Problems) That is, the semiconductor wafer of the present invention includes a semiconductor wafer, a large number of semiconductor elements formed on the semiconductor wafer, and a semiconductor wafer on which the semiconductor elements are not formed. and an inspection electrode connected to at least one of the semiconductor elements formed in the region.

Furthermore, in the semiconductor device testing method of the present invention, when testing the electrical characteristics of a plurality of semiconductor devices formed on a semiconductor wafer, a plurality of electrode bands are placed in advance on the outer periphery of the semiconductor wafer on which the semiconductor devices are not formed. In addition to establishing
The present invention is characterized in that a conductive pattern is provided to electrically connect these electrode bands and the semiconductor element, and the electrical characteristics of the semiconductor element are tested via the electrode pads.

(Function) In the semiconductor wafer of the present invention and the method for testing semiconductor elements of the semiconductor wafer, a plurality of electrode pads are provided in advance on the outer periphery of the semiconductor wafer, and these electrode pads and the semiconductor elements are electrically connected. A conductor pattern is provided.

The conductor pattern is formed, for example, on a scribe line, and the electrode pad is large in size and provided in a portion of the outer periphery of the semiconductor wafer where semiconductor elements cannot be formed.

Then, electrode terminals or the like are brought into contact with these electrode pads to establish electrical continuity with the semiconductor element, and the electrical characteristics of the semiconductor element are tested.

Therefore, it is possible to inspect the electrical characteristics of a semiconductor element in the state of a semiconductor wafer more easily than in the past without requiring highly accurate positioning as in the past. Therefore, it is possible to absorb errors caused by thermal expansion and contraction caused by large temperature changes, and it is also possible to conduct environmental tests in the state of semiconductor wafers.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

As shown in FIGS. 1 and 2, a semiconductor wafer 1 formed into a circular disk shape has a large number of rectangular semiconductor elements 2.
are formed, and scribe lines 3 each having a width of 1008 m, for example, are formed between these semiconductor elements 2.

Further, in a portion of the outer periphery of the semiconductor wafer 1 where the semiconductor element 2 cannot be formed, a large rectangular electrode pad 4 is provided, which is larger than the area of the electrode pad to be formed on the semiconductor element 2, for example, with dimensions of several millimeters in each direction. are formed in large numbers.

Further, as shown in FIG. 3, a plurality of conductive patterns 5 are formed on the scribe line 3 of the semiconductor wafer 1, and electrode pads 6 of each semiconductor element 2 and large conductive patterns on the outer periphery of the semiconductor wafer 1 are formed. The electrode pads 4 are electrically connected to each other by these conductive patterns 5. By forming the conductive pattern 5 and the large electrode pad 4 in this way, the method of the present invention can be carried out without wasting space on the semiconductor wafer 1 and without causing a decrease in space efficiency.

Note that the conductive pattern 5 and large electrode pad 4 are as follows:
The wiring pattern of the semiconductor element 2 is formed simultaneously with the wiring pattern of the semiconductor element 2 through a series of photolithography processes.

In this embodiment, electrical continuity with the semiconductor element 2 is obtained by bringing electrode terminals (probe needles or pogo pins described later) into contact with these large electrode pads 4, and testing the semiconductor element 2 with a tester (not shown) or the like. Inspect electrical characteristics.

In addition, in the semiconductor wafer 1 shown in FIGS. 1 to 3, if the arrangement of the semiconductor elements 2 in the horizontal direction is called a column, and the arrangement of the semiconductor elements 2 in the vertical direction is called a row, for example, as shown in FIG. VccSGND (or CHIP EN
ABLE, CHIP DISABLE) large electrode pads 4 are arranged, and large electrode pads 4 corresponding to one chip are arranged above and below each row. As a result, Vcc, GN
p (or CHIP ENABLE, CHIP
By selecting a desired column using ``DISABLE'' and performing measurement using the upper and lower large electrode pads 4 of a desired row, desired semiconductor elements 2 can be measured one by one.

In addition, if the tester is capable of performing multi-tests on semiconductor devices 2 for each row, it is possible to test multiple semiconductor devices 2 for each -column.
can also be measured at the same time.

In such a case, each column is separated left and right at the center of the semiconductor wafer 1, and the Vc of the semiconductor elements 2 arranged on the left side of the center is
c, GND is connected to the large electrode pad 4 provided on the left end of the semiconductor wafer 1, and the V of the semiconductor elements 2 arranged on the right side of the center
By connecting cc and GND to the large electrode pad 4 provided on the right end of the semiconductor wafer 1, it is possible to prevent the wiring length from becoming too long. Alternatively, it is also possible to make the scribe line in the center of the wafer several millimeters wide and insert the necessary large electrode pads. In this case, it is possible to further shorten the wiring length. In short, test electrode pads are formed in areas of the wafer where semiconductor elements are not formed.

In addition, even if there is a leak in VCC%GND, it is easy to determine whether the semiconductor element 2 with the leak is the semiconductor element 2 arranged on the left side of the center or the semiconductor element 2 arranged on the right side. can be judged.

For example, if the Vcc of a specific semiconductor element 2 drops to GND and affects the surrounding semiconductor elements 2, cut off the Vcc and GND of only that semiconductor element 2 with a laser or the like to reduce the influence on the surroundings. It can also be avoided.

FIG. 4 shows the configuration of a wafer holder 10 as an example of an apparatus for testing the electrical characteristics of the semiconductor element 2 by the above method.

As shown in the figure, the wafer holder 10 includes a wafer holder 11 formed in a rectangular plate shape and configured to be able to hold the semiconductor wafer 1, and a large-sized semiconductor wafer 1 held in the wafer holder 11. The electrode part 13 is provided with an electrode mechanism such as a pogo pin 12 corresponding to the electrode pad 4 and is formed in a rectangular plate shape. The wafer holding part 11 and the electrode part 13 are configured to be openable and closable as shown by arrows in the figure, and the semiconductor wafer 1 is held between the wafer holding part 11 and the electrode part 13 when they are closed. At the same time, the pogo pins 12 are configured to come into contact with the large electrode pads 4 of the semiconductor wafer 1 to obtain electrical continuity. In addition, each pogo pin 1 is attached to the electrode part 13.
A conductor pattern 14 is formed extending from the electrode portion 13 to the end portion (the lower part in this embodiment) of the electrode portion 13.
A socket portion 15 is provided at the end portion of.

Then, as shown in FIG. 5, for example, a plurality of the wafer holders 10 (for example, 25 to 50 wafer holders) are placed in the oven 20, and a burn-in test or the like is performed, for example. Note that an electrical connection mechanism is installed in the oven 20 to correspond to the socket portion 15 and to establish an electrical connection with the tester.

In this way, electrical continuity is obtained by bringing the pogo pins 12 into contact with the large electrode pads 4, so there is no need for highly accurate alignment, and positional deviations due to temperature changes during burn-in tests (differences in thermal expansion of each part) are avoided. ) can also be absorbed. Furthermore, if this holder is moved in and out of the oven by a robot or the like, an automated burn-in system is possible.

In the above embodiment, test electrode pads were provided for every semiconductor element, but it is also possible to divide the wafer into multiple regions and lead out only the sampling chips in each divided region to large electrode pads, or All areas within the area may be commonly connected to a large electrode pad equivalent to -chip.

[Effects of the Invention] As explained above, according to the semiconductor wafer and the method for inspecting semiconductor elements of the semiconductor wafer of the present invention, the electrical characteristics of the semiconductor elements in the semiconductor wafer state can be recorded in the package as compared to the conventional method. It becomes possible to perform environmental tests in the state of semiconductor wafers.

[Brief explanation of the drawing]

1 to 3 are diagrams showing the configuration of a semiconductor wafer for explaining a semiconductor device testing method according to an embodiment of the present invention, and FIG. 4 is a diagram showing the configuration of a wafer holder used in an embodiment of the method of the present invention. The figure shown in FIG. 5 is a diagram showing a state in which the wafer holder shown in FIG. 4 is placed in an oven. 1... Semiconductor wafer, 2... Semiconductor element, 3... Scribe line, 4... Large electrode pad, 5... Conductive pattern, 6...
...Electrode pads for semiconductor devices. Applicant Tokyo Electron Co., Ltd. Agent Patent Attorney Sasa Suyama - (1 other person)

Claims (2)

[Claims] (1) A semiconductor wafer, a large number of semiconductor elements formed on the semiconductor wafer, and an inspection electrode connected to at least one semiconductor element formed in an area of the semiconductor wafer where no semiconductor element is formed. A semiconductor wafer comprising: (2) When inspecting the electrical characteristics of a plurality of semiconductor elements formed on a semiconductor wafer, a plurality of electrode pads are provided in advance on the outer periphery of the semiconductor wafer where the semiconductor elements are not formed, and these electrode pads and A method for testing a semiconductor device, characterized in that a conductor pattern is provided to electrically connect the semiconductor device, and the electrical characteristics of the semiconductor device are tested via the electrode pads.