JP3076831B2 - Device test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an element test device.

B. 2. Description of the Related Art In general, before a wafer is separated by a scribing process in an IC (Integrated Circuit) assembling process, an inspection of a wafer is performed by performing an electrical test of each IC chip formed on the wafer to detect those defective products. A process is taking place. This is mainly based on a device having a probe card provided with a large number of probes (probes for electrically contacting each pad of each IC chip) called a prober, and a high-speed called an IC tester. The test system is made up of an automatic measuring device. That is, a predetermined signal is sent to each pad (input pad) of the IC chip through the probe by the IC tester,
The result is passed through the probe contacted to the output pad to the IC.
By measuring with a tester, each IC chip is sorted into non-defective products and defective products. This sorting is performed by imprinting defective products with magnetic ink or the like.

An example of the above-described prober will be described with reference to FIGS. 21 and 25. However, FIG. 21 is a schematic cross-sectional view of a main part along the line XXI-XXI in FIG. 25, and FIG. 25 is a top view of the entire prober.

The prober 1 includes a supply cassette 2 for supplying a wafer 3 to be tested, a storage cassette 14 for storing the tested wafer 3, a pre-alignment stage 5 for mechanically aligning the wafer 3 in advance, and a wafer 3. Chucks 12 for sucking the wafer 3 and moving them to predetermined positions, respectively, and a suction stage for sucking the wafer 3 carried by the Bernoulli chuck 7 at a predetermined position and moving it to a probing (test operation) area 9. It is mainly constituted by a chuck 47 (not shown) and a probe card 17 (see FIG. 21) having a number of probe needles 19 attached to the head stage 10 and used for predetermined probing.

In the figure, reference numeral 4 denotes a belt for moving the wafer 3, 6 denotes a loading side, 8 denotes a displacement sensor for measuring the shape of the wafer, 11 denotes an unloading side, and 15 denotes a probe operation accurately. And a microscope 16 for monitoring the wafer 3 is an optical unit of a fine alignment device for performing a fine alignment of the wafer 3 (alignment for accurately aligning the chip 3a on the wafer 3 with reference to the X axis and the Y axis). Arrows A1 to A7 indicate the directions in which the wafer 3 moves.

At the time of the probe operation, as shown in FIG. 21, the chuck 47 is configured to operate in the X and Y directions (horizontal direction) and the Z direction (vertical direction),
Fine adjustment in the horizontal direction is performed while monitoring with the microscope 15 through the opening 18 of 17, the chuck 47 is raised, and each probe 19 is moved.
Each pad (not shown in FIG. 21) of the IC chip 3a is electrically contacted with a predetermined pressing force.

Next, problems of the above-described prober 1 will be described with reference to FIGS. 21 to 24. FIG.

That is, in the above-described example, when performing the probe operation, since the operation must be performed while monitoring through the opening 18 of the probe card 17 by the microscope 15, the probe is provided on the probe card 17 as shown in FIG. The probe needle 19 must be arranged at a predetermined angle (in an oblique direction) with respect to the IC chip 3a (that is, the layout must be such that the probe operation can be monitored by the microscope 15 through the opening 18 of the probe card 17). .). For this reason, the probe needle 19, whose tip portion 19a is generally bent in a substantially U-shape, and which is formed so as to be slightly narrower toward its tip, is normally connected to the pad 3b as shown in FIG. 22A. Arrow F
(Horizontal direction), and the tip 19a is scraped off by friction with the pad 3b as shown in FIG. 22B.

Therefore, since the length and diameter of the tip portion 19a of the probe needle 19 fluctuate, the displacement is likely to occur. In the worst case, as shown in FIG. 22B, an insulating film (protective film) slightly coated on the pad 3b is used. The film 3c will also be damaged. As a result, in a later dicing step, moisture (humidity) or the like easily enters at a portion where the insulating film is damaged, which causes a serious problem that the internal circuit element is damaged. Tungsten is usually used for the probe knee 19, but tungsten is relatively weak in material in terms of friction, and it is impossible to prevent the tip 19a from being reduced.

Here, as shown in FIG. 23, when the angle of the distal end portion 19a of the probe needle 19 with respect to the contact surface is θ, and the reduced length of the distal end portion 19a is ln, the horizontal position with respect to the contact surface.
t _n is expressed as t _n = l _n · cos θ. However, t ₀ in the figure is the horizontal position (original position) with respect to the contact surface before the tip 19 a is reduced, and t ₁ is the tip 19.
a horizontal position relative to the contact surface when the length of a is decreased by l _1.

That is, as shown in the above equation, as l _n increases, t ₀ and t _n
, And the positional deviation also increases. Also,
Probe needle so that it becomes slightly thinner toward the tip
Since the tip portion 19a of 19 is formed, the diameter φ increases as l _n increases.

FIG. 24 is a schematic plan view for explaining that the probe needles 19 cannot be simultaneously brought into contact with the pads 3b of many IC chips 3a using the prober 1 in the above-described example.

C. SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable test by eliminating displacement of a semiconductor chip with respect to a pad surface due to a contact such as a probe. It is an object of the present invention to provide an element test apparatus capable of normally performing the test.

D. In other words, the present invention relates to a tester for testing the semiconductor chip and a plurality of contacts that substantially vertically contact the power supply pad and the signal pad of the semiconductor chip in a one-to-one correspondence relationship. Switch means and first wiring connected in series for electrically connecting the power supply pad via the corresponding contact, and the signal pad connected to the tester via the corresponding contact. And a plurality of unit test sections each including a second wiring for electrically connecting the plurality of unit test sections, and each of the plurality of unit test sections corresponds to each pad of a plurality of semiconductor chips formed on a semiconductor wafer. When a plurality of semiconductor chips are simultaneously tested by contacting a contact, when a defective semiconductor chip is detected, the switch means corresponding to a power supply pad of the defective semiconductor chip is opened. The present invention relates to an element test apparatus in which power supply to the defective semiconductor chip is stopped.

The term “substantially perpendicular” ideally means 90 °, but also includes an error range of about 90 ° ± 5 °.

E. Examples Hereinafter, examples of the present invention will be described.

FIG. 1 to FIG. 11 show a first embodiment of the present invention.

Since the entire system of the wafer test apparatus according to this embodiment is substantially the same as the above-described embodiment, the description is omitted, but a significant difference is that instead of the probe card 17 in the above-described prober 1, the pad 3b of the IC chip 3a is replaced. That is, a probe card provided with a plurality of probes all oriented perpendicular to the surface is used.

That is, the probe card 27 according to the present embodiment will be described. As shown in FIGS. 1 and 2, mainly, a holder 26 for fixing and holding a plurality of vertically oriented probes 29 and this holder and board 27a of a predetermined printed wiring has been applied to fix the 26, each of the connection between the probe 29 and their corresponding power supply V _cc and the ground V _ss, which is connected to the IC tester 30 side described later when the test A relay board (RL1 to RL16) for turning on and off is mounted, and a relay board 23 on which predetermined printed wiring is provided. However, in this example, since 16 chips (16 IC chips 3a formed on the wafer 3) can be measured at the same time, the number of probes 29 is, for example, 21 pads per chip. Then for a total of 336, also relay also becomes a total of 32 required in combination with ground V _ss power supply side V _cc per chip, for convenience of explanation, in FIG. 1-FIG. 3 ground V Only the _ss relays RL1 to RL16 are shown, and the power supply-side V _DD relay is not shown (this power supply-side V _DD relay is also the same as the ground-side V _SS relay RL 1 to RL 16 described above. It can be similarly configured.).

Here, reference numeral 21 in the drawing denotes a coaxial cable (75Ω), which is directly soldered to a post portion 29c, which will be described later, of each prober 29, and is further provided with predetermined wiring on a board 27a. As shown in FIGS. 5 and 8, which will be described later, the tester 30 is connected to the tester 30 by predetermined wiring. Reference numeral 22 denotes a cable pressing plate, reference numeral 24 denotes a fixing base for fixing the relay board 23 on the board 27a,
Is an opening for attaching the probe holder 26 to the board 27a, and C is a capacitor (see FIGS. 5 and 8) connected to the _VDD side. In this example, as shown in FIG. 1-FIG. 3, is performed by dividing the predetermined wiring on the board 27a of the probe card 27 to the V _DD side and V _SS side.

The probe holder 26 mainly includes a fixing plate 26 for fixing the probe 29, as shown in FIGS.
a, support plate 26b to prevent lateral deflection of probe 29
And a stopper plate for preventing the probe 29 from shifting downward, whereby the very thin and vertically long probes 29 can be held respectively. The probe 29 is made of, for example, a BeCu needle portion (tip portion) 29a (two cylindrical portions having different diameters, and a portion having a smaller diameter on the contact side has a rounded tip. The end of the larger diameter part on the opposite side is formed in a triangular pyramid shape.), A cylindrical case 29b made of, for example, stainless steel and the whole surface is plated with gold, and a post part made of, for example, BeCu 29c (consisting of two cylindrical portions having different diameters, both ends of which are formed in a triangular pyramid shape), and a needle portion 29a housed in a case 29b and attached to a pad 3b of the IC chip 3a. Each of them is constituted by, for example, a SWP spring 31 usually called a piano wire, which is formed so as to obtain a predetermined contact pressure when it comes into contact.

In this example, as shown in FIGS. 5 and 6,
In each of the rectangular chips 3a, pads 3b are provided on two short sides, respectively. The pads 3b are simultaneously contacted with the pads 3b of 16 chips (CHIP1 to CHIP16) in two rows and eight columns on the wafer 3 (pad 3b). A plurality of probes 29 are provided on the probe holder 26 of the probe card 27 so as to be in contact with each other so as to be all perpendicular to the surface (first).
FIG. 2, FIG. 3 and FIG. 3). FIG. 8 is a schematic block diagram showing a connection relationship between each probe 29 and the tester 30 in the probe card 27. Further, FIG. 9 is a connection circuit diagram of a relay RL1~RL8 for V _SS (or RL9～RL16), FIG. FIG. 10 is representative of the connection wiring pattern in the relay board 23 (i.e., connections depicted in FIG. 9 Circuit diagram for relay board 23
Figure) for forming a wiring pattern on, FIG. 11 changeover relay V _SS side that is used in this example RL1~RL
16 is an external view of this example (in this example, a VS-105N manufactured by Sanko Kogyo Co., Ltd. of a movable contact type with a coil voltage of 5 V is used). Here, for switching the relay of V _DD side in this example RL21~R
A description of is omitted for L36, but switching relay circuit easily V _DD side with the structure similar to the V _SS side switching relay circuit shown in FIG. 9 to 11 diagram described above (5 (See FIG. 8 and FIG. 8). However, in the relay circuit on the _VDD side, the GND in the circuit diagram shown in FIG.
The line is V for applying a predetermined voltage from the tester 30.
_DD line.

As shown in FIG. 5 and FIG. 8, each unit test section in this embodiment substantially corresponds to the V _DD and Vss pads of each semiconductor chip CHIP and the other pads (signal pads) 3b in a one-to-one correspondence. Multiple vertical contacts (32 in this example)
Probe 29, a relay switch RL and a first wiring 60 connected in series for electrically connecting the _VDD pad and the Vss pad 3b to the tester 30 via the corresponding probe 29, 30 includes a second wiring 62 for electrically connecting the signal pad 3b via the corresponding probe 29 to the signal pad 3b.

During the test, the chuck 47 is raised while performing a predetermined position adjustment as shown in FIG. 3 as in the above-described example, whereby all the probes 29 are moved to the predetermined positions as shown in FIG. 4B. Are vertically oriented with respect to the pads 3b on the IC chip 3a, and are respectively brought into contact with the pads 3b while maintaining a predetermined contact pressure by a spring 31. And tester
A predetermined signal from the 30 side is passed to each pad 3b through each probe 29.
The tester 30 performs a predetermined test such as a DC test by detecting the result on the tester 30 side through the probe 29 contacted with the output pad or the like. In this case, for example, among one item V _DD pad and V _SS pad circuitry to respectively from the tester 30 side of the chip each time for chip 3a result of the test is defective for each test item Must be cut off (otherwise,
The predetermined voltage is not sufficiently supplied from the tester 30 side to the other normal chips 3a, and each test of other test items cannot be performed. ), As described above, each chip 3a
Of the relays RL1 to RL36 connected between the V _DD pad and the V _SS pad and the tester 30 side, the relay connected to the defective chip 3a (for example, if the chip 1 shown in FIG. 5 is defective, the relays RL1 and RL21 ) Is turned off by the control on the tester 30 side. That is, turns off the relay switch by applying a voltage of the coil, for example, from the tester 30 side to 5V relays disconnected only from the tester 30 side V _DD pad and V _SS pads defective chip 3a.

And actually, for example, in a 6-inch wafer 3
The test procedure for the 286 IC chips 3a (for example, a 1M dynamic RAM) will be described with reference to FIG. 7. First, all the areas in the direction from the start position in the direction indicated by the arrow W1 (toward the orientation flat surface) will be described. Chip 3a
A predetermined test is performed by repeating each operation described above for. At this time, as described above, the probe card 27 of the prober 1 according to the present embodiment is provided with the probe 29 that can simultaneously contact each pad 3b of a total of 16 chips in 2 rows and 8 columns. As shown, the probe 29 does not naturally contact the portion where the chip 3a does not exist,
Therefore, the test is performed only on the chip 3a that has come into contact with the probe 29 (the same applies to other areas).

Next, after performing each test for all the chips 3a in the region (3), the above description is performed for all the chips 3a in the region (in the direction from the orientation flat surface to the bottom in the diagram) in the direction indicated by the arrow W2 in the drawing. Perform the same test as. And all the chips in the area of
After performing each test for 3a, the arrows W3 and W4
The test of the wafer 3 is completed by performing the respective tests on all the chips 3a in the respective regions in the directions indicated by W5 and W5.

Although not shown in this example, for example, a CCD camera or the like is installed at a predetermined position of the chuck 47 in FIG.
Has a predetermined monitoring means configured so that the state of connection to the pad 3b of each IC chip 3a can be externally monitored by the CCD camera, so that the wafer 3 (IC Fine adjustment of the position of the tip 3a) can be easily performed.

In addition, there are actually IC chips 3a formed on the wafer 3 that are good in nature because of good performance, but cannot be handled as non-defective products (for example, on the back surface of the wafer 3). Is usually plated with gold, but there is always a region on the outer periphery where this is not done.) The chip 3a is determined not to be a test chip (INK CHIP) in advance and the test is not performed (in this example, the IC formed on the wafer 3 as shown in FIG. 7).
There are a total of 316 chips 3a, of which there are 30 INK CHIPs not shown. In the above-described example, illustration is omitted for convenience of explanation (the same applies to the following examples).

As described above, according to the present example, the distal ends 29a of the plurality of probes 29 are configured so as to be all perpendicular to the contact surface of the pad 3b of the IC chip 3a. The tip 19a like the probe 19
But obliquely (at a predetermined angle) to the contact surface of the pad 3b
There is no contact. Therefore, the probe 29 is connected to the IC chip 3a.
When contacting the pad 3b, there is no positional displacement due to the above-described lateral force (that is, as shown in FIG. 4B, the tip 29a of the probe 29 contacts the pad 3b). Since it is oriented perpendicularly to the surface and is in contact with it, no lateral force is applied.), Its positioning is easy, and a highly reliable test can be performed.

Further, in this example, as described above, since BeCu is used for the distal end portion 29a of the probe 29, the contact resistance is small in terms of material, and therefore, there is little adverse effect on the friction on the contact surface. There is no need to worry about reduction of the tip portion 29a due to friction or the like. Further, in the present embodiment, as described above, the spring 31 formed separately from the distal end portion 29a of the probe 29 is configured to be able to maintain a predetermined contact pressure on the pad 3b surface.
By appropriately designing 31, the above contact pressure can be easily set appropriately.

What should be noted in this example is that the fifth
As shown in FIG. 6 and FIG. 6, a total of 16 chips (CHIP1 to CHIP1) on the wafer 3 shown in FIG.
6) The ability to test the IC chip 3a simultaneously. That is, as shown in FIG. 24, a 16-chip IC such as this example is provided by a conventional obliquely protruding probe 19 (see FIG. 21).
Considering that the chip 3a is tested at the same time, due to the layout limitation of the probe 19 as described above (that is,
In the conventional probe 19, the layout in the horizontal direction is restricted as shown in FIG. ), Each adjacent pad between adjacent chips 3a (eg, CHIP1 and CHIP9)
Although contact of the probe 19 with the probe 3b is impossible, in this example, as described above, each pad 3b of each IC chip 3a is used.
Since there are a plurality of probes 29 that can be all directed perpendicular to the contact surface of the device, there is almost no need to worry about restrictions on the horizontal layout as in the past, and the degree of freedom in the layout is increased. Will increase. as a result,
The probe 29 can be brought into contact with all the pads 3b of the 16 chips (CHIP1 to CHIP16).
Many chips such as 16 chips can be similarly tested. In the conventional probe 19, the length of the probe 19 varies depending on the position of the pad 3b on the chip 3a,
Therefore, there is a possibility that a predetermined voltage is not supplied due to a difference in contact force with the pad 3b.
Can apply a constant contact force to each pad 3b regardless of the position of the pad 3b.

When the test is actually performed for each chip, it takes about 2.19 hours to complete the test of all (for example, 286 chips) IC chips 3a on one wafer 3. However, in this example, since 16 chips can be tested simultaneously as described above, the time required can be greatly reduced to about 12.9 minutes.
This is an epoch-making thing that cannot be considered at all with the conventional test equipment.

FIGS. 12 to 14 show another example of the present invention, and the basic structure and operation thereof are almost the same as those of the above-described first embodiment. The difference is
A total of 8 chips (CHIP1 to C
HIP8) are configured to be tested simultaneously.

That is, as shown in Figure 13 and Figure 14, respectively two sides of each pad 3b (V _SS side and the V _DD side plurality of probes 29 similar to the example described above in each IC chip 3a of CHIP1~CHIP8 s It is configured so that all the pads 3b are oriented perpendicularly to the contact surface of each of the pads 3b and simultaneously contact the contact surface of each of the pads 3b.

Therefore, also in this example, the probe 29
With the advantage that there is no need to worry about displacement when contacting the contact surface of the pad 3b on the IC chip 3a,
Also in this example, as described above, the eight chips (CHIP1 to CHIP
8) can be tested simultaneously, so that all (for example, 286 chips) I on a single wafer 3 are actually
It should be noted that the test of the C chip 3a can be completed in a very short time of about 20.8 minutes as in the above example.

FIG. 15 and FIG. 16 show another example of the present invention, and the basic configuration is almost the same as the example of FIG. 12 to FIG. The difference is that, as shown in FIG.
By using the flexible substrate 38 provided with the a, the wiring of the coaxial cable or the like on the board 37a of the probe card 37 is not required, and the probe 29
Is attached to a predetermined probe holder 36, inserted into an opening 35 of a board 37a of a probe card 37 and fixed to the board 37a, and the probe 29 is directly passed through a through hole 38b provided on a flexible substrate 38. Can be easily installed through.

Therefore, as described above, the predetermined wiring pattern 38
Since the flexible board 38 provided with a is used, it is not necessary to perform wiring or the like on the board 37a of the probe card 37 for connecting the probe 29 to the tester 30 side. Is easy to manufacture,
This is convenient for implementation. Further, by changing the flexible substrate 38, the wiring pattern can be easily changed as appropriate, and the connection relationship between the probe 29 and the tester 30 can be set as appropriate. In addition, since a flexible material such as the flexible substrate 38 is used, multiple wiring is possible, which leads to an improvement in mounting density.

However, in this example, for the sake of explanation, the relays for disconnecting the V _DD pad and the V _SS pad of each IC chip 3a from the tester 30 side are not shown, but they are the same as those described above. It can be configured similarly. Reference numeral 39 in the figure denotes a reinforcing plate for holding the flexible substrate 38 on the board 37a, but is not shown in FIG.

FIG. 17 shows yet another example of the present invention, in which the plurality of probes 29 in each of the above-described examples are all directed perpendicularly to the contact surface of each pad 3b of the IC chip 3a. However, in this example, the probe 49
Are configured so that only the respective tip portions 49a are all directed perpendicularly to the contact surface of the pad 3b,
Other configurations are the same as those of the conventional probe 19.

Therefore, also in this example, similarly to the above-described example, each tip portion 49a of the probe 49 is configured so as to be all directed perpendicularly to the contact surface of each pad 3b with the IC chip 3a. This has the advantage that there is almost no need to worry about the displacement of the probe 49 when it comes into contact with the probe.In the case of this example, the design of the tip 49a of the probe 49 is slightly changed from the conventional one. Can be easily realized.

FIG. 18 shows an example in which pads 3b are located on four sides in the IC chip 3a, and is not shown. However, if the probe 29 in the above-described example is used, the pads 3b having the arrangement pattern shown in the figure are provided. The IC chip 3a can be easily configured so that multiple chips (for example, 16 chips as in the above-described example) can be simultaneously tested.

19 and 20 show the post 29 of the probe 29 described above.
This is an example in which short-circuiting between adjacent probes 29 can be prevented by covering c with an insulating cap 50. That is, as shown in the figure, the cable 21 is soldered to the post portion 29c of each probe 29 in the same manner as in the above-described example, and further, the post portion 29c is covered with the cap 50 together with the soldered cable 21. Cap 5 provided on post part 29c of adjacent probe 29
Bend 0 left and right alternately.

Although the present invention has been described above, the above-described example can be further modified based on the technical idea of the present invention.

For example, in the above-described example, the tip portions of the plurality of probes are configured to be completely perpendicular to the contact surface of each pad 3b of the IC chip 3a, but they are not completely perpendicular to the contact surface. The angle may be slightly shifted, or the angle may be slightly shifted from the vertical. Further, the material, shape, structure and the like of the probe may be variously changed, for example, the pad 3b of the probe 29 described above.
As means for maintaining the contact pressure on the surface, an appropriate means having elasticity other than the spring 31 may be used. In addition, other components can be variously modified.

In the above-described example, an example in which 16 chips and 8 chips are tested at the same time has been described. However, by configuring the probe 29 and the like, 24 wafers and 32 chips as well as one wafer can be simultaneously tested. Testing can be performed at the same time. Also, as in the example of FIG.
If a probe card having a probe 29 configured for simultaneous measurement of multiple chips is used for an IC chip 3a having a pad 3b on one side, a probe card having a pad 3b on two sides can be used. And a highly flexible wafer test can be performed. Further, for example, the chuck 47 itself on which the wafer 3 is adsorbed is configured to be rotated, or the probe card provided with the probe is configured to be rotatable, so that an appropriate probe card can be easily replaced without having to replace the probe card or the like. Testing of wafers can be performed.

In each of the above examples, each probe is configured to contact each pad 3b of the IC chip 3a at the same time.
For example, it is also possible to use a suitable selecting means such as a plunger solenoid or the like so that only a predetermined probe among the probes is selectively brought into contact with the pad.

In each of the above-described examples, the present invention is applied to the test of the IC chip. However, the present invention may be applied to the test of other elements.

F. Advantageous Effects of the Invention As described above, according to the present invention, at least each of the tips (for example, the above-described tips 29a, 49a) of all of the plurality of contacts (for example, the above-described probes 29, 49) is an element such as an IC chip. Since it is configured to be directed substantially perpendicular to the contact surface such as a pad, the tip portion does not obliquely contact the contact surface unlike a conventional probe or the like. Therefore, it is possible to provide a highly reliable device test apparatus without displacement of the contact with respect to the contact surface. In the device testing apparatus of the present invention,
When testing multiple IC chips on a wafer simultaneously,
When an IC chip is detected, the relay switch corresponding to the V _DD pad and V _SS pad of the defective chip is turned off, so that the tester cannot perform the test because the predetermined voltage is not sufficiently supplied from the tester to other normal IC chips. The problem of disappearing can be prevented.

[Brief description of the drawings]

1 to 20 show an embodiment of the present invention. FIG. 1 is a perspective view of a probe card constructed so that 16 chips according to the present invention can be tested at the same time, and FIG. FIG. 3 is a partially cutaway perspective view, FIG. 3 is a cross-sectional view of a main part showing a probe card and a prober device around the probe card along the line III-III in FIG. 1, and FIG. 4A is an internal structure of the probe and the probe is an IC. FIG. 4B is a cross-sectional view of a main part showing a state before contacting a pad of a chip, FIG. 4B is a cross-sectional view of a main part showing a state after the probe comes into contact with a pad of an IC chip, and FIG. FIG. 6 is a schematic plan view for explaining that each pad on one IC chip is connected to the tester side, and FIG. 6 illustrates that each probe is in contact with each pad on 16 IC chips. FIG. 7 is a schematic plan view showing an actual wafer. Plan view for explaining a procedure of performing a test by chromatography server apparatus, a schematic block diagram for FIG. 8 is for explaining a connection relationship between each probe and the tester, and FIG. 9 is V _SS pad with the tester-side Relay circuit diagram for relay to disconnect, Fig. 10 is mounting pattern diagram of the relay circuit, Fig. 11 is V
FIG. 12 is an external view of a relay for disconnecting the connection between the _SS pad and the tester, FIG. 12 is a perspective view of a probe card showing another example of the present invention, and FIG. 13 is a view taken along line XIII-XIII of FIG. FIG. 14 is a cross-sectional view of a main part showing a probe card along and a prober device around the probe card. FIG. 14 is a schematic diagram for explaining that pads and tester sides of eight IC chips are connected to each other via each probe. FIG. 15 is a sectional view of a main part showing a probe card according to another example of the present invention and a prober device around the probe card, FIG. 16 is an exploded perspective view of the probe card according to the example of FIG. 15, and FIG. FIG. 18 is a cross-sectional view of a main part of a probe according to another example of the present invention (however, the probe is omitted from cross-sectional hatching for convenience of explanation). FIG. 18 shows an example in which pads are provided on four sides of an IC chip. FIG. 19 is a schematic plan view, and FIG. 19 is a pair of probes adjacent to the probe. Perspective view showing a state of attaching a cap to prevent electrical shorts, FIG. 20 is a schematic perspective view showing a state of attaching the cap to all probes. 21 to 25 show a conventional example, and FIG. 21 is a sectional view of a main part showing a conventional probe card and a prober device around the probe card (a sectional view taken along a line XXI-XXI in FIG. 25 described later). FIG. 22A and FIG. 22B are cross-sectional views of a main part for explaining the displacement of the conventional probe with respect to the pad surface of the IC chip (however, for the sake of explanation, diagonal lines representing the cross section are omitted from the probe). FIG. 23 is a perspective view of a main part of the probe for explaining how the tip is reduced due to displacement of the probe with respect to the pad, and FIG. 24 is each pad of 16 IC chips by a conventional probe. FIG. 25 is a schematic plan view for explaining that it is impossible to make contact with the prober at the same time, and FIG. 25 is a plan view of the prober device. In the reference numbers shown in the drawings, 1 ... prober device 3 ... wafer 3a ... IC chip 3b ... pads 19, 29, 49 ... probes 19a, 29a, 49a ... tips 10, 20 ... head stage 21 Coaxial cable 26, 36 Probe holder 27, 37 Probe card 30 Tester 47 Chuck RL1 to RL36 Relay

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 1/073 G01R 31/28 H01L 21/66

Claims (1)

(57) [Claims] 1. A plurality of contacts which respectively substantially vertically contact a power supply pad and a signal pad of a semiconductor chip in a one-to-one correspondence, and the power supply pad is provided to a tester for testing the semiconductor chip. A switch means and a first wiring connected in series for electrical connection through the corresponding contact, and the signal pad is electrically connected to the tester through the corresponding contact. A plurality of unit test sections each including a second wiring for connection, and a corresponding contact of each of the plurality of unit test sections is brought into contact with each pad of a plurality of semiconductor chips formed on a semiconductor wafer; When a plurality of semiconductor chips are simultaneously tested and a defective semiconductor chip is detected, the switch means corresponding to the power supply pad of the defective semiconductor chip is opened to open the defective semiconductor chip. An element testing device that stops power supply to a semiconductor chip.