JPH04205426A - Method and device for processing data - Google Patents

Abstract

PURPOSE:To increase data processing system speed as a whole, by previously converting an instruction requiring access to a data memory into an instruction requiring no data memory access. CONSTITUTION:A 4-port memory 3 to be used also as a data memory and a code memory and a peripheral I/O equipment are connected to a processor 1 for processing a pipeline based upon an inputted instruction through a common data bus 2. Prior to at least one cycle from the input of an instruction to the processor 1, an instruction is inputted in parallel with the input of the instruction to the processor 1 and an instruction requiring data memory access is converted into an instruction requiring no data memory access and the converted instruction is written in the code memory constituted of the 4-port memory 3. Consequently the processing speed of the whole system is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a data processing method and apparatus thereof, and more specifically, to a processor that pipelines read instructions and a processor that stores instructions. - A data processing method and device suitable for a data processing system including a hard drive memory and a data memory for storing data, and in which a bus for instruction access by a processor and a bus for data access are not separated. Regarding.

<Prior art and problems to be solved by the invention> Conventionally, data processing systems have been configured to include a processor that processes read instructions in a pipeline, a code memory that stores instructions, and a data memory that stores data. Generally adopted. In addition, this data processing system includes a processor that employs a bus architecture (hereinafter referred to as Barbed architecture) in which buses are separated for instructions and data, and a system that employs a bus architecture in which buses are separated for instructions and data. Princeton architecture (hereinafter referred to as Princeton architecture) is broadly classified into systems that include processors that employ a bus architecture that is not based on the Princeton architecture.

Here, in a data processing system that includes a processor based on the Barbard architecture, code memory can be accessed even while data memory is being accessed by the processor, so data access is completed. Instruction access can be executed even before the MIP S (Me
ga-fnstrucLions Per 5econ
d) The value can be improved.

However, in data processing systems that include Princeton architecture processors, because the buses are not separated, code memory cannot be accessed while data memory is being accessed, and as a result, the system The overall processing speed, ie, the MIPS value, will decrease.

A data processing system including a Princeton architecture processor will be described in more detail with reference to FIGS.

FIG. 11 is a block diagram showing an example of the configuration of a data processing system, which includes a data port of a processor (71) capable of pipeline processing of read instructions, and a static random access memory (hereinafter abbreviated as SRAM). a data memory (72) consisting of a dynamic random access memory (hereinafter abbreviated as DRAM), a code memory (73) consisting of a dynamic random access memory (hereinafter abbreviated as DRAM), and various input/output devices (hereinafter abbreviated as Ilo) (74). They are connected by a common data bus (75). Then, the address read from the address port of the processor (71) is temporarily held in the address register (76), and the contents of the address register (76) are directly stored in the data memory (
72) to perform data memory accesses. In addition, the contents of the address register (7B) are supplied as they are to the row address comparator (77), and after being held in the - hour register (78), they are supplied to the row address comparator (77). It is determined whether or not the lower address has changed, and this determination result is supplied to the DRAM control circuit (79) to generate a negative logic row address strobe signal (hereinafter referred to as RAS) for the code memory (73).
signal) and a negative logic column address strobe signal (hereinafter abbreviated as CAS signal). Further, the address output from the address register (76) is separated into a row address and a column address and is supplied to the multiplexer (80).
One of them is selected in response to a control signal output from the RAM control circuit (79) and supplied to the code memory (73).

Furthermore, a time-up signal from a timer (81) that defines the data processing interval is supplied to the DRAM control circuit (79), which in turn controls the code memory (79).
73).

Note that the code memory (73) is accessed in high-speed page mode;
The access time is set to within one cycle of the processor (7). Second, instruction fetching by the processor (71) can be stopped during the refresh period of the code memory (73).

The operation of the processor in the data processing system having the above configuration is as shown in FIGS. 12 and 13.

FIG. 12 shows processing that does not involve access to the data memory (72).
Fetching instructions from the controller, decoding the instructions, executing the instructions, and writing the execution results to internal registers is executed in this order in one clock cycle, and the same processing is performed for the next instruction at a timing one clock cycle later. Do this. Therefore, this is equivalent to fetching an instruction, decoding the instruction, executing the instruction, and writing the execution result to an internal register in one clock cycle, thereby achieving high-speed processing.

However, if data read access from the data memory (72) is required, the L
IOP processing of one cycle in one clock is interposed between the execution cycle of the OAD instruction and the write cycle, and the LOAD
If there is a data dependency between an instruction and the next instruction, the instruction execution process will be delayed by two clock cycles from the decoding of the next instruction, and two clock cycles will be delayed from the next instruction fetch.
The decoding process is delayed by a tarok cycle.

Therefore, data is stored until the subsequent instruction fetch.
code memory (73) for two clock cycles.
You will not be able to access the .

As a result, each time an instruction that requires access to the data memory (72) is executed, the code memory (73) cannot be accessed for two clock cycles, resulting in a reduction in processing speed. be.

Furthermore, when performing write access to the data memory (72), the code memory (73) cannot be accessed for just two cycle clocks, resulting in an inconvenience in that the processing speed decreases. .

<Object of the invention> This invention was made in view of the above problems,
In a data processing system using a Princeton architecture processor, a data processing method and its method are provided to prevent the overall processing speed from decreasing even when instructions requiring access to data memory are executed or intervened. The purpose is to provide equipment.

Means for Solving the Problems> In order to achieve the above object, the data processing method of the present invention is such that both the code memory and the data memory are composed of multi-port memories, and The processor also fetches instructions at least one cycle in advance in parallel with the instruction fetch by the processor, and transfers instructions that require data memory access to the data memory.
This method converts the instruction into an instruction that does not involve access and writes it into the code memory.

In order to achieve the above object, the data processing device of the present invention includes both the code memory and the data memory as multi-port memories, and the data processing device is configured such that both the code memory and the data memory are multi-port memories, and the data processing device is configured such that both the code memory and the data memory are composed of multi-port memories, and the data processing device is configured such that both the code memory and the data memory are composed of multi-port memories. an instruction capture unit that captures an instruction in parallel with the instruction capture; an identification unit that identifies whether or not the captured instruction is an instruction that involves data memory access;
Based on the identification result from the discriminating means indicating that the instruction involves data memory access,
and an instruction conversion means for converting an instruction requiring access into an instruction that does not involve data memory access and writing it into the code memory.

In the data processing device of the third aspect of the invention, the instruction converting means converts an instruction requiring data memory access into the data memory.
It has a table for converting to instructions that do not involve access.

A data processing device according to a fourth aspect of the present invention includes specific instruction detection means for detecting instructions and branch instructions that change the contents of data memory during instruction conversion; The method further includes a control means for invalidating the change process.

<Operation> With the data processing method described above, in a data processing system including a processor of Printo architecture and code memory and data memory consisting of at least one of DRAM, at least one The code is configured with multi-port memory by fetching instructions in parallel with the instruction fetching by the processor before the cycle, and converting instructions that require data memory access into instructions that do not involve data memory access. Since it writes to memory, the processor fetches and executes an instruction that does not involve data memory access and is equivalent to the above instruction, rather than an instruction that requires data memory access, resulting in pipeline processing. This means that the processing speed of the entire system, that is, the MIPS value, can be increased.

If the data processing device has the above configuration, Princeton
architecture, at least one of which is a DR
In a data processing system including a code memory and a data memory consisting of an AM, an instruction is fetched by an instruction fetching means in parallel with the instruction fetching by the processor at least one cycle before the instruction fetching by the processor, and the fetched instruction is converted into data. - The identification means identifies whether the instruction involves memory access or not, and if it is identified as an instruction that requires data memory access, the instruction conversion means converts the corresponding instruction to the data memory.・Since the processor converts the instruction to an instruction that does not involve access and writes it to the code memory configured with multi-port memory, the processor converts the instruction to an instruction that involves data memory access, rather than an instruction that requires data memory access. The processing speed of the entire system, that is, the MI
PS value can be increased.

If the instruction conversion means has a table for converting an instruction that requires data memory access into an instruction that does not involve data memory access, the instruction conversion means can convert the instruction by referring to the table. Changes can be easily achieved.

Further, there is a specific instruction detection means for detecting instructions and branch instructions that change the contents of data memory during instruction conversion, and a control means for disabling instruction change processing based on an instruction detection signal from the specific instruction detection means. If a specific instruction is detected that affects other instructions by executing the instruction conversion or prevents the execution of the previously read instruction, the instruction conversion is disabled. Therefore, it is possible to achieve high-speed processing while maintaining processing reliability.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram schematically showing an embodiment of a data processing device according to the present invention, in which a processor (1) that performs pipeline processing on fetched instructions is connected to a processor (1) via a common data bus (2). , a 4-port memory (3) that also serves as data memory and code memory, and peripheral input/output devices (4) are connected. And processor (1)
A control unit (6) temporarily holds the address output from the address register (5) and supplies it to the 4-port memory (3), and performs a series of processes necessary for instruction conversion. We also supply This control unit (6
) to the 4-port memory (3
) so that the control unit (6) can access instructions in parallel with the memory access by the processor (1).

FIG. 2 is a block diagram showing the configuration of the control section (6),
A first control unit (6a) that determines whether or not instruction conversion may be performed, and a second control unit (6b) that actually performs instruction conversion.
) and a third control section (6c) for writing the converted instructions into the 4-port memory (3), and each control section is operated in a pipeline.

The first control unit (6a) uses an adder (6al) to add a constant value (for example, 3) indicating the number of cycles for prefetching instructions to the address output from the address register (5). The first cancel control unit (6a2) determines whether the read instruction is a 5TORE instruction, a branch instruction, or neither. If it is determined that it is any command, a cancel instruction signal is supplied to the second control section (6b) and the third control section (6c).

Conversely, if it is determined that it is not any instruction, the corresponding instruction is held in the register (6a3).

The second control unit (6b) extracts the address of the data memory using the data memory address extraction unit (6bl) based on the instruction held in the register (6a3), and stores the address in the 4-port memory (3). 4-port memory (
The data read out from the C port of 3) and the instructions held in the register (6a3) are converted to the instruction conversion table (
6b2) to convert an instruction that requires data memory access into an instruction that does not involve data memory access, and causes the register (6b3) to hold -time. Further, the data memory address extracted by the data memory address extraction unit (6bl) is supplied to the second cancellation control unit (6b4), and if it is equal to the access address by the processor (1), the address of the data memory extracted by the data memory address extraction unit (6bl) is supplied to the third control unit. A cancel instruction signal is supplied to (6c). Specifically, as shown in FIG.
) is temporarily held in the register (6b41), and the address of the data memory extracted by
) matches the address supplied to the A port of the 4-port memory (3).
2), and the determination result signal output from the comparator (6b42) and the write strobe signal for the A boat are supplied to the AND gate (6b43). Therefore, a cancel instruction signal is supplied to the third control section (6c) on condition that both addresses match and a write strobe signal for the A port is supplied.

The third control unit (6c) adds a constant value (for example, 1) to the address output from the address register (5) using an adder (6cl) and supplies the result to the four-port memory (3). Specify the write address. Then, the instruction held in the register (6b3) is rewritten by supplying it to the rewrite/save control unit (8c2), and it is determined whether storage is necessary or not. Only when necessary, the 4-port memory (3
) is supplied with the corresponding instruction to the D port.

The operation of the data processing device having the above configuration is as follows.

FIG. 4 is a timing chart showing instruction pipeline processing by processor (1) only. When instructions that do not involve data memory access are consecutive, instruction fetch, decode, execution, internal Writes to registers are executed with a delay of one clock cycle.

However, for example, when executing an instruction that requires read access to data memory, pipeline processing is necessary because the data memory is read from data memory and then written to internal registers following the execution cycle. will be disrupted. Note that T shown in FIG. 4 indicates the boundary between the processing timing before the conversion decision is made for the conversion target instruction and the processing timing after the conversion decision is made, and T depends on the pipeline configuration of the control unit (6). S indicates the number of cycles depending on the execution/planning of the processor (1).

In this timing chart, the instruction that involves reading from the data memory is J-3, so the fifth instruction
As shown in the figure, the instruction is fetched three cycles ago, converted into an instruction that does not involve data memory access in the next cycle, and then rewritten in the next cycle. As a result, the processor (1) takes in and processes the converted instructions, and since the converted instructions do not involve data memory access, they can be processed at high speed without disrupting pipeline processing. can be achieved.

FIGS. 6 and 7 are timing charts showing cases where No and S are different, and in this case as well, instructions that require data memory access are converted to instructions that do not involve data memory access. Since the processor processes the corresponding instruction only after the instruction is executed, it is possible to prevent disturbances in pipeline processing and achieve high-speed processing.

Figure 8 (AI) (A2), Figure 9 (AI) (A2) and Figure 1O are LOAD instruction, ADD instruction, 5
These are formats that indicate HIFT instructions, and instruction conversion will be specifically explained without reference to these formats.

For example, in the format shown in FIG. 8 (A2),
An instruction to read one word of data at data address 51mm13 is given, the address of register rsl that stores the read data is given by rO, and the memory contents at data address 51mm13 are H#000000A.
In the case of O, all you need to do is change the operand to ADD and 51mm13 to H#OAO in the format shown in FIG. 9 (A2), and you can obtain the same execution result as the LOAD instruction, and - Can be converted to instructions that do not involve memory access.

In addition, in the format shown in FIG. 8 (A2), the memory contents of data address 51mm13 are H#002.
28000, it is sufficient to instruct shift processing by setting operands OP and OP2 to 00 and 100, respectively, and setting 1mm22 to H#000114, and the same execution result as the LORD instruction can be obtained. , and can be converted into an instruction that does not involve data memory access.

However, if the instruction cannot be converted, an invalid dummy instruction is supplied to the rewrite/save control unit (6c2).

Furthermore, if any inconvenience occurs due to the above instruction conversion process, the instruction conversion process is canceled as follows.

That is, if the contents of the corresponding address of the data memory change during the cycle indicated by S, the execution result of the instruction after conversion and the execution result of the instruction before conversion will no longer match, and
If a branch instruction exists in the cycle indicated by , the flow of instructions changes significantly, and instruction prefetching becomes invalid.

Therefore, when the first cancel control unit (6a2) detects the 5TORE instruction during the cycle indicated by J, it is obvious that the content of the data memory is changed, so the second control unit (6b) and third control section (6c)
A cancel instruction signal is supplied to invalidate the process.

Furthermore, when a branch instruction is detected, a cancel instruction signal is similarly supplied to invalidate the processing of the second control section (6b) and the third control section (6C).

Furthermore, the contents of the data memory change during the cycle indicated by the first control section (6a) and the second control section (6a).
It is permissible during the process of 6b), but the third
It is not acceptable for the contents of the data memory to change during processing by the control unit (6c).

Therefore, in such a case, the second cancel control section (6b4) generates a cancel instruction signal and cancels the third cancel control section (6b4).
The signal is supplied to the control unit (6C) to invalidate the processing of the third control unit (6c).

As is clear from the above explanation, instruction conversion can be performed only when it is possible and there are no inconveniences associated with changing the contents of data memory. 1) The number of instructions that must access data memory can be greatly reduced,
The processing speed of the data processing system as a whole can be increased.

As is clear from the above explanation, the number of cycles can be arbitrarily determined, but as the number of cycles increases, the possibility of intervening 5TORE instructions and branch instructions during the J cycle increases. It is preferable to set it as small as possible. Furthermore, the first cancellation control section (6a2)
Accordingly, a disturbance in pipeline processing caused by data memory access occurring during the J cycle is detected in advance, and a cancel instruction signal is supplied to the second control section (6b) and the third control section (6C). It is possible to omit the second cancellation control section (Bd4).

<Effects of the Invention> As described above, in the first invention, an instruction that requires data memory access can be converted in advance to an instruction that does not involve data memory access, and as a result, the processor pipe Since the instructions can be processed sequentially without disrupting the line, it has the unique effect of greatly increasing the processing speed of the data processing system as a whole.

The second invention also allows instructions that require data memory access to be converted in advance to instructions that do not involve data memory access, and as a result, the instructions can be sequentially converted without disturbing the pipeline of the processor. This has the unique effect of greatly increasing the processing speed of the data processing system as a whole.

The third invention has the unique effect that it is possible to easily convert instructions by referring to a table, and that it is possible to speed up the instruction conversion process and simplify the configuration.

The fourth invention is that the instruction conversion can be disabled when there is a possibility that the initial result will not be obtained due to the instruction conversion, so that the processing as a whole data processing system can be performed while ensuring the accuracy of data processing. It has the unique effect of greatly increasing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing an embodiment of the data processing device of the present invention, FIG. 2 is a block diagram showing the configuration of the control section in detail, and FIG. 3 is an example of the configuration of the second cancellation control section. FIGS. 4 and 5 are diagrams for explaining an example of the instruction conversion process; FIGS. 6 and 7 are diagrams for explaining another example of the instruction conversion process; FIG. 8 (AI) A2), Figure 9 (AI) (A2) and Figure 1O are the LOAD instruction, ADD instruction, and SH, respectively.
FIG. 11 is a block diagram showing a conventional example of a data processing system; FIGS. 12 and 13 are timing charts illustrating pipeline processing of a processor in the conventional example. (1)...processor, (2)...data bus,
(3)...4-port memory, (6)...control unit, (
6a)...First control unit, (6al)...Adder, (
6a2)...first cancellation control section, (6b)...
Second control unit, (6b2)...Instruction conversion table, (6
b4)...Second cancellation control section, (6C)...Third control section, (6c2)...Rewrite/save control section Patent applicant
Daikin Industries, Ltd.

Claims (1)

[Claims] 1. A processor that pipelines read instructions (
1), a code memory (3) for storing instructions, and a data memory (3) for storing data, including a bus (2) for instruction access by the processor (1) and a bus (2) for data access. In a data processing system in which a bus (2) of The processor (
The feature is that the instruction is fetched in parallel with the instruction fetch by step 1), and an instruction that requires data memory access is converted into an instruction that does not involve data memory access, and the converted instruction is written into the code memory (3). Data processing methods. 2. A processor that pipelines read instructions (
1), a code memory (3) for storing instructions, and a data memory (3) for storing data, including a bus (2) for instruction access by the processor (1) and a bus (2) for data access. In a data processing system in which a bus (2) of Instruction fetching means (6) (6a) (6a1) fetching an instruction in parallel with instruction fetching by a processor at least one cycle before fetching, and whether the fetched instruction is an instruction that involves data memory access. Based on the identification results from the identification means (6), (6a), and (6a2) that identify whether or not the instruction instruction conversion means (6) (6b) (6) for converting an instruction requiring data memory access into an instruction that does not involve data memory access and writing it into the code memory (3);
c) A data processing device characterized by comprising (6c2). 3. The instruction conversion means (6) (6b) (6c) (6c2) has a table (6b2) for converting an instruction requiring data memory access into an instruction that does not involve data memory access. A data processing apparatus according to claim 2, wherein the data processing apparatus comprises: 4. Specific instruction detection means (6a2) (6b4) for detecting instructions and branch instructions that change the contents of the data memory (3) during instruction conversion;
) (6b4) control means (6a2) (6b4) (6b4) for disabling the command change processing based on the command detection signal from (6b4)
1) (6b42) (6b43).