JPH03269743A - High-reliability cache control system - Google Patents

Abstract

PURPOSE:To improve the reliability of cache control in a simple cache circuit using an SRAM with comparator by generating a parity bit from a partial address of an access address. CONSTITUTION:An address A04 to A15 is inputted as the address input of an SRAM module 2-1, and an address A16 to A31, the parity bit generated from the address A16 to A31 by a parity bit generating circuit 3, and effective bits are inputted as the data input and are written. The value read out by inputting the address A04 to A15 to the input address of the SRAM module 2-1 and the data input consisting of the address A16 to A31, the parity bit, and effective bits are inputted to a comparator 2-2 at the time of discriminating hit/mishit, and hit is discriminated in the case of coincidence between them, but mishit is discriminated in the case of disaccord. Thus, the reliability of cache control is improved in the simple cache circuit using an SRAM 2 with comparator.

Description

[Detailed Description of the Invention] [Summary] Regarding a highly reliable cache control method that controls cache with high reliability, the present invention aims to improve the reliability of cache control in a simple cache circuit using an SRAM with a comparator. Equipped with an SRAM with a comparator consisting of an SRAM module and a comparator, a parity bit generation circuit that generates a parity bit, and a cache data RAM that writes data and outputs when hit, an address is input to the SRAM module of the SRAM with a comparator when accessed. The value read by inputting a part of the access address as , the remaining address of the access address, the parity bit generated by the above parity bit generation circuit from the remaining address, and multiple valid bits. is input to the comparator, and when there is a match/mismatch, it is determined as a hit/miss. On the other hand, when there is a miss, the data read from the main storage device etc. is written to the cache data RAM, and the SRAM module of the SRAM with the comparator is written. The configuration is such that a partial address of the access address is input as an address input, and the remaining address of the access address, a parity bit, and a plurality of valid bits are input as data input to write.

[INDUSTRIAL APPLICATION FIELD 2] The present invention relates to a highly reliable cache control method for controlling Canon units with high reliability.

[Prior art and problems to be solved by the invention] Conventionally, as shown in FIG.
The comparison circuit 23 compares the value read from the AM 22 and the address to be read accessed, and when they match (hit), the data is read from the cache data RAM 25 and transferred to the MPU 21.

At this time, the cache tag RAM 22 and comparison circuit 23
Figure 5 (b) SRAM 27 with comparator, which has the function of
It is possible to simplify the circuit configuration by using However, when this SRAM 27 with a comparator is used, there is a problem in that it is not possible to add redundant bits (such as a parity bit) to improve reliability.

The present invention aims to improve the reliability of cash control in a simple cache circuit using an SRAM with a comparator.

[Means to solve problems]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, SRAM2 with comparator is SRA
It is composed of an M module 2-1 and a comparator 22.

Parity bit generation circuit 3 is a circuit that generates parity bits.

The cache data RAM 5 is used to write data, read the data when hit, and output the data to the access source.

[Effect]

As shown in FIG. 1, the present invention provides a value read out by inputting a part of the access address as an address input to the SRAM module 2-1 of the SRAM with comparator 2 at the time of access, and the remaining address of the access address. Parity bit generation circuit 3 from the remaining address
The parity bit generated by While writing to RAM5, S R with comparator
A part of the access address is input manually to the SRAM module 21 of A M 2 as an address input, and the remaining address of the access address is input as data input,
The parity bit and multiple valid bits are manually written.

Therefore, in a simple cache circuit using the SRAM 2 with a comparator, it is possible to improve the reliability of cache control.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 to 4.

In FIG. 1(A), an MPU (microprocessor) 1 performs various processes and is an access request source here.

The SRAM with comparator 2 includes an SRAM module 2-1 and a comparator 2-1, as shown in FIG.
2 (described later).

The parity bit generation circuit 3 is an SRAM with a comparator.
This circuit generates a parity bit of an address to be inputted to the second data input, and generates an odd/odd parity node of, for example, 1 bit in 8 bits.

The response control circuit 4 outputs a response signal to MP when there is a notification of a match signal (notification that an E throat has been performed) from the SRAM with comparator 2 in response to a notification of a start signal from the MPUI.
It notifies the UI and causes it to fetch data output from the cache data RAM 5 to the data bus.

The cache data RAM 5 is a memory that stores data in the event of a miss, reads out the data in the event of a hit, and outputs the data to the access request source.

The main storage device 6 is a large-capacity memory that stores data.

In FIG. 1(b), the SRAM module 21 has M
A part of the access address from the PUI is used as an address input, the remaining address of the access address, the parity 5's generated from this remaining address by the parity bit generation circuit 3, and a plurality of valid bits are used as data input to generate the data. It stores the input, and uses a part of the access address from the MPUI as an address input to read the value and input it to the comparator 2-2.

The comparator 2-2 compares the value read from the SRAM module 21 with the remaining address of the access address, the parity bit generated by the parity bit generation circuit 3 from this remaining address, and a plurality of valid bits, and determines whether there is a match ( This is to determine whether the information is correct or inconsistent.

Next, using Figure 2,
The operation of AM2 will be explained. Here, from address AO to A
31 and 32, the case where data is accessed in a 16 (2') height block will be explained.

FIG. 2 ↓ Here, AO4 to A15 are input as address inputs of the SRAM module 2-1, A16 to A31 are input as data inputs, and valid bits of parity 5 and 2.2 bits are input and written. As a result, when data is written to the cache data RAM 5 at the time of a miss, the written data is stored in the SRAM module 2-1 of the SRAM with comparator 2 as a hit/hit.
Information for determining a miss can be stored with high reliability. Then, when determining hits/misses, S
The values read by inputting the access addresses AO4 to A15 to the input addresses of the RAM module 2-1 and the access addresses A16 to A31 . The 2-bit parity bit and 2-bit valid bit generated from the access addresses A16 to A31 are output to the comparator 2-
2, and when the two match, it is judged as a hit, and when they do not match, it is judged as a miss, and it is judged as a hit. Here, the reliability of addresses 16 to A31 is enhanced by parity bits. In addition, the valid bit is normally set to "11" to provide redundancy, and it is determined that it is a hit only when both are "1", and when either one is O and 7, it is determined as a miss and the data is stored in the main memory 6. We are leading the data and increasing reliability.

By the way, effective Binoro, when using a single processor, normally "11" is written. When expanded to a multiprocessor system, the valid bit is set to 0 to invalidate the data corresponding to the entry.

Next, in accordance with the order shown in the flowchart of FIG. 3,
The operation of the groove bottom in FIG. 2 will be explained in detail.

In FIG. 3, in (■), the MPUI issues a REIT access.

@ determines whether it is a hint or not. This is the value read out by outputting the read address to the address bus at ■, manually inputting AOA to A15 into the address input of the SRAM module 2-1 of the SRAM with comparator 2, and
The remaining A16 to A31, these A16 to A31
2-bit parity bit, valid bit °
11'' are respectively input to the comparator 2-2, and the two are compared to determine whether they match (hit) or not.

If YES (if there is a match, if there is a hit),
As shown in (2), it is determined that a hint has been given, and the data read from the cache data RAM 5 is transferred to the MPUI in O, and the MPU accepts the data in [phase].

On the other hand, in the case of NO (in case of mismatch, in case of mishit), the main memory bag N6 is accessed with 0, the data read in [phase] is transferred to the MPUI, and step 2, [phase] is performed. This will be explained below.

[Phase] is determined to be a miss at @N○, so the data read from the main memory 6 is transferred to M via the data bus.
When transferring to PUI, cache data RAM is also
Write in 5. At this time, as shown in Figure 1 (a), M
With AO2 to A15 of the read addresses sent from the PUI to the address bus being input, the data sent to the data bus is transferred to the cache data RAM 5.
write to.

[Phase] writes AOA to A15 as addresses, A16 to A31.2 parity bits, and valid bits "11" as data to the SRAM 2 with a comparator. As a result, it is stored that the data at the read address has been written to the cache data RAM 5.

O indicates content determined to be a hint by @YES. This is an SRAM using AOA to A15 as the input address.
The value read from module 2-1 and A16 to A
31, the comparator 2-2 compares the 2-bit parity bit generated from A16 to A31 with the valid bit "11", and the two match (hint).

[Phase] inputs AO2 to A15 as addresses into the cache data RAM 5, reads the data, and reads the data from the cache data RAM 5.
Transfer to PUI. Then, MPU1 receives this with @.

Next, the operation of the configuration shown in FIG. 1(a) will be explained using the fourth operation waveform chart.

(1) When the MPUI performs read access to the main memory device 6, a start signal is sent to the response control circuit 4 at timing T.
It also outputs the read address to the address bus. Then, input AOA to A15 of the read address to the address input of SRAM 2 with comparator, and input the parity bits of A16 to A31.2 bits and valid hit "11" to SR with comparator.
Manual input/output of AM2 data. Then, when they match as described above (when they match when checked at timing T2), the response control circuit 4 is notified of the match signal from the comparator 2-2.

(2) When the matching signal is notified to the response control circuit 4,
A response signal is sent to the MPUI, and data read from the cache data RAM 5 is sent to the data bus. The MPUI accepts the response signal at timing T, samples the data, and terminates the hash cycle at the same time.

(3) If they do not match, as described above, transfer the data read from the main memory 6 to the MPUI and write it to the data RAM 5, and
16 to A31.2 bits of parity bit and valid bit "11" are collectively set to S of SRAM2 with comparator.
Write to RAM module 21.

〔Effect of the invention〕

As explained above, according to the present invention, a part of the access address is input to the address input of the SRAM 2 with a comparator, and the remaining address of the access address, a parity bit, and a plurality of valid bits are input to the data input. , SRA with the corresponding comparator when accessing
A configuration is adopted that determines a hit/miss when the value read inside M2 and the input access address, parity bit, and multiple valid bits match/mismatch, making it easy to use with SRAM2 with a comparator. It is possible to improve the reliability of cache control in Canon Yu circuits.

[Brief explanation of drawings]

FIG. 1 is a structural diagram of one embodiment of the present invention, FIG. 2 is a diagram explaining the operation of the SRAM with a comparator according to the present invention, FIG. 3 is a flowchart explaining the operation of the present invention, and FIG. The waveform diagram in FIG. 5 is an explanatory diagram of the prior art. In the figure, l is MPU (microprocessor), 2 is SRAM with comparator, 2-1 is SRAM module, 2
-2 is a comparator, 3 is a parity bit generation circuit, 4
5 represents a response control circuit, 5 represents a cache data RAM, and 6 represents a main storage device.

Claims (1)

[Claims] A highly reliable cache control method for controlling a cache with high reliability, comprising: an SRAM module (2-1) and a comparator (2-1);
-2) with a comparator, a parity bit generation circuit (3) that generates a parity bit, and a cache data RAM (5) that writes data and outputs when there is a hit. SR of SRAM with comparator (2)
A value read by inputting a part of the access address as an address input to the AM module (2-1), the remaining address of the access address, and the parity bit generation circuit (3) generated from the remaining address. The parity bit and multiple valid bits are input to the above comparator (2-2), and when they match/mismatch, it is determined as a hit/miss hit.On the other hand, when there is a miss hit, the parity bit and multiple valid bits are input to the comparator (2-2). While writing data to the cache data RAM (5), input a part of the access address as an address input to the SRAM module (2-1) of the SRAM with comparator (2), and input the rest of the access address as a data input. A highly reliable cache control method characterized in that the address, parity bit, and multiple valid bits are input and written.