JPH04204830A - Display device - Google Patents

Abstract

PURPOSE:To eliminate the faulty due to the shift of the pattern position caused by a photomask and an exposure device by forming a self-pattern (gate wiring, drain wiring, source electrode) formed a display electrode on the substrate as a mask. CONSTITUTION:As a resist pattern is stripped off by using a lift-off method the display electrode 8 is formed. In this case, a semiconductor film 4 and an impurity semiconductor film 5 function as a spacer for lift-off use, so a film thickness of the display electrode material 80 is necessary to be thinner than the film thickness of the semiconductor film 4 and the impurity semiconductor film 5. In this step, on the region being not light-shielded with the gate wiring 20, 20,..., the drain wiring 60, 60,..., and the source electrode 7, the display electrode material 80 remains and on the display region, the display electrode is formed with high definition and in a minute interval. Besides a combined electrode 9 electrically connecting the source electrode 7 and the display electrode 8 is formed. Hence the faulty due to the shift of the pattern position is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a display device. For example, it relates to a manufacturing method and structure of a liquid crystal display device using liquid crystal.

(b) Prior art In recent years, thin film transistors (hereinafter referred to as TPTs) operating as switching transistors have been coupled to each display electrode of a large number of picture units arranged in a matrix.
Active matrix display devices using PT as a driving circuit have been developed.

Since this device can provide very clear display, C
It is attracting attention as a flat-panel display device that can replace RT [see the article ``Flat panel display aimed at displaying documents and images'' in Nikkei Electronics (January 2, 1984)].

FIG. 22(a) shows a plan view of each pixel of a TPT array in a conventional active matrix type liquid crystal display device, and FIG. 22(b) shows a cross-sectional view taken along line BB' at the TFT position.

These TPTs in the same figure are attached to one insulating substrate 1 of the liquid crystal cell.
Ohmic contacts are made to each of the gate electrode 2 formed on the top and forming a part of the gate wiring 20, the gate insulating film 3 provided on the entire surface of the substrate, the islanded semiconductor film 4, and the source and drain positions of the semiconductor film. It forms a so-called inverted stagger type consisting of a laminate of an impurity semiconductor layer 5, a source electrode 7, and a drain electrode 6, and this source ti7
A display electrode 8 for each pixel is coupled to the drain electrode 6, and the drain electrode 6 is coupled to a drain wiring 60 for supplying a display signal.

(c) Problems to be Solved by the Invention Each electrode of the TFT array of the above-mentioned active matrix display device is formed by finely processing the material for forming the electrode by photoetching after depositing the material. In that case,
The processing accuracy of wiring patterns is determined by the capabilities of the photomask and exposure equipment. Generally, the total pitch error of current photomasks is ±1 μm, and the alignment error of exposure equipment is ±1 μm.
1 μm, and the formation position accuracy of a wiring pattern processed using both is at least ±2 μm. Therefore, ±
A pattern position shift of 2 μm, 0 to 4 μm occurs. For this purpose, the area occupied by the TPT display electrode (aperture ratio)
In order to avoid overlapping the display electrode pattern with the wiring pattern, it is necessary to design the display electrode pattern with a dimension interval that takes into account the amount of pattern position shift.

When the image size becomes smaller, for example, when manufacturing a display device such as an ultra-high-definition liquid crystal display device compatible with high-definition vision of about 30 to 50 μm square, there is a disadvantage that the aperture ratio in a unit element is significantly reduced due to the above-mentioned pattern design. was occurring. That is, a decrease in the aperture ratio causes the display inner surface to become dark as a whole, resulting in a disadvantage that the display quality is degraded.

(d) Means for Solving the Problems The display device of the present invention includes forming a gate wiring on a transparent substrate, sequentially depositing a gate insulating film and a semiconductor film, and then forming a drain wiring on the semiconductor film. By exposing from the back of the board,
A resist pattern is formed on the region shielded from light by the gate wiring and the drain wiring, the semiconductor film is etched using the resist pattern and the drain wiring as a mask, a conductive material for forming a display electrode is deposited, and the resist pattern is etched using the resist pattern and the drain wiring as a mask. The display electrode is manufactured by peeling off the pattern using a lift-off method, thereby leaving the conductive material for forming the display electrode in the area not shielded from light by the gate wiring and the drain wiring, thereby forming the display electrode.

Further, in the display device of the present invention, a gate wiring is formed on a transparent substrate, a gate insulating film and a semiconductor film are sequentially deposited, a drain wiring is formed on the semiconductor film, and the A resist pattern is formed on the area shielded from light by the gate wiring and the drain wiring, the semiconductor device is etched using the resist pattern and the drain wiring as a mask, and a transparent conductive material for forming a display electrode is deposited, and then the semiconductor device is etched from the back side of the substrate. A method of forming display electrodes in areas not shielded from light by gate wirings and drain wirings by etching the transparent conductive material using as a mask a resist pattern formed in areas not shielded by gate wirings and drain wirings by exposure to light. It is manufactured.

Further, the display device of the present invention includes a plurality of gate wirings having a uniform width formed on a light-transmitting substrate, a gate insulating film formed on the gate wirings, and a gate wiring formed on the gate insulating film. a semiconductor film formed into an island with the same width at most, and a plurality of drain wirings with uniform widths intersecting with the gate wiring;
a source electrode that faces a drain electrode region that is locally provided on the drain interconnection with a fixed distance therebetween, with a gate insulating film interposed on the gate electrode that is locally provided on the gate interconnection; The display electrode is arranged in a region surrounded by the gate wiring and the adjacent drain wiring and is electrically connected to the source electrode.

(E) Function According to the present invention, since display electrodes are formed in a self-aligned manner using the wiring pattern formed on the substrate as a mask, errors caused by conventional photomasks and exposure equipment can be eliminated, and each wiring The display electrode spacing can be formed at a very small spacing with respect to the pattern. Therefore, it is possible to obtain a display device in which the display electrode formation area, that is, the aperture ratio is greatly increased.

(F) Example (Example 1) FIG. 1 shows a plan view of a pixel unit of a TPT array of an active matrix display device obtained by the present invention.

A plurality of gate wirings 6 with uniform width formed on a transparent substrate
0.60. ..., the gate insulating film formed on the gate wiring, and the gate wiring 60,60 on the gate insulating film.
A semiconductor film 4 formed into an island with at most the same width for...
and a plurality of drain wirings 20.20. with uniform width intersecting the gate wiring. and gate electrodes 60, 60, locally provided on the gate wiring. . . . The source electrode 6 faces the drain electrode region locally provided in the drain region 20. 20 through the gate insulating film at a constant distance, and the adjacent gate. Wiring 60
．． 60. ... and adjacent drain wiring 20.20.
A method for manufacturing a display device having a structure including a display electrode 8 arranged in a region surrounded by . . . and electrically connected to the source electrode 6 will be described with reference to the drawings.

Figures 2 (i) to (vii) are cross-sectional views of each manufacturing process along the line A-A' (TFT section) in Figure 1, and B in Figure 1.
- The cross-sectional diagram of each manufacturing process of the “B” line (gate wiring part) is shown in the third section.
Figures (i) to (vii) show cross-sectional views of each manufacturing process along line c-c' (drain wiring part) in Figure 1, and Figure 4 (i).
) to (vii) and will be explained accordingly.

1st process Fig. 2(i), Fig. 3(i), Fig. 4 i)]
Mo and Cr are placed on a transparent substrate 1 made of glass.

A gate wiring 20 locally provided with a gate electrode 2 made of W, Ti, Ta, A1, etc. is formed.

2 steps [Figure 2 (ii), Figure 3 (i), Figure 4 (ii)
) A gate insulating film 3 made of silicon nitride film or tantalum oxide, etc., a semiconductor film 4 made of amorphous silicon or polysilicon, etc., and an impurity semiconductor film 5 for the purpose of making ohmic contact with the metal film are sequentially formed using a P-CVD device or the like. Form.

3rd step (Figure 2 (iii), Figure 3 (iii), 4th step)
Figure (iii)] M o + Cr + W * T
A drain wiring 60 locally provided with a drain electrode 6 made of 1*T a + A I or the like and a source electrode 7 are formed.

4th step (Figure 2 (iv), Figure 3 (iv), Figure 4 (
iv) Apply a positive resist, and form a resist pattern 30 on the region shielded from light by the gate wiring 20 where the gate electrode 2 is locally provided, the drain wiring 60 where the drain electrode 6 is locally provided, and the source electrode 7. It is formed by back exposure, and the semiconductor film 4 and impurity semiconductor film 5 are etched.

5th process (Figure 2 (V), Figure 3 (v), Figure 4 (■))
A display electrode material 80 such as ITO, SnO, etc. is deposited.

6th process [Figure 2 (f), Figure 3 (φ), Figure 4 (vi)
1. The display electrode 8 is formed by peeling off the resist pattern using a lift-off method. In this case, since the semiconductor film 4 and the impurity semiconductor film 5 function as a spacer for lift-off, the film thickness of the display electrode material 80 needs to be smaller than the film thickness of the semiconductor film 4 and the impurity semiconductor film 5. In this step, the gate wiring 20.20. The display electrode material 80 remains in a region not shielded from light by the drain wirings 60, 60, and the source electrode 7, and display electrodes are formed in this display region with high precision and at minute intervals. - On the other hand, in the terminal area, in order to avoid short circuits between the terminals when making a TAB connection, for example, cover only the terminal area with metal masonry to prevent the display electrode material 80 from accumulating, or etch the display electrode material 80 after lift-off. Needs to be removed.

Seventh step (FIG. 2(vii), FIG. 3(vii), FIG. 4(vii)) A coupling electrode 9 that electrically connects the source electrode 7 and the display electrode 8 is formed. Thereafter, the semiconductor film 4 and impurity semiconductor film 5 on the gate line are partially etched to form islands. This etching (island formation) of the semiconductor film 4 and the impurity semiconductor film 5 may be performed before the coupling electrode 9 is formed.

Finally, the impurity semiconductor film 5 in the channel portion is removed by etching using the drain electrode 6 and source electrode 7 as masks.

Furthermore, in this step, when forming the coupling electrode 9, if an auxiliary drain wiring 90 that matches the drain wiring 60 is simultaneously formed on the drain wiring 60, disconnection of the drain wiring 60 can be prevented (Fig. 1 A-A ' line is shown in FIG. 5, and line c-c' in FIG. 1 is shown in FIG. 6].

As described above, according to the present invention, the display electrode is formed using the self-pattern (gate wiring, drain wiring, source electrode) formed on the substrate as a mask, so that pattern position shift caused by the conventional photomask and exposure device is avoided. Since defects caused by this can be eliminated and the spacing between the self-pattern and the self-pattern can be very small, the display electrode forming area can be maximized as a result. Further, by forming the display electrode by a lift-off method, a display electrode pattern is formed in the area where the foreign matter is present. Therefore, there is also the effect that short-circuit defects between the display electrode and the wiring pattern are less likely to occur.

<Example 2> Next, cross-sectional views of each manufacturing process of a second example of the present invention are shown in FIGS. 7, 8, and 9.

Cross-sectional views of each manufacturing process along line AA' (TFT section) in Figure 1 are shown in Figures 7(V) to (F), and BB' in Figure 1
The cross-sectional view of each manufacturing process along the line (gate wiring part) is shown in the 8th section.
Figures (v) to (vii) show cross-sectional views of each manufacturing process along the line CC' (drain wiring part) in Figure 1, and Figure 9 (V
) to (vii).

(i) to (iv) in FIGS. 7 to 9 are the same as (i) to (iv) in FIGS. 2, 3, and 4 of the first embodiment of the present invention, respectively, I will omit it here. The following description will be made with reference to FIGS. 7, 8, and 9.

Step 5 (Fig. 7 (V), Fig. 8 (v), Fig. 9 (v) Gate arrangement @ 20. 20...The upper semiconductor film 4 and impurity semiconductor film 5 are partially etched to form islands. However,
Etching (island formation) of the semiconductor film 4 and the impurity semiconductor film 5 does not necessarily need to be performed in this step, and may be performed, for example, after the display electrode is formed or the coupling electrode is formed.

Step 6 [Figure 7 (vi), Figure 8 (vi), Figure 9 (
vi) After depositing a transparent conductive film 81 such as ITO, SnO, etc., a negative resist 30 is applied to form a gate wiring 20 locally provided with a gate electrode 2 and a drain wiring 60 locally provided with a drain electrode 6. Then, a resist pattern 30 is formed on the region not shielded by the source electrode 7 by back exposure. Note that the resist pattern 30 can also be formed by a positive resist image reversal method.

Step 7 (Figure 7 (vii), Figure 8 (vii), Figure 9 (vii)) Using the resist pattern as a mask, I
Etching the transparent conductive film 81 such as TO15n O*,
Display electrodes 8 are formed. In this case, the transparent conductive film material 81
The film thickness may be larger or smaller than the film thicknesses of the semiconductor film 4 and the impurity semiconductor film 5. The distance between the wiring pattern and the display electrode is determined by the resist pattern forming position and the side etching amount of ITO with respect to the resist pattern forming position. In this step, ITO, SnO,
, etc. remain, and display electrodes 8 remain in the display area.
are formed with high precision and at minute intervals. On the other hand, in the terminal area, for example, in order to avoid short circuits between terminals when making TAB connections, only the terminal area is covered with a metal mask using ITO.
Either prevent the transparent conductive film 81 such as SnO from being deposited, or remove the transparent conductive film 81 such as ITOlSnO after lift-off.
1 needs to be removed by etching.

Eighth Step [FIG. 7 (Unbiased)] A coupling electrode 9 that electrically connects the source electrode 7 and the display electrode 8 is formed. Finally, drain electrode 6 and source electrode 7
Using this as a mask, the impurity semiconductor film 5 in the channel portion is removed by etching.

Furthermore, in this step, when forming the coupling electrode 9, if an auxiliary drain wiring 90 is simultaneously formed on the drain wiring 60 to match the auxiliary drain wiring 90, disconnection of the drain wiring 60 can be prevented [Fig. ' line in Figure 10,
line c-c' is shown in FIG. 11].

In this way, according to the present invention, the self-patterns (gate wiring, drain wiring, source electrode) formed on the substrate
Since the etching resist pattern for display electrode formation is formed using the etching resist pattern as a mask, it is possible to eliminate defects due to pattern misalignment caused by the conventional photomask and exposure device. As a result, the display electrode formation area can be maximized. Furthermore, since the display electrode pattern is formed in the area where the foreign matter is present, short-circuit defects between the display electrode and the wiring pattern, which would occur if the pattern remains, are less likely to occur.

<Example 3> A third embodiment of the invention will now be described.

FIG. 12 shows a plan view of each pixel of the TPT array. FIG. 13(a) is a cross-sectional view taken along line AA' (TFT section) in FIG. 12, and FIG. 13(a) is a cross-sectional view taken along line BB' (gate wiring section) in FIG. (b), c in Fig. 12
A cross-sectional view taken along the -c' line (drain wiring part) is shown in FIG. 13(c).

In Examples 1 and 2, the drain wiring, drain electrode, and source electrode were formed at the same time. In the formation method of Example 3, although the display electrode and the drain wiring, drain electrode, and source electrode are formed with minute intervals, the display electrode is formed as an inverted pattern of the drain wiring and drain electrode by self-alignment. This has the advantage that short circuits between display electrodes and other patterns due to remaining patterns are less likely to occur. However, it is not always necessary to form the drain wiring, the drain electrode, and the source electrode at the same time.

Therefore, after forming the drain wiring 60 and the drain electrode 6, the drain wiring 60 is formed using the same method as in Example 1 or Example 2.
FIG. 12 shows an example in which the display electrode 8 is formed in an inverted pattern of the 0 and drain electrodes 6, and then the source electrode 7 is formed. By forming the auxiliary drain wiring 90 that matches the drain wiring at the same time, the drain wiring 60 can be prevented from being disconnected (line cc' in FIG. 12 is shown in FIG. 14).

In Example 3, the display electrode formation area can be further increased compared to Example 1 and Example 2, and the combination! It has the advantage that poles can be omitted.

Next, after forming the drain wiring 60 in FIGS. 15 and 16,
Using the same method as in Example 1 or Example 2, the drain wiring 6
An example will be shown in which a display electrode 8 is formed in an inverted pattern of 0, and then a drain electrode 6 and a source electrode 7 are formed. 1st
Figure 5 shows a plan view of each pixel of the TPT array.
Figure 6(a) is a cross-sectional view taken along line BB' (gate wiring section) in Figure 15. 161N(b)+: FIG. 16(c) is a cross-sectional view taken along line CC'()' (rain wiring portion) in FIG. 115.

Further, when forming the drain electrode 6 and the source electrode 7, if an auxiliary drain wiring 60 matching the drain wiring tiA60 is simultaneously formed, the drain wiring 60
(The line c-c' in Fig. 15 is shown in Fig. 17).This method also allows the display electrode formation area to be further increased compared to Embodiments 1 and 2, and the coupling electrode is omitted. It has the advantage of being possible.

<Example 4> FIG. 18 shows a plan view of a pixel unit of a TPT array of an active matrix display device obtained by the manufacturing method of the present invention. 19(i) to (vii) are cross-sectional views of each manufacturing process along line AA' (TFT section) in FIG. 18.
), FIGS. 20(i) to (vii) are cross-sectional views of each manufacturing process along the line BB' (gate wiring part) in FIG. 20 (1) to (vii) are cross-sectional views of each manufacturing process along the wiring section), and the explanation will be given accordingly.

First step (Fig. 19 (1), Fig. 20 (j), Fig. 21 (1)) Mo and Cr are deposited on a transparent substrate made of glass.

A gate wiring 20 locally provided with a gate tffi2 made of W, Ti, Ta, AI, etc. is formed, and a gate insulating film 3 made of a silicon nitride film or tantalum oxide, etc.
A semiconductor film 4 made of amorphous silicon or polysilicon, and a passivation insulating film 3 are formed by P-CVD.
Form them sequentially using a device or the like.

2nd step (Fig. 19 (ii), Fig. 20 (ii),
(ii)) The passivation insulating film 3' is etched and the impurity semiconductor film 5 is deposited on the entire surface. This passivation insulating film 3'' functions as an etching stopper when etching the impurity semiconductor 5 in the channel portion.

Third step (Figure 19 (iii), Figure 20 (iii),
Figure 21 (iii): Mo, Cr, W, Ti, Ta, A
A drain wiring 60 locally provided with a drain electrode 6 made of I or the like and a source electrode 7 are formed.

4th step [Figure 19 (iv), Figure 20 (iv), 2
Figure 1 (■) 1 A positive resist is applied onto a region shielded from light by the gate wiring 20 where the gate electrode 2 is locally provided, the drain wiring 6o where the drain electrode 6 is locally provided, and the source electrode 7. A resist pattern 3o is formed by back exposure.

Fifth step (FIG. 19 (V), FIG. 20 (■), FIG. 21 (V)) The resist pattern 30, the drain wiring 6o locally provided with the drain electrode 6, and the source electrode 7
Using this as an etching mask, the semiconductor film 4 and the impurity semiconductor film 5 are etched. A display electrode material 80 such as MTTo, SnO, etc. is deposited.

Step 6 (Fig. 19 (vi), Fig. 20 (■), Fig. 21
(Figure (■)) The display electrode 8 is formed by peeling off the resist pattern using a lift-off method. In this case, the display electrode material 80 remains in the region not shielded from light by the gate wiring 20, the drain wiring 60, and the source electrode 7, and the display electrodes 8 are formed in the display area with high precision and at minute intervals. on the other hand,
In the terminal area, for example, in order to avoid a short circuit between the terminals when making a TAB connection, it is necessary to apply a metal mask only to the terminal area so that the display electrode material 80 does not accumulate, or to remove the display tS material 80 by etching after lift-off. .

Step 7 (Figure 19 (vii), Figure 20 (vii),
FIG. 21(vii)] A coupling electrode 9 that electrically connects the source electrode 7 and the display electrode 8 is formed. Finally, the drain electrode 6, the source electrode 7 and the badge insulation film 3'
Using this as a mask, etching of the impurity semiconductor film 5 in the channel portion and partial etching (island formation) of the semiconductor film 4 and the impurity semiconductor film 5 on the gate wiring 20 are simultaneously performed.

In this case, the semiconductor film 5 remains in the region covered with the drain electrode 6, the drain wiring 60, the source tffi 7, and the passivation insulating film 3', and the impurity semiconductor @4 remains in the region covered with the drain electrode 6, the drain wiring 6o, and the source electrode 7. Remains in covered areas. In this way, in Examples 1 to 3, the etching of the impurity semiconductor film 5 in the channel portion and the partial etching (island formation) of the semiconductor film 4 and impurity semiconductor film 5 on the gate wiring 2o are performed in separate steps. However, the provision of the passivation insulating film 3' has the advantage that it can be carried out in the same process.

As described in the above embodiments, the display electrode 8 may be formed by etching using a resist pattern formed by back exposure as shown in embodiment 2, or by etching the display electrode 8 after forming the display electrode as in embodiment 3. An electrode or source electrode may also be formed. The gist of the present invention is to form a display electrode having an inverted shape with respect to the wiring pattern by a back exposure method using the gate wiring and drain wiring as masks.
If there is no problem with the off-characteristics of T, the partial etching (island formation) process of the semiconductor film 4 and impurity semiconductor film 5 on the gate wiring 20 in Examples 1.2 and 3 may be omitted; If ohmic contact can be made between the semiconductor film and the metal film, the impurity semiconductor film 5 can be omitted.

(G) Effects of the Invention As is clear from the above explanation, according to the present invention, the display electrodes are formed using the self-patterns (gate wiring, drain wiring, source electrode) formed on the substrate as a mask, which is different from conventional methods. It is possible to eliminate defects due to pattern positional deviation caused by the photomask and exposure device used in the method, and display electrodes can be formed at very small intervals with respect to the wiring pattern without any short-circuit defects. As a result, the aperture ratio can be increased,
The display quality of the liquid crystal display device can be improved.

Further, in the display device of the present invention, since the wiring pattern has a uniform width, the shape of the display electrode can be close to a rectangle. Furthermore, since the precision of the pattern is thereby improved, it is possible not only to prevent the occurrence of short circuits between wiring patterns, but also to contribute to an improvement in the aperture ratio.

[Brief explanation of the drawing]

FIG. 1 is a plan view of each pixel of a TPT array of a display device according to an embodiment of the present invention, and FIG. 2 is a plan view of each pixel of a TPT array according to the first embodiment of the present invention. 3 is a sectional view of each manufacturing process taken along line BB' in FIG. 1, and FIG. 4 is a sectional view of the first embodiment of the present invention. 1. FIG. 5 is another sectional view taken along line A-A' in FIG. 1. FIG. 6 is a cross-sectional view taken along line c-c' in FIG. 1. Another cross-sectional view taken along line c', FIG. 7 is a cross-sectional view of each manufacturing process taken along line c-c' in FIG. 1, and FIG. 8 is a second embodiment of the present invention. In the second embodiment, the first
9 is a sectional view of each manufacturing process taken along the line AA' in the figure, and FIG. 9 is a sectional view of each manufacturing process taken along the line AA' in FIG. 10 is another sectional view taken along the line A-A' in FIG. 1, FIG. 11 is another sectional view taken along the line c-c' in FIG. FIG. 13 (a) is a plan view of each pixel of the TPT array of the display device of the example.
) is the third embodiment of the present invention and is a cross-sectional view of each manufacturing process along the line A-A" in FIG. 12, and FIG. 13(C) is a cross-sectional view of each manufacturing process taken along the line AA' in FIG. 12 according to the third embodiment of the present invention; FIG. FIG. 14 is another sectional view taken along line c-c' in FIG. 12, and FIG. 15 is a TP of a display device according to another embodiment of the present invention.
FIG. 16(a) is a plan view of a pixel unit of the T array, and FIG. ) is a third other embodiment of the present invention, and is another sectional view taken along line BB' in FIG. 15, and FIG.
Figure (C) is a third alternative embodiment of the present invention;
Another cross-sectional view along line c', FIG. 17 is c- of FIG.
Another sectional view taken along line c', FIG. 18 is a plan view of each pixel of the TPT array of a display device according to still another embodiment of the present invention, and FIG. A- in Figure 18
20 is a sectional view of each manufacturing process taken along line A', and FIG. 20 is a sectional view of each manufacturing process taken along line BB' in FIG. In the fourth embodiment of the invention, the first
Cross-sectional view of each manufacturing process along line C-C' in Figure 8, No. 22
The figure is a plan view of a picture unit of a TPT array of a conventional display device. 1... Translucent insulating substrate, 2... Gate electrode, 3... Gate insulating film, 3'... Passivation insulating film, 4...
- Semiconductor film, 5 - Impurity semiconductor film, 6... Drain electrode, 7... Source electrode, 8 Display electrode, 9... Coupling electrode, 20... Gate wiring, 30... Resist pattern, 60... Drain wiring, 80 Display electrode material, 81... Transparent conductive film, 90... Auxiliary drain wiring.

Claims (3)

[Claims] (1) After forming a gate wiring on a light-transmitting substrate and sequentially depositing a gate insulating film and a semiconductor film, a drain wiring is formed on the semiconductor film, and the gate wiring and drain wiring are exposed from the back side of the substrate. A resist pattern is formed on the light-shielded area, the semiconductor film is etched using the resist pattern and the drain wiring as a mask, a conductive material for forming a display electrode is deposited, and the resist pattern is removed using a lift-off method. A method for manufacturing a display device, comprising: forming a display electrode by leaving a conductive material for forming a display electrode in a region not shielded from light by the gate wiring and the drain wiring by peeling the conductive material. (2) After forming a gate wiring on a light-transmitting substrate and sequentially depositing a gate insulating film and a semiconductor film, a drain wiring is formed on the semiconductor film, and the gate wiring and drain wiring are exposed from the back side of the substrate. A resist pattern is formed on the light-shielded area, the semiconductor film is etched using the resist pattern and the drain wiring as a mask, a transparent conductive material for forming display electrodes is deposited, and gate wiring is formed by exposure from the back side of the substrate. and a display characterized in that a display electrode is formed in an area not shaded by the gate wiring and the drain wiring by etching the transparent conductive material using a resist pattern formed in the area not shaded by the drain wiring as a mask. Method of manufacturing the device. (3) A plurality of gate wirings formed on a transparent substrate with a uniform width, a gate insulating film formed on the gate wirings, and a gate wiring formed on the gate insulating film with a width at most the same as that of the gate wirings. A semiconductor film formed into an island, a plurality of drain wirings having a uniform width that intersect with the gate wiring, and a gate electrode that is locally provided on the gate wiring, and a gate electrode that is locally provided on the drain wiring through a gate insulating film. a source electrode that faces the provided drain electrode region with a constant interval; and a display that is arranged in a region surrounded by the adjacent gate wiring and the adjacent drain wiring and is electrically connected to the source electrode. A display device comprising an electrode.