JPH04199801A - Manufacture of positive-characteristic thermistor element - Google Patents

Manufacture of positive-characteristic thermistor element

Info

Publication number
JPH04199801A
JPH04199801A JP2335766A JP33576690A JPH04199801A JP H04199801 A JPH04199801 A JP H04199801A JP 2335766 A JP2335766 A JP 2335766A JP 33576690 A JP33576690 A JP 33576690A JP H04199801 A JPH04199801 A JP H04199801A
Authority
JP
Japan
Prior art keywords
electrode
areas
electrode forming
chip
ptc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2335766A
Other languages
Japanese (ja)
Inventor
Yuichi Takaoka
高岡 祐一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2335766A priority Critical patent/JPH04199801A/en
Publication of JPH04199801A publication Critical patent/JPH04199801A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a decline in mechanical breaking strength of the title element by leaving a partial electrode in each electrode forming area in such a way that the surfaces of no-electrode forming areas are made to protrude from the surfaces of electrode forming areas and, after forming a full-surface electrode on the entire surface of a positive-characteristic(PTC) ceramic chip, part of the full-surface electrode are deleted from the no-electrode forming areas. CONSTITUTION:Protruding sections 2 are formed in areas where no partial electrode is required (no-electrode forming areas) on the surface of PTC ceramic chip 1 by causing the surfaces of the areas to protrude from the areas where partial electrodes are required (electrode forming areas). Then a full-surface electrode 4 is formed on the entire surfaces of six faces of the chip by electroless plating of Ni, etc., and the electrode 4 is deleted from the surfaces of the protruding sections 2 by a grinding method using sandblast, lapping, etc., after masking the electrode forming areas as required. In addition, the chip surface is exposed in the no-electrode forming areas and, at the same time, the partial electrodes 3 are formed by using the electrodes left in the electrode forming areas. Therefore, a decline in the mechanical breaking strength of this positive-characteristic thermistor element can be prevented.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は、チップ型をした正特性サーミスタ素子の製造
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a chip-type positive temperature coefficient thermistor element.

[背景技術] 第4図(a) (b) (c)に従来より実施されてい
る正特性(以下、PTCという。)サーミスタ素子の製
造方法を示す。第4図(a)に示すものは、直方体形状
に焼成されたPTCセラミックチップ51であって、こ
のチップ51の表面全面には第4図(b)に示すように
ニッケル(Ni)メツキ等によって全面電極52が形成
される。ついで、電極不要領域53を露出させるように
して全面電極52の一部をマスキング材料によって覆い
、全面電極52のマスキング材から露出した部分をサン
ドブラスト法によって研削し、第4図(C)に示すよう
に1、全面電極52を2つに分割して部分電極54を形
成している。さらに、この部分電極54の上に銀ペース
トを塗布及び焼き付けして正特性サーミスタ素子56の
外部電極55を形成している。
[Background Art] FIGS. 4(a), 4(b), and 4(c) show a conventional method of manufacturing a positive characteristic (hereinafter referred to as PTC) thermistor element. What is shown in FIG. 4(a) is a PTC ceramic chip 51 fired into a rectangular parallelepiped shape, and the entire surface of this chip 51 is plated with nickel (Ni) or the like as shown in FIG. 4(b). A full surface electrode 52 is formed. Next, a part of the entire surface electrode 52 is covered with a masking material so as to expose the electrode unnecessary region 53, and the portion of the surface electrode 52 exposed from the masking material is ground by sandblasting, as shown in FIG. 4(C). First, the entire surface electrode 52 is divided into two to form a partial electrode 54. Furthermore, a silver paste is applied and baked onto the partial electrode 54 to form the external electrode 55 of the positive temperature coefficient thermistor element 56.

[発明が解決しようとする課題]−′ しかしながら、上記のようにして全面電極52をサンド
ブラストし、分割電極54を形成する方法では、全面電
極52t!−サンドブラストによって部分的に削除する
際、電極金′属だけでなく、′その下のPTCセラミッ
クチップ51も削り取られ、電極形成領域と電極不要領
域53との境界部でチップ表面に段差が生じている(第
4図(C)参照)。
[Problems to be Solved by the Invention]-' However, in the method of sandblasting the entire surface electrode 52 and forming the divided electrodes 54 as described above, the entire surface electrode 52t! - When partially removing by sandblasting, not only the electrode metal but also the underlying PTC ceramic chip 51 is scraped off, creating a step on the chip surface at the boundary between the electrode forming area and the electrode unnecessary area 53. (See Figure 4(C)).

このため、この段差部分に応力集中が発生し易く、この
部分でPTCサーミスタ素子56の機械的折れ強度が低
下するという欠点があった。
Therefore, stress concentration tends to occur in this stepped portion, and the mechanical bending strength of the PTC thermistor element 56 decreases in this portion.

また、このPTCサーミスタ素子56をプリント配線基
板57の表面に実装した時、第5図に示すように、PT
Cセラミックチップ51がプリント配線基板57の表面
に接触せず、プリント配線基板57との間に空間58が
発生する。このためプリント配線基板57の熱や温度を
PTCサーミスタ素子56によって検出しにくくなり、
PTCサーミスタ素子56のセンサー能力が低下すると
いう問題があった。
Furthermore, when this PTC thermistor element 56 is mounted on the surface of the printed wiring board 57, as shown in FIG.
The C ceramic chip 51 does not contact the surface of the printed wiring board 57, and a space 58 is created between the C ceramic chip 51 and the printed wiring board 57. This makes it difficult for the PTC thermistor element 56 to detect the heat and temperature of the printed wiring board 57.
There was a problem in that the sensing ability of the PTC thermistor element 56 was reduced.

本発明は叙上の従来例の欠点に鑑みてなされたものであ
り、その目的とするところは、機械的折れ強度の低下や
センサー能力の低下を招くことなく、電極を形成するこ
とができる正特性サーミスタ素子の製造方法を提供する
ことにある。
The present invention has been made in view of the drawbacks of the conventional examples described above, and its purpose is to provide a method for forming electrodes without causing a decrease in mechanical bending strength or a decrease in sensor performance. An object of the present invention is to provide a method for manufacturing a characteristic thermistor element.

[i1!題を解決するための手段コ 本発明の正特性サーミスタ素子の製造方法は、PTCセ
ラミックチップの少なくとも実装面及び実装面と対向す
る表面において電極不要領域の表面を電極形成領域の表
面よりも突出させておき、PTCセラミックチップの当
該表面の全面に全面電極を形成した後、電極不要領域に
おいて全面電極の一部を削除し、各電極形成領域に部分
電極を残すことを特徴としている。
[i1! Means for Solving the Problem: The method of manufacturing a PTC thermistor element of the present invention includes making the surface of the electrode-free region protrude beyond the surface of the electrode formation region at least on the mounting surface and the surface facing the mounting surface of the PTC ceramic chip. The method is characterized in that after a full-scale electrode is formed on the entire surface of the PTC ceramic chip, a part of the full-face electrode is removed in areas where electrodes are not required, and partial electrodes are left in each electrode formation area.

口作用] 本発明にあっては、PTCセラミックチップの電極不要
領域の表面を電極形成領域の表面よりも突出させである
ので、電極不要領域において全面電極を削除してチップ
表面を露出させても、電極不要領域のチップ表面が部分
電極の部分よりも削り込まれることがなく、PTCサー
ミヌタ素子の機械的折れ強度の低下を防止することがで
きる。
In the present invention, since the surface of the electrode-free region of the PTC ceramic chip is made to protrude from the surface of the electrode-forming region, even if the entire surface electrode is removed in the electrode-free region and the chip surface is exposed, In this case, the chip surface in the area where electrodes are not required is not etched further than the part of the partial electrodes, and a decrease in the mechanical bending strength of the PTC therminuta element can be prevented.

また、PTCサーミスタ素子の実装面をほぼ均一な面と
することができるので、このPTCサーミスタ素子をプ
リント配線基板等に実装した時、チップ表面をプリント
配線基板等に接触ないし近接させることができ、PTC
サーミスタ素子のセンサー能力を高めることができる。
In addition, since the mounting surface of the PTC thermistor element can be made almost uniform, when this PTC thermistor element is mounted on a printed wiring board etc., the chip surface can be brought into contact with or close to the printed wiring board etc. PTC
The sensing ability of the thermistor element can be improved.

[実施例] 以下、本発明の実施例を添付図に基づいて詳述する。[Example] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

第1図(a) (b) (c)は本発明の一実施例の製
造方法を示している。第1図(a)に示すものは、正温
度特性を示すセラミック類のPTCセラミックチップ1
であって、略長方体状に成形された焼成品であり、チッ
プ表面の部分電極を設ける必要のない領域(電極不要領
域)−の表面を部分電極の必要な領域(電極形成領域)
の表面よりも突出させ、電極不要領域に、突出部2を形
成しである。図示例では、PTCセラミックチップ1の
中央部に沿ってチップ表面の4面に帯状の突出部2を設
けであるが、この突出部2は用途等に応じて適当な形状
にしてもよい。また、突出部2の突出高さhは、部分電
極3の膜厚よりも大きくなっている。ついで、第1図(
b)に示すように、PTCセラミックチップ1の6面金
面に無電解メツキによってNiメツキ等を施して全面電
極4を設け、必要に応じて電極形成領域をマスキングし
、サンドブラストやラップ等の研磨方法によって突出部
2の上の全面電極4を削除し、第1図(c)に示すよう
に、電極不要領域においてチップ表面を露出させると共
に電極形成領域に残された電極によって部分電極3を形
成する。また、電極不要領域のチップ表面と部分電極表
面とは、はぼ面一となる。この後、ハンダ付は性を良好
にするため、部分電極3の上にAgもしくはAg合金か
らなる電極ペーストを塗布焼付けし、あるいは電解メツ
キして追加電極5を形成する。
FIGS. 1(a), 1(b), and 1c show a manufacturing method according to an embodiment of the present invention. The one shown in Fig. 1(a) is a PTC ceramic chip 1 of ceramic type exhibiting positive temperature characteristics.
It is a fired product formed into a substantially rectangular shape, and the area on the chip surface where it is not necessary to provide a partial electrode (electrode unnecessary area) is replaced by the area where a partial electrode is required (electrode formation area).
A protrusion 2 is formed in an area where no electrode is required, protruding from the surface of the electrode. In the illustrated example, band-shaped protrusions 2 are provided on four sides of the chip surface along the central portion of the PTC ceramic chip 1, but the protrusions 2 may have an appropriate shape depending on the application. Further, the protrusion height h of the protrusion 2 is larger than the film thickness of the partial electrode 3. Next, Figure 1 (
As shown in b), the six gold surfaces of the PTC ceramic chip 1 are plated with Ni using electroless plating to form electrodes 4 on the entire surface, masking the electrode formation area as necessary, and polishing such as sandblasting or lapping. As shown in FIG. 1(c), the entire surface electrode 4 on the protrusion 2 is removed by this method, and the chip surface is exposed in the area where no electrode is required, and a partial electrode 3 is formed using the electrode left in the electrode formation area. do. Further, the chip surface in the electrode-free region and the partial electrode surface are flush with each other. Thereafter, in order to improve soldering properties, an additional electrode 5 is formed by applying and baking an electrode paste made of Ag or an Ag alloy onto the partial electrode 3 or by electroplating.

したかって、PTCセラミックチップ1には削り過ぎに
よる薄肉部分が生じず、機械的折れ強度の低下を防止す
ることができる。このため、ハンダ付は時のヒートスト
レスによるクラックの発生もなくなり、素子の信頼性も
向上する。
Therefore, the PTC ceramic chip 1 does not have a thin portion due to excessive cutting, and a decrease in mechanical bending strength can be prevented. Therefore, the occurrence of cracks due to heat stress during soldering is eliminated, and the reliability of the element is improved.

また、このPTCサーミスタ素子6をプリント配線基板
7の表面に実装すると、第2図に示すように、PTCセ
ラミックチップlの下面に空間が生じず、プリント配線
基板7の表面に密着するので、プリント配線基板7の熱
がPTCセラミックチップ1に伝わり易く、PTCサー
ミスタ素子6のセンサー能力を高めることができる。ま
た、PTCサーミスタ素子6の表面に凹凸がなく、平坦
であるため、チッププレーサ−によりPTCサーミスタ
素千6をプリント配線基板7に装着させ易くなり、素子
実装時の工程不良を削減できる。
Furthermore, when this PTC thermistor element 6 is mounted on the surface of the printed wiring board 7, as shown in FIG. The heat of the wiring board 7 is easily transmitted to the PTC ceramic chip 1, and the sensing ability of the PTC thermistor element 6 can be improved. Further, since the surface of the PTC thermistor element 6 is flat without any unevenness, it becomes easy to attach the PTC thermistor element 6 to the printed wiring board 7 using a chip placer, and process defects during element mounting can be reduced.

第3図に示すものは、本発明の別な実施例の製造方法に
よって製造されたPTCサーミスタ素子8の断面図であ
る。これは、略直方体状をしたPTCセラミックチップ
1の上面及び下面のみにおいて電極不要領域に突出部2
を設けておき、PTCセラミックチップ1の上表面及び
下表面の全面に無電解Niメツキ等によって全面電極(
図示を省略する。)を設けた後、電極不要領域の電極を
除去して上下表面の電極形成領域に部分電極3を設け、
ついで部分電極3の表面及びPTCセラミックチップ1
の両端面にAgないしAg合金によって追加電極5を形
成したものである。
What is shown in FIG. 3 is a sectional view of a PTC thermistor element 8 manufactured by a manufacturing method according to another embodiment of the present invention. This is because the protrusions 2 are located only in the upper and lower surfaces of the substantially rectangular parallelepiped-shaped PTC ceramic chip 1 in areas where electrodes are not required.
The entire upper and lower surfaces of the PTC ceramic chip 1 are covered with electrodes (
Illustrations are omitted. ), remove the electrodes in areas where electrodes are not needed and provide partial electrodes 3 in the electrode formation areas on the upper and lower surfaces,
Next, the surface of the partial electrode 3 and the PTC ceramic chip 1
Additional electrodes 5 are formed on both end faces of Ag or Ag alloy.

従って、この実施例は、親基板(図示せず)の上面及び
下面の全面に全面電極を形成しておき、全面電極形成後
に親基板を各PTCセラミックチップにカットする場合
に適している。
Therefore, this embodiment is suitable for forming electrodes on the entire upper and lower surfaces of a parent substrate (not shown) and cutting the parent substrate into PTC ceramic chips after forming the electrodes on the entire surface.

[発明の効果コ 本発明よれば、電極不要領域におけるPTCセラミック
チップの削り込みがなくなるので、チップの傷が少なく
なり、素子の機械的強度が高まる。
[Effects of the Invention] According to the present invention, since the PTC ceramic chip is not scraped in areas where electrodes are not required, there are fewer scratches on the chip and the mechanical strength of the element is increased.

また、これによりハンダ付は時のヒートストレスによる
クラックの発生もなくなり、素子の信頼性が向上する。
This also eliminates the occurrence of cracks due to heat stress during soldering, improving the reliability of the device.

さらに、素子の実装面に段差がなくなるので、素子をプ
リント配線基板に密着させて取付けることができ、PT
Cサーミスタ素子のセンサー能力が向上する。また、表
面に凹凸がないので、チッププレーサ−による素子の装
着も確実かつ容易に行なえる。
Furthermore, since there are no steps on the mounting surface of the element, the element can be mounted closely to the printed wiring board, and the PT
The sensing ability of the C thermistor element is improved. Furthermore, since there are no irregularities on the surface, mounting of elements using a chip placer can be carried out reliably and easily.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a) (b) (c)は本発明の一実施例にお
けるPTCサーミスタ素子の製造方法を示す断面図、第
2図は同上の方法によって製造された素子をプリント配
線基板上に実装した状態を示す断面図、第3図は本発明
の別な実施例を示す断面図、第4図(a) (b) (
c)は従来の製造方法を示す断面図、第5図は同上の方
法によって製造された素子をプリント配線基板上に実装
した状態を示す断面図である。 1・・・PTCセラミックチップ 2・・・突出部 3・・・部分電極 4・・・全面電極 特許出願人 株式会社 村田製作所 第2図
Figures 1 (a), (b), and (c) are cross-sectional views showing a method for manufacturing a PTC thermistor element according to an embodiment of the present invention, and Figure 2 is a mounting of the element manufactured by the above method on a printed wiring board. 3 is a sectional view showing another embodiment of the present invention, and FIGS. 4(a) (b) (
c) is a sectional view showing a conventional manufacturing method, and FIG. 5 is a sectional view showing a state in which an element manufactured by the above method is mounted on a printed wiring board. 1... PTC ceramic chip 2... Protrusion 3... Partial electrode 4... Full electrode Patent applicant Murata Manufacturing Co., Ltd. Figure 2

Claims (1)

【特許請求の範囲】[Claims] (1)PTCセラミックチップの少なくとも実装面及び
実装面と対向する表面において電極不要領域の表面を電
極形成領域の表面よりも突出させておき、PTCセラミ
ックチップの当該表面の全面に全面電極を形成した後、
電極不要領域において全面電極の一部を削除し、各電極
形成領域に部分電極を残すことを特徴とする正特性サー
ミスタ素子の製造方法。
(1) At least on the mounting surface and the surface facing the mounting surface of the PTC ceramic chip, the surface of the area where no electrode is required is made to protrude beyond the surface of the electrode formation area, and an electrode is formed on the entire surface of the PTC ceramic chip. rear,
A method of manufacturing a positive temperature coefficient thermistor element, characterized in that a part of the entire surface electrode is removed in an area where no electrode is required, and a partial electrode is left in each electrode formation area.
JP2335766A 1990-11-29 1990-11-29 Manufacture of positive-characteristic thermistor element Pending JPH04199801A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2335766A JPH04199801A (en) 1990-11-29 1990-11-29 Manufacture of positive-characteristic thermistor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2335766A JPH04199801A (en) 1990-11-29 1990-11-29 Manufacture of positive-characteristic thermistor element

Publications (1)

Publication Number Publication Date
JPH04199801A true JPH04199801A (en) 1992-07-21

Family

ID=18292220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2335766A Pending JPH04199801A (en) 1990-11-29 1990-11-29 Manufacture of positive-characteristic thermistor element

Country Status (1)

Country Link
JP (1) JPH04199801A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014082303A (en) * 2012-10-16 2014-05-08 Koa Corp Method of manufacturing multiple-chip resistor
WO2016098556A1 (en) * 2014-12-15 2016-06-23 株式会社村田製作所 Electronic component manufacturing method and electronic component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014082303A (en) * 2012-10-16 2014-05-08 Koa Corp Method of manufacturing multiple-chip resistor
WO2016098556A1 (en) * 2014-12-15 2016-06-23 株式会社村田製作所 Electronic component manufacturing method and electronic component
JPWO2016098556A1 (en) * 2014-12-15 2017-09-14 株式会社村田製作所 Electronic component manufacturing method and electronic component
US10074465B2 (en) 2014-12-15 2018-09-11 Murata Manufacturing Co., Ltd. Method of manufacturing electronic component, and electronic component

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