JPH04199556A - Pin grid array type ic package - Google Patents
Pin grid array type ic packageInfo
- Publication number
- JPH04199556A JPH04199556A JP29301390A JP29301390A JPH04199556A JP H04199556 A JPH04199556 A JP H04199556A JP 29301390 A JP29301390 A JP 29301390A JP 29301390 A JP29301390 A JP 29301390A JP H04199556 A JPH04199556 A JP H04199556A
- Authority
- JP
- Japan
- Prior art keywords
- pins
- package
- wiring board
- grid array
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003780 insertion Methods 0.000 claims abstract description 23
- 230000037431 insertion Effects 0.000 claims abstract description 23
- 238000005476 soldering Methods 0.000 description 3
- 241000288673 Chiroptera Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3415—Surface mounted components on both sides of the substrate or combined with lead-in-hole components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はピングリッドアレイ形ＩＣパッケージに関し、
より詳しくは、プリント配線板の配線パターン密度の向
上に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pin grid array type IC package,
More specifically, it relates to improving the wiring pattern density of printed wiring boards.
（従来の技術）
第４図及び第５図は従来のピングリッドアレイ形ＩＣパ
ッケージを示すもので、ピングリッドアレイ形ＩＣパッ
ケージ（１）はパッケージ（２）の下部に一定のピッチ
（２５４ＩＩＩＩ１１が多い）で複数の挿入ピン（３）
を備え、この複数の挿入ピン（３）が配線パターン（５
）を印刷したプリント配線板（４）の対応した複数のス
ルーホール（６）に挿入後、半田（７）で半田付けされ
ることにより、プリント配線板（４）に接続固定されて
いた。(Prior Art) Figures 4 and 5 show conventional pin grid array type IC packages, in which the pin grid array type IC package (1) has a fixed pitch (254III11 is often used) at the bottom of the package (2). ) with multiple insertion pins (3)
The plurality of insertion pins (3) are connected to the wiring pattern (5).
) was inserted into a plurality of corresponding through-holes (6) of a printed wiring board (4) on which the printed wiring board (4) was printed, and then connected and fixed to the printed wiring board (4) by being soldered with solder (7).
尚、この種の先行技術文献として特開昭６１−２３４０
５７号、及び特開平１−２１８０９１号公報等がある。In addition, as a prior art document of this kind, Japanese Patent Application Laid-Open No. 61-2340
No. 57, and Japanese Unexamined Patent Publication No. 1-218091.
従来のピングリッドアレイ形ＩＣパッケージ（１）は以
上のように構成され、全ての挿入ピン（３）が半田付け
されるので、プリント配線板（４）にスルーホール（６
）を穿設せざるを得す、このため、配線パターン（５）
の設計が妨げられ、配線密度が低下していた。The conventional pin grid array type IC package (1) is constructed as described above, and all the insertion pins (3) are soldered, so that through holes (6) are formed in the printed wiring board (4).
), therefore, wiring pattern (5)
design was hindered and wiring density was reduced.
本発明は上記に鑑みなされたもので、ピンの本数を維持
しつつプリント配線板の配線密度を向上させることので
きるピングリッドアレイ形ＩＣバツケ、−ジを提供する
ことを目的としている。The present invention has been made in view of the above, and an object of the present invention is to provide a pin grid array type IC package that can improve the wiring density of a printed wiring board while maintaining the number of pins.
本発明においては上述の目的を達成するため、プリント
配線板のスルーホールに挿入され半田付けされる複数の
挿入ピンを備えたピングリットアレイ形ＩＣパッケージ
において、上記複数の挿入ピンの一部を、プリント配線
板の表面のバットに当接する突き当てピンとして構成し
たことを特徴としている。In order to achieve the above-mentioned object in the present invention, in a pin grid array type IC package equipped with a plurality of insertion pins that are inserted into through holes of a printed wiring board and soldered, some of the plurality of insertion pins are It is characterized by being constructed as an abutment pin that abuts against a butt on the surface of a printed wiring board.
（作用）
本発明によれば、突き当てピンがプリント配線板の表面
に当接し、半田付けされるので、スルーホールの数を減
少させて配線密度の向上を図ることができる。(Function) According to the present invention, the abutment pins abut against the surface of the printed wiring board and are soldered, so that the number of through holes can be reduced and the wiring density can be improved.
（実施例）
以下、第１図〜第３図に示す一実施例に基づき本発明を
詳述すると、図中、（１） はピングリットアレイ形Ｉ
Ｃパッケージで、このピングリッ）こアレイ形ＩＣパッ
ケージ（１）はパッケージ（２）と、このパッケージ（
２）の下部に垂直に配設された複数の挿入ピン（３）と
、該パッケージ（２）の下部に垂直に配設され挿入ピン
（３）よりも短かい複数の突き、当てピン（８）とから
構成され、挿入ピン（３）と突き当てピン（８）の比率
が半々になっている。(Example) Hereinafter, the present invention will be described in detail based on an example shown in FIGS. 1 to 3. In the figure, (1) is a pin grid array type I.
In C package, this pingrid array type IC package (1) is connected to package (2) and this package (
A plurality of insertion pins (3) are arranged vertically at the bottom of the package (2), and a plurality of pins (8) are arranged vertically at the bottom of the package (2) and are shorter than the insertion pins (3). ), and the ratio of the insertion pin (3) and the abutting pin (8) is half and half.
（４）は配線パターン（５）を印刷したプリント配線板
で、このプリント配線板（４）は挿入ピン（３）に貫通
される複数のスルーホール（６）と、表面に設けられ突
き当てピン（８）に当接される複数のバット（９）とを
備えている。(4) is a printed wiring board on which a wiring pattern (5) is printed, and this printed wiring board (4) has a plurality of through holes (6) penetrated by insertion pins (3), and abutment pins provided on the surface. (8) and a plurality of bats (9) that come into contact with the bats (8).
従って、ピングリッドアレイ形ＩＣパッケージ（１）は
第３図に示す如く、挿入ピン（３）がスルーホール（６
）に挿入されるとともに、突き当てピン（８）がパッド
（９）に当接し、これらのピン（３）・（８）が半田（
７）を介して半田付けされることにより、プリント配！
！（４）に接続固定される。この接続の際、挿入ピン（
３）の機能を営む突き当てピン（８）がバット（９）に
当接後、半田付けされるので、スルーホール（６）の数
を減少させることができ、配線パターン（５）が妨げら
れることがなく、配線密度の低下を防止することがてき
る。また、挿入ピン（３）のスルーホール（６）への挿
入により、突き当てピン（８）とパッド（９）が位置決
めされるので、突き当てピン（８）とバット（９）の接
続を良好ならしめることが可能となる。Therefore, in the pin grid array type IC package (1), as shown in Fig. 3, the insertion pin (3) is inserted into the through hole (6).
), the abutment pin (8) abuts the pad (9), and these pins (3) and (8) are soldered (
7) By soldering through the print distribution!
! (4) is connected and fixed. When making this connection, use the insertion pin (
Since the abutting pin (8) that performs the function of 3) is soldered after coming into contact with the butt (9), the number of through holes (6) can be reduced and the wiring pattern (5) is not disturbed. Therefore, a decrease in wiring density can be prevented. Also, by inserting the insertion pin (3) into the through hole (6), the abutment pin (8) and pad (9) are positioned, so the connection between the abutment pin (8) and the butt (9) is good. It becomes possible to get used to it.
尚、本願に係る発明と上記諸公報の発明は、目的・構成
・効果が全く相違するので、別設問題を生じない。また
、上記実施例では挿入ピン（３）と突き当てピン（８）
の比率を半々としたものを示しタカ、これに限定される
ものではない。Incidentally, since the invention according to the present application and the inventions of the above-mentioned publications are completely different in purpose, structure, and effect, no separate problem arises. In addition, in the above embodiment, the insertion pin (3) and the abutment pin (8)
The ratio is 50/50 and is not limited to Tk.
（発明の効果〕
以上のように本発明によれば、挿入ピンを備えたピング
リッドアレイ形ＩＣパッケージに、プリント配線板表面
のパッドに当接する突き当てピンを配設しているので、
ピンの本数を維持しつつ配線密度の向上を図ることがで
き、高密度実装のプリント回路板を得ることがで各ると
いう効果がある。(Effects of the Invention) As described above, according to the present invention, the pin grid array type IC package equipped with insertion pins is provided with abutment pins that abut against pads on the surface of the printed wiring board.
The wiring density can be improved while maintaining the number of pins, and a printed circuit board with high density mounting can be obtained.
第１図は本発明に係るピングリッドアレイ形ＩＣパッケ
ージの一実施例を示す断面側面図、第２図は本発明に係
るピングリッドアレイ形ＩＣパッケージの一実施例を示
す斜視図、第３図は本発明に係るピングリッドアレイ形
ＩＣパッケージとプリント配線板の半田付は部分を示す
拡大断面図、第４図は従来のピングリットアレイ形ＩＣ
パッケージを示す断面側面図、第５図は従来のピングリ
ッドアレイ形ＩＣパッケージとプリント配線板の半田付
は部分を示す拡大断面図である。
図中、（１）はピングリッドアレイ形ＩＣパッケージ、
（３）は挿入ピン、（４）はプリント配線板、（６）は
スルーホール、（７）は半田、（８）は突ぎ当てピン、
（９）はパッドである。
尚、各図中、同一符号は同−又は相当部分を示す。
一部
代理人 山 崎 宗 秋 ］・。
＋：！
ζ−一二一
＠１図
第３図
ｆＩＮ４ 図FIG. 1 is a cross-sectional side view showing an embodiment of the pin grid array type IC package according to the present invention, FIG. 2 is a perspective view showing an embodiment of the pin grid array type IC package according to the present invention, and FIG. 4 is an enlarged sectional view showing the soldering portion of the pin grid array IC package and printed wiring board according to the present invention, and FIG. 4 is a diagram showing the conventional pin grid array IC package.
FIG. 5 is an enlarged sectional view showing a soldering portion of a conventional pin grid array type IC package and a printed wiring board. In the figure, (1) is a pin grid array type IC package;
(3) is an insertion pin, (4) is a printed wiring board, (6) is a through hole, (7) is solder, (8) is a butting pin,
(9) is a pad. In each figure, the same reference numerals indicate the same or corresponding parts. Partial agent Souaki Yamazaki]. +:! ζ-121@1 Figure 3 fIN4 Figure
Claims (1)
る複数の挿入ピンを備えたピングリッドアレイ形ＩＣパ
ッケージにおいて、上記複数の挿入ピンの一部を、プリ
ント配線板の表面のパッドに当接する突き当てピンとし
て構成したことを特徴とするピングリッドアレイ形ＩＣ
パッケージ。In a pin grid array type IC package including a plurality of insertion pins inserted into through holes of a printed wiring board and soldered, a part of the plurality of insertion pins is brought into contact with a pad on a surface of the printed wiring board. A pin grid array type IC characterized by being configured as pins.
package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29301390A JPH04199556A (en) | 1990-10-30 | 1990-10-30 | Pin grid array type ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29301390A JPH04199556A (en) | 1990-10-30 | 1990-10-30 | Pin grid array type ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04199556A true JPH04199556A (en) | 1992-07-20 |
Family
ID=17789348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29301390A Pending JPH04199556A (en) | 1990-10-30 | 1990-10-30 | Pin grid array type ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04199556A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660405A3 (en) * | 1993-12-22 | 1996-03-20 | Ibm | Surface mount chip package. |
| US5986337A (en) * | 1997-11-17 | 1999-11-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor element module and semiconductor device which prevents short circuiting |
| CN105990296A (en) * | 2015-02-15 | 2016-10-05 | 展讯通信（上海）有限公司 | Chip connecting structure and manufacturing process |
| CN110678759A (en) * | 2017-05-30 | 2020-01-10 | 日本麦可罗尼克斯股份有限公司 | Electrical connection device |
-
1990
- 1990-10-30 JP JP29301390A patent/JPH04199556A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660405A3 (en) * | 1993-12-22 | 1996-03-20 | Ibm | Surface mount chip package. |
| US5986337A (en) * | 1997-11-17 | 1999-11-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor element module and semiconductor device which prevents short circuiting |
| CN105990296A (en) * | 2015-02-15 | 2016-10-05 | 展讯通信（上海）有限公司 | Chip connecting structure and manufacturing process |
| CN110678759A (en) * | 2017-05-30 | 2020-01-10 | 日本麦可罗尼克斯股份有限公司 | Electrical connection device |
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