JPH04196816A - Phase locked loop - Google Patents

Abstract

PURPOSE:To prevent a communication fault from occurring by providing a band pass filter(BPF) which filters a frequency signal in the pull-in limit range of a phase locked loop(PLL), and an amplifier(AMP) which amplifies the amplitude of a BPF output signal to the amplitude necessary to the operation of a phase comparator(PC). CONSTITUTION:Even when a disturbance noise beyond the pull-in limit range is mixed with an input frequency, and the frequency signal is inputted to a BPF 1, the frequency components of the disturbance noise are removed, so that the frequency components of the disturbance noise can't remain, and only the input frequency can remain, in the BPF output signal. The amplitude of the input frequency is reduced when the input frequency passes through the BPF 1, and when it is inputted to an AMP 2, the amplitude is amplified to the amplitude necessary to the operation of a PC 30, and inputted to the PC 30. The signal inputted to the PC 30 has the frequency in the pull-in limit range of the PLL, so that the signal can easily be pulled in. Thus, the communication fault is prevented from occurring.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase-locked circuit, particularly a phase-locked circuit suitable for timing extraction of PCM communication, etc. The present invention relates to a phase synchronized circuit that can easily perform phase synchronization even when disturbance noise having a frequency component t# other than frequency ft' is mixed.

[Conventional technology]

In the conventional circuit, the input signal 1 and the PC were directly connected, as described in "New PLL Technology", Ohmsha, author: Shinbu Koyo (published on May 25, 1981), pages 2 to 3.

[Problem to be solved by the invention]

In the prior art described above, the input signal fi and pc were directly connected. However, in actual applications, as fi, f, /
f(" may be mixed in, and the problem is shown below.

The purpose of PLL (7) is to make fO equal to f( in terms of frequency and phase) by interlocking PC, LPF, and VCO (7). This equalizing operation is called retraction, and the retraction range is finite. When f( is between the minimum retractable frequency fwin and the same maximum frequency flag, that is, f5hin≦fi≦f1αX), retraction is possible. This range is called the retraction limit range. .

Normally, it is adjusted so that f win≦g and I≦frmcLn, and is always in a retractable state.

However, in g and r, disturbance noise fi' exceeding the pull-in limit range (that is, ft'<fmin or fmcLx<
fi'), the PLL will not be able to retract.
Communication failure occurs.

The purpose of the present invention is to provide disturbance noise ft exceeding the pull-in limit range.
An object of the present invention is to provide a phase synchronized circuit which can be easily pulled in even if " is mixed into fLl, and which does not cause a communication failure."

[Means to solve the problem]

In order to achieve the above purpose, PLL is installed between fl and PC.
The system is equipped with a BPF that filters only frequencies within the capture range of , and an AMP that amplifies the high titer o' of the BPF whose amplitude is attenuated when it passes through the BPF to the amplitude necessary for the operation of the PC.

[Effect]

Even if the disturbance noise f1'' exceeding the pull-in limit range mixes into fLl, when it is input to the BPF, the frequency component of fLl disappears, so the BPF output reliability value o' is equal to f□'
No frequency component remains, and only fLl remains. f□′ is B
Although the amplitude is attenuated when passing through the PF, it is input to the AMP, amplified to the amplitude necessary for the operation of the PC, and input to the PC. Since the signal input to the PC has a frequency within the pull-in limit range of the PLL, it can be easily pulled in, and communication failures will not occur.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

The input signal fτ is input to the BPFI, becomes a signal 10, and is input to the AMP2. The output signal 20 of AMP2 is PL
It is input to L3 and becomes the output fO.

PLL3 will be explained. PC30 has signal 20 and ■
The output signal fo of C○32 is input, and its phase difference ΔT is converted into a voltage V+Δ■ by the PC 30, which is output as a signal 300. When ΔT=O, Δ■=0, and ■ is the voltage of the DC signal 300 when fi and fo are finally equal in frequency and phase. The DC signal 300 is input to the LPF 31 and only its low frequency component passes through to become a signal 310 with a voltage of ■+Δ■, which is input to the VCO 32. vC○32 receives the signal 310 and outputs the voltage V
A frequency fo corresponding to +Δ■ is output. fO is repeatedly input to the PC 30 and compared with signal 1, and the phase difference ΔT
The above basic operation of the PLL 3 is repeated until the value becomes O. As mentioned above, the signals fi and fo will eventually become equal in terms of frequency and phase, and at this time
ΔT20, Δv=0.

Next, BPFI, AMP2. The details of PLL3 will be explained.

The pull-in limit range of PLL3 is finite, and pull-in is possible when l is between the minimum pull-in possible frequency f win and the same maximum frequency fmcLx, that is, f win≦f (≦ fmcLx. In an actual application example Expected input frequency ft
' is adjusted to satisfy f+iin≦t, l≦f■α, and is always in a retractable state.

Disturbance noise f with a frequency exceeding the pull-in limit range is added to fLl.
i'c or ft'<fmin or fllIcLx<f
t') is mixed in. Even if these fLl and fLl signals fi are input to BPFI, BPFI is f min
If only the frequency fllPF where ≦fBPF≦fma* is passed, f□' will slightly disappear after passing through the BPFI, and only fLl will remain. In other words, the signal 10 has only the frequency ft' and has no disturbance noise component.

However, the signal 10 normally has its amplitude attenuated when passing through the BPFI, and is input to the AMP 2 and amplified. The purpose of this amplification is to adjust the signal 20 to the operating level of the PC 30, for example, the TTL level.

The signal 20 that matches the operating level of the PC 30 is input to the PC 30, and the rest is pulled in by the basic operation of the PLL 3 described above.

According to this embodiment, the disturbance noise f(' exceeding the pull-in limit range of the PLL 3 is the signal f, L defined as input).
Even if it is mixed in, BPFI removes ft# and AMP2
Since the level of fLl is restored in PLL 3, there is no disturbance noise fi'' input to PLL 3, and the pull-in can be easily performed.

Examples of the BPFI include a monolithic Chris Null filter and an Lc filter.

Examples of AMP2 include a comparator and an operational amplifier.

A second example is shown in FIG. In other words, the input signal l is set to A in advance.
The disturbance noises f and # may be amplified by MP2 and then removed by BPFI.

〔Effect of the invention〕

According to the present invention, even if disturbance noise having a frequency component within the PLL pull-in limit range mixes into the input signal, the disturbance noise can be removed before being input to the PLL.
This has the effect of eliminating the problem of communication failure caused by the LL becoming unable to be retracted.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are diagrams showing an example of the configuration of a phase locked circuit according to the present invention. 1...Bandpass filter, 2...Amplifier, 3...
・PLL, 30...phase comparator, 3 draw pass filter, 32・
...Voltage controlled oscillator.

Claims (1)

[Claims] 1. A voltage controlled oscillator (VCO), a phase comparator (PC) that detects the phase difference between the VCO's output signal f_o and an external input signal f_i, and a phase comparator (PC) that allows only the low frequency component of the PC output to pass through. A phase locked loop (PLL) consisting of a low pass filter (LPF) that outputs the control voltage of the above VCO
, a bandpass filter (
BPF) and BPF whose amplitude is attenuated when passing through the BPF.
A phase synchronized circuit characterized in that it is provided with an amplifier (AMP) that amplifies the output signal f_o' to an amplitude necessary for the operation of a PC.