JP3179390B2 - PLL synchronization method at clock system switching - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL synchronization system at the time of clock system switching, and more particularly to a PLL synchronization system capable of converging in a short period of time by increasing a loop gain so as to increase the followability at the time of switching.

[0002]

2. Description of the Related Art As a prior art relating to a PLL circuit when a master clock is selected from a plurality of systems of clocks and the system is switched, Japanese Patent Application Laid-Open Nos. 8-288845, 5-227017, and 5-1666293 are known. There is one disclosed in Japanese Patent Publication No.

In the conventional PLL circuit configuration, when a master clock is selected from a plurality of systems of clocks and the system is switched, P
The output of the LL circuit fluctuated greatly, and it took time to stabilize.

[0004]

In a conventional PLL circuit, in order to shorten the time required for stabilization when the clock is switched, a wide pull-in range that covers the frequency fluctuation of the input signal is realized and a steady phase is obtained. It was necessary to increase the loop gain in order to reduce the error and obtain a faster response characteristic.However, when the loop gain was increased, the noise band increased, and the effect of input signal jitter and input noise increased. there were.

An object of the present invention is to solve the above-mentioned problems and to provide a PLL synchronization system in which, when a plurality of clocks are selected and the systems are switched, the time until the output of the PLL is stabilized is shortened.

[0006]

A phase comparator and an LPF
(Low-pass filter), a DC amplifier, a loop filter, and a PLL circuit including a VCO (Voltage Controlled Oscillator). When an input clock is selected and a system is switched, the input clock is generated from a phase difference of the input clock. In order to quickly converge the output fluctuations, a plurality of phase comparators, LPFs and DC amplifiers are used in the same combination, and the phase difference of the input clock is constantly detected, and the output is input to a differential amplifier having a gain of 1. I do.

By providing a switch at the output of the differential amplifier and adding the switch to the preceding stage of the loop filter when switching the system, the loop gain is instantaneously increased by the phase difference of the input clock.

After that, when the output phase of the PLL approaches the switched clock, the output of the differential amplifier decreases, and when the output falls below a certain level, the switch is turned off.

After the switch is turned off, the loop gain returns to the state before switching.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The PLL synchronization system of the present invention will be described in detail with reference to FIG. FIG. 1 is a block diagram showing an embodiment of a PLL synchronization system according to the present invention. In this embodiment, two clocks a and b are selected and the systems are switched.

The PLL synchronization system includes two sets of a selector, a phase comparator, an LPF, and a DC amplifier in parallel. That is, the selector 1a, the phase comparator 2a, the LPF 3a,
DC amplifier 4a, selector 1b, phase comparator 2b, L
PF 3b and DC amplifier 4b.

A differential amplifier 6, a switch (SW) 5, an adder 7, a loop filter 8, and a VCO 9 are provided downstream of the DC amplifiers 4a and 4b.

Now, it is assumed that the PLL circuit operates in synchronization with the clock a. In this state, the selector 1a
Has selected clock a, and the selected clock a
Is compared with the output clock of the VCO 9 by the phase comparator 2a, filtered by the LPF 3a, and amplified to a constant gain by the DC amplifier 4a. At this time,
Since the switch SW5 is OFF, the output of the DC amplifier 4a passes through the adder and is input to the VCO 9 via the loop filter 8. An output clock is generated from VCO 9.

On the other hand, the selector 1b selects the clock b, and the selected clock b is supplied to the phase comparator 2b.
b, the phase is compared with the output clock of the VCO 9 and LP
The signal is filtered by F3b and amplified to a constant gain by DC amplifier 4b.

The outputs of the DC amplifiers 4a and 4b are input to a differential amplifier 6 having a gain of 1 and the difference output is sent to SW5. This difference output indicates the phase difference between clock a and clock b. In this case, since the SW 5 is in the OFF state, the clock phase difference is not added to the adder 7.

A case where the master clock is switched from clock a to clock b in the above state will be described below with reference to FIG. FIG. 2 is a waveform timing chart for explaining the operation. The waveform (a) shows the output E of the loop filter 8, the waveform (b) shows the outputs A and B of the DC amplifiers 4a and 4b, the waveform (c) shows the output C of the differential amplifier 6, and the waveform (d) shows , SW5 are shown respectively.

When a system switching signal is generated, SW5 becomes O
N. The output C of the differential amplifier 6 becomes a gain of a phase difference required at the time of system switching, and changes to a signal D through SW5. The signal D is added to the output A of the DC amplifier 4a. The output of the adder 7 is passed through a loop filter 8 to VC
Since the signal is input to O9 and the output clock is adjusted, the loop gain is increased by the difference between the input clock a and the input clock b immediately after system switching, and the synchronization time can be reduced.

The waveform (a) in FIG. 2 shows a state in which the output E of the loop filter 8 has increased immediately after the system switching.

In the selector 1a to which the input clock a and the input clock b are input, the clock b is selected as the master clock in accordance with the system switching signal, and the phase comparator 2a compares the phase with the output clock of the VCO 9 to perform the LPF 3a And the DC amplifier 4a
And is amplified to a constant gain.

On the other hand, in the selector 1b to which the input clock a and the input clock b are inputted, the clock a not selected by the selector 1a is selected according to the system switching signal, and the phase comparator 2b selects the phase with the output clock. The signal is compared, filtered by the LPF 3b, and amplified to a constant gain by the DC amplifier 4b.

Outputs A and B of the DC amplifiers 4a and 4b are shown in a waveform (b) of FIG. The output A gradually increases when switching from clock a to clock b. Output B
Decreases gradually from clock b to clock a. At this time, the output C of the differential amplifier 6 is
As shown in waveform (c) of FIG. This means that the output phase of the PLL has become closer to the switched clock, ie, clock b.

After the system switching, when the output level of the differential amplifier 6 falls below a certain value, the switch SW5 is turned off to complete the system switching.

The above operation is summarized as follows. That is, when the clock switching signal is changed in the PLL circuit operating in synchronization with the phase of the input clock a to switch the system to the clock b, the output A of the DC amplifier 4a becomes as shown in FIG. It changes to follow the phase of clock b after switching. At this time, output A
Is sharply changed, the jitter characteristic of the PLL itself deteriorates, so that the output is performed with a slow change.

Similarly, when the selector b is also switched, immediately after the switching, the amount of phase change required by the PLL itself after the system switching becomes the output B of the DC amplifier 4b.

The difference between the output A and the output B is calculated by the differential amplifier 6
Is obtained as the output C, and is added to the output A again by the adder 7 through the switch SW5. SW5 is normally OFF, and is turned ON at the same time as system switching. Immediately after system switching, the output is output as output D from SW5. The output of the loop filter 8 changes abruptly like the output E, and the output phase of the VCO 9 is adjusted to the clock b after switching. Since this phase rapidly matches after a certain time, the level of the output C of the differential amplifier 6 drops, and when a certain threshold value is cut off, the SW5 is turned off to compensate for the phase change after the clock system switching. Output D is cut and normal P
Return to the LL feedback system and complete the system switching.

By the above operation, the phase amount of the clock to be newly synchronized is detected in advance, and when switching the clock system, the loop gain of the PLL is increased by the previously detected phase amount and stabilized. The time until the time can be shortened. After stabilization to a certain value or less, the phase amount added to the loop gain is cut, and it becomes possible to suppress the influence of input signal jitter and input noise.

In the above embodiment, the condition for turning off the switch SW5 is considered when the output of the differential amplifier 6 falls below a certain threshold value. However, as shown in FIG. Alternatively, when a certain threshold value is exceeded, the SW5 may be turned off.

[0028]

As described above, the present invention has the following effects.

That is, at the time of a normal PLL operation, the loop gain is reduced so that the influence of jitter or the like is reduced.
By using a PLL having a high degree of stability and a low tracking ability, a stable PLL output can be obtained irrespective of the fluctuation of the input clock phase. Although the performance is low, the loop gain is increased so as to increase the tracking performance, and there is an effect that convergence can be achieved in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL circuit according to one embodiment of the present invention.

FIG. 2 is a diagram showing output characteristics of main blocks in the embodiment of FIG.

FIG. 3 is a block diagram of a PLL circuit according to another embodiment of the present invention.

[Explanation of symbols]

 1a selector 1b selector 2a phase comparator 2b phase comparator 3a LPF 3b LPF 4a DC amplifier 4b DC amplifier 5 SW 6 differential amplifier 7 adder 8 loop filter 9 VCO A DC amplifier output B DC amplifier output C differential amplifier output D SW output E Loop filter output

Claims (5)

(57) [Claims] In a PLL synchronization method for selecting a master clock from two clocks and switching a clock system, a phase comparator for comparing the phase of a VCO output with an input clock, and an output of the phase comparator. LP to filter
F and a DC amplifier for amplifying the LPF output as one set,
Two sets are provided, one set of the two sets has a first selector for selecting a master clock from the two clocks, and the other set of the two sets is selected by the selector. A second selector for selecting a missing clock, detecting a phase difference between a VCO output and a clock input to the second selector in preparation for clock system switching, and including the clock in the one set. A differential amplifier that obtains a difference between an output of the DC amplifier and an output of the other set of DC amplifiers that is detecting a phase difference in preparation for clock system switching; and A switch that is turned on only immediately after system switching and is turned off under a predetermined condition; an adder that adds an output of the DC amplifier included in the one set and an output of the differential amplifier that has passed through the switch. , Loop filter and clock system when switching the PLL, characterized in that the VCO output of the loop filter is input, comprising filtering the output of the adder
Synchronous method. 2. The PLL synchronization system according to claim 1, wherein said predetermined condition is that the output of said differential amplifier exceeds a certain threshold. 3. The PLL synchronization system according to claim 1, wherein said predetermined condition is that an output of a DC amplifier included in said one set exceeds a certain threshold value. 4. In a PLL synchronization system for selecting a master clock from two clocks and switching clock systems, a first selector for selecting a master clock from two clocks, a selected master clock and a VCO A first phase comparator for comparing the phase with the output, a first LPF for filtering the output of the first phase comparator, and a first LF
A first DC amplifier for amplifying a PF output, a second selector for selecting a clock other than the master clock from the two clocks, and a selected clock and a VCO
A second phase comparator for comparing the phase with the output, a second LPF for filtering the output of the second phase comparator,
A second DC amplifier for amplifying a second LPF output; a differential amplifier for obtaining a difference between outputs of the first DC amplifier and the second DC amplifier; and an output of the differential amplifier being input. A switch that is turned on only immediately after the switching of the clock system and is turned off when the output of the differential amplifier exceeds a certain threshold value; an output of the first DC amplifier; and an output of the differential amplifier that has passed through the switch. And a loop filter for filtering the output of the adder; and a VCO to which the output of the loop filter is input.
Synchronous method. 5. A PLL synchronizing method for selecting a master clock from two clocks and switching clock systems, wherein a first selector for selecting a master clock from two clocks, a selected master clock and a VCO A first phase comparator for comparing the phase with the output, a first LPF for filtering the output of the first phase comparator, and a first LF
A first DC amplifier for amplifying a PF output, a second selector for selecting a clock other than the master clock from the two clocks, and a selected clock and a VCO
A second phase comparator for comparing the phase with the output, a second LPF for filtering the output of the second phase comparator,
A second DC amplifier for amplifying a second LPF output; a differential amplifier for obtaining a difference between outputs of the first DC amplifier and the second DC amplifier; and an output of the differential amplifier being input. A switch that is turned on only immediately after the switching of the clock system and is turned off when the output of the first DC amplifier exceeds a certain threshold value; an output of the first DC amplifier; and the differential amplifier that has passed through the switch. And a VCO to which the output of the loop filter is input. A PLL at the time of switching the clock system, comprising:
Synchronous method.