JP2004140688A - High-speed pll frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL (Phase Lock Loop) frequency synthesizer which can switch the output frequency at a high speed and which has a low spurious output frequency. <P>SOLUTION: A high-speed PLL frequency synthesizer comprises: a voltage-controlled oscillator 1 composing a phase lock loop; a frequency divider 2; a frequency phase comparator 3; a loop filter 4 for widening loop band width in switching the output frequency of the voltage-controlled oscillator 1 and narrowing the loop band width after approximately stabilizing the output frequency after switching; and a switch 5 for controlling the loop band width of the loop filter. The fluctuation in the output frequency of the voltage-controlled oscillator 1 in switching the loop band width is suppressed by inserting a resistor into a connection from the switch 5 to the capacitor of a lag lead filter, thereby realizing a high-speed response of the PLL frequency synthesizer. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a high-speed response of a PLL frequency synthesizer used in the communication field.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a PLL frequency synthesizer used in the communication field is disclosed in the Patent Publication Building (for example, see Patent Document 1).
[0003]
FIG. 8 shows a conventional PLL frequency synthesizer. In FIG. 8, 1 is a voltage controlled oscillator, 2 is a frequency divider that receives the output of the voltage controlled oscillator 1 as an input, 3 is a frequency phase comparator that receives the output of the frequency divider 2 and a reference signal, and 4 is A loop filter 5 for changing the filter characteristic by the switch 5 is a switch for controlling a second branch output obtained by branching the output of the frequency-phase comparator 3 into a plurality of parts, and controlling the second branch output to form a loop. A switch for changing the filter characteristics of the filter 4. The loop filter 4 includes at least a lag-lead filter 6 and a capacitor 7, and the lag-lead filter 6 includes a first resistor 20, a second resistor 21, and a capacitor 22, and one end of the first resistor 20. Is connected to a first branch output of the frequency phase comparator 3, the other end of the first resistor 20 is connected to one end of the second resistor 21, and the voltage control terminal of the voltage controlled oscillator 1 One end of the capacitor 7 is connected, the other end of the capacitor 7 is grounded, the other end of the second resistor 21 is grounded via the capacitor 7 and the other end of the frequency phase comparator 3 is connected via the switch 5. 2 branch outputs. When the output frequency of the voltage controlled oscillator 1 is switched or when the PLL composed of 1 to 7 is switched from non-operation to operation, the switch 5 is turned on, and the loop bandwidth of the phase locked loop is set by the second branch output. By widening the frequency and pulling in the frequency at high speed and turning off the second branch output at a predetermined time when the output frequency is almost stabilized, the loop bandwidth is narrowed to obtain desired phase noise and spurious characteristics. Control the phase locked loop. However, the operation will be described with reference to FIG. 9. When the second branch output is stopped by the switch 5, the “control voltage” of the voltage controlled oscillator 1 is changed due to the potential difference between “voltage A” and “voltage B”. The output frequency fluctuates, and the “output frequency” that should have been pulled in at high speed shifts. After the shift, the PLL lock-in response becomes slow because the loop bandwidth is narrow and pulling in at low speed.
[0004]
[Patent Document 1]
JP 05-48454 A
[Problems to be solved by the invention]
2. Description of the Related Art Conventionally, in a PLL frequency synthesizer used in the field of communication processing, there has been a problem of speeding up a PLL lock response in order to perform high-speed frequency switching.
[0006]
The present invention solves the above-mentioned conventional problem, and suppresses the fluctuation of the control voltage of the voltage controlled oscillator 1 when the second branch output is stopped, stabilizes the output frequency, and enables high-speed response. It is an object to provide a PLL frequency synthesizer.
[0007]
[Means for Solving the Problems]
In order to achieve this object, in the PLL frequency synthesizer according to the present invention, the second branch output of the frequency phase comparator 3 is connected to the capacitor via the third resistor of the lag-lead filter 6 so that the second This is a PLL frequency synthesizer that suppresses fluctuations in the control voltage of the voltage controlled oscillator 1 when the branch output is stopped, speeds up frequency switching by stabilizing the output frequency, and enables a high-speed response of the PLL.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
The invention according to claim 1 of the present invention provides a voltage controlled oscillator 1, a frequency divider 2 having an input of the output of the voltage controlled oscillator, and a frequency phase comparison having an output of the frequency divider and a reference signal as inputs. , A loop filter 4, and the output of the frequency phase comparator 3 are branched into a plurality of parts, a first branch output is connected to the loop filter 4, and a second branch output is connected to the output frequency of the voltage controlled oscillator 1. When switching the PLL, or when switching the PLL composed of 1 to 5 from non-operation to operation, the switch 5 is turned on, the loop bandwidth of the phase-locked loop is widened by the second branch output, and the frequency is rapidly increased. In a PLL frequency synthesizer having a switch 5 for controlling to reduce a loop bandwidth by turning off a second branch output at a predetermined time when a pull-in output frequency is substantially stabilized. The loop filter 4 includes at least a lag-lead filter 6 and a capacitor 7. The lag-lead filter 6 includes a first resistor, a second resistor, a third resistor, and a capacitor, and outputs the second branch output. A control is provided to suppress a potential difference between a voltage charged in the capacitor of the lag-lead filter and a voltage charged in the capacitor 7 by connecting to a capacitor of the lag-lead filter via a third resistor. Thus, the control voltage of the voltage controlled oscillator 1 when stopping the second branch output is suppressed, the output frequency can be stabilized, and the lock response of the PLL at the time of frequency switching can be speeded up. .
[0009]
The invention according to claim 2 of the present invention includes the same 1 to 7 as in claim 1, and divides the first resistor of the lag lead filter into two or more connected in series, and each division point is A PLL frequency synthesizer which is grounded via a resistor. The PLL frequency synthesizer has the same function as that of claim 1, and further comprises a lag filter composed of a divided resistor and a capacitor connected thereto, and a phase noise outside the loop band. Has the effect of improving spurious characteristics.
[0010]
The invention according to claim 3 of the present invention includes the same 1 to 7 as in claim 1 or claim 2, and further includes a second branch output of the frequency / phase comparator 3 controlled by the switch 5, In a PLL frequency synthesizer having a bypass resistor connected between a second resistor and the third resistor, the PLL frequency synthesizer has the same operation as the first and second embodiments, and the switch 5 is turned off by the bypass resistor. In the state, the operation noise from the second branch output to the lag lead filter 6 is suppressed, and the phase noise and spurious characteristics can be improved.
[0011]
The invention according to claim 4 of the present invention comprises the same 1 to 7 as in claims 1 to 3, and has a third branch output in the plurality of outputs of the frequency phase comparator 3. 3. The PLL frequency synthesizer controlled by the switch 8 and connected to the dividing point of the first resistor according to claim 2, which has the same operation as in claim 1, 2, and 3, and further includes a loop at the time of pull-in. This has the effect that the bandwidth can be further widened and higher speed pull-in can be performed.
[0012]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0013]
FIG. 1 shows a diagram of a PLL frequency synthesizer according to the first embodiment. In FIG. 1, 1 is a voltage-controlled oscillator, 2 is a frequency divider, 3 is a frequency-phase comparator, 4 is a loop filter, 5 is a switch for controlling a second branch output of the frequency-phase comparator, and 6 is a first switch. The lag-lead filter 7 includes a resistor 30, a second resistor 31, a third resistor 32, and a capacitor 33. One end of the lag-lead filter 7 is connected to one end of the first resistor 30 of the lag-lead filter 6. Is connected to the control terminal of the other, and the other end is grounded.
[0014]
The operation of the PLL frequency synthesizer of the first embodiment configured as described above will be described below with reference to FIG. In FIG. 2, when the "output frequency" is switched or when the PLL composed of 1 to 5 is switched from the non-operating state to the operating state, the switch 5 is turned on, and the second of the frequency phase comparator 3 is turned on. Since the branch output is connected to the loop filter, the loop bandwidth of the synchronous loop is widened, and after a lapse of a predetermined time during which the output frequency after the switching is substantially stabilized, the switch 5 is turned off by the "loop band switching signal" and the second The loop bandwidth is narrowed by stopping the branch output. At this time, the time constants of “voltage A” and “voltage B” are matched by the third resistor 32 connected between the second branch output and the capacitor 33 of the lag-lead filter, so that the second The fluctuation of the "control voltage" of the voltage controlled oscillator 1 when the branch output is stopped can be suppressed, the "output frequency" can be stabilized, and the PLL lock response at the time of frequency switching can be speeded up.
[0015]
With reference to FIG. 3, a description will be given of a characteristic due to a difference in time constant between “voltage A” and “voltage B”. In the state where the resistor 32 is not provided or the value is small, the time constant of the “voltage A” is smaller than the time constant of the “voltage B”. Therefore, there is a potential difference when the switch 5 is switched, and the frequency pull-in time is delayed. In addition, when the value of the resistor 32 is large, the time constant of “voltage A” is larger than the time constant of “voltage B”. Therefore, there is a potential difference when the switch 5 is switched, and the frequency pull-in time is delayed. In the case of the value of the resistor 32 that makes the time constants of “voltage A” and “voltage B” similar, there is no potential difference when the switch 5 is switched, so that the frequency pull-in time is shortened.
[0016]
Also, if the spurious characteristics of the conventional filter including the first resistor 20, the second resistor 21, and the capacitor 22 in FIG. 8 are known, the “value of the resistor 20” = “the value of the resistor 30” and the “capacitor By using a filter that satisfies “value of 22” = “value of capacitor 33” and “value of resistor 21” = “value of resistor 31” + “value of resistor 32”, spurious characteristics can be obtained as before and response characteristics can be obtained. Can be speeded up.
[0017]
Next, FIG. 4 shows a diagram of a PLL frequency synthesizer according to the second embodiment, which is an embodiment according to claim 2. In FIG. 4, reference numerals 1 to 7, 31, 32, and 33 are the same as those in the first embodiment, and the first resistance of the divided first resistance of the lag lead filter 6 is 34, Reference numeral 35 denotes a resistor, and reference numeral 36 denotes a capacitor having one end connected to a connection point between the resistors 34 and 35 and the other end grounded.
[0018]
The PLL frequency synthesizer according to the second embodiment configured as described above has the same effect as the first embodiment, and further includes a lag filter configured by the resistor 34 and the capacitor 36, Phase noise and spurious characteristics outside the loop band can be improved.
[0019]
In this embodiment, the lag filter including the resistor 34 and the capacitor 36 is provided in one stage, but two or more lag filters may be added.
[0020]
Next, FIG. 5 shows a diagram of a PLL frequency synthesizer according to the third embodiment, which is an embodiment according to claim 2. In FIG. 5, reference numerals 1 to 7, 31, 32, and 33 are the same as those in the first embodiment, and the first resistance of the divided first resistance of the lag-lead filter 6 is 37 and the second resistance is 37. Reference numeral 38 denotes a resistor, 39 denotes a third resistor, and 40 denotes a capacitor having one end connected to a connection point between the resistors 37 and 38 and the other end grounded.
[0021]
The PLL frequency synthesizer according to the third embodiment configured as described above has the same effect as the first embodiment, and also has a lag filter including the resistor 37 and the capacitor 40, and the resistor 39. By providing the lag filter constituted by the capacitor 7, phase noise and spurious characteristics outside the loop band can be improved.
[0022]
Next, FIG. 6 shows a diagram of a PLL frequency synthesizer according to the fourth embodiment, which is an embodiment according to claim 3. In FIG. 6, 1 to 7, 31, 32, and 33 are the same as those in the first embodiment, and the second branch output of the frequency / phase comparator 3 controlled by the switch 5, the resistor 31, and the The bypass resistor 41 is connected between the resistors 32.
[0023]
The PLL frequency synthesizer according to the fourth embodiment configured as described above has the same effect as that of the first embodiment, and further includes the bypass resistor 41 so that when the switch 5 is off, The operation noise from the second branch output to the lag lead filter 6 can be suppressed, and the phase noise and spurious characteristics can be improved.
[0024]
Next, FIG. 7 shows a diagram of a PLL frequency synthesizer according to the fifth embodiment, which is an embodiment according to claim 4. In FIG. 7, 1 to 7 and 31 to 36 are the same as those of the second embodiment, and have a third branch output among a plurality of outputs of the frequency phase comparator 3 and are controlled by the switch 8. It is connected to the connection point between the resistor 34 and the resistor 35. When the output frequency of the voltage controlled oscillator 1 is switched by the "loop band switching signal 2" or when the PLL composed of 1 to 5 is switched from the non-operating state to the operating state, the switch 8 is turned on to set the loop. The loop bandwidth is narrowed by widening the bandwidth, pulling in the output frequency at high speed, and turning off the third branch output at a predetermined time when the output frequency after switching is substantially stabilized.
[0025]
The PLL frequency synthesizer of the fifth embodiment configured as described above has the same effects as those of the first and second embodiments, and further includes a third branch output controlled by the switch 8. Thereby, the loop bandwidth at the time of pull-in can be further widened, and there is an effect that higher-speed pull-in can be performed.
[0026]
In the present embodiment, the control signal of the switch 5 is a “loop band switching signal” and the control signal of the switch 8 is “loop band switching signal 2”. However, even if the control signals of the switch 5 and the switch 8 are the same. Good.
[0027]
Further, in the present embodiment, the first to third branch outputs are used in the plurality of branched outputs of the frequency phase comparator 3, but the fourth or more branch outputs and the switches for controlling the same may be connected. Good.
[0028]
【The invention's effect】
As described above, the present invention provides a PLL frequency synthesizer having a control for stabilizing the control voltage of a voltage controlled oscillator when switching from a high-speed loop filter to a low-speed loop filter, thereby increasing the lock response of the frequency-locked PLL. Thus, it is possible to realize an excellent PLL frequency synthesizer.
[Brief description of the drawings]
FIG. 1 is a diagram of a PLL frequency synthesizer according to a first embodiment of the present invention; FIG. 2 is a diagram (1) for explaining the operation of FIG. 1;
FIG. 3 is a diagram (2) for explaining the operation of FIG. 1;
FIG. 4 is a diagram of a PLL frequency synthesizer according to a second embodiment of the present invention. FIG. 5 is a diagram of a PLL frequency synthesizer according to a third embodiment of the present invention. FIG. 6 is a PLL according to a fourth embodiment of the present invention. FIG. 7 is a diagram of a frequency synthesizer. FIG. 7 is a diagram of a PLL frequency synthesizer according to a fifth embodiment of the present invention. FIG. 8 is a diagram of a conventional PLL frequency synthesizer.
REFERENCE SIGNS LIST 1 voltage-controlled oscillator 2 frequency divider 3 frequency-phase comparator 4 loop filter 5 switch 6 lag-lead filter 7 capacitor 8 switch 20 in fifth embodiment of present invention first resistor 21 of conventional lag-lead filter 21 conventional lag Second resistor 22 of the lead filter 22 Conventional lag-lead filter capacitor 30 First resistor 31 of the lag-lead filter of the present invention Second resistor 32 of the lag-lead filter of the present invention Resistor 33 Capacitor of lag-lead filter 34 First resistor 35 obtained by dividing resistor 30 in the second embodiment of the present invention Second resistor 36 obtained by dividing resistor 30 in the second embodiment of the present invention The capacitor 37 connected to 34 in the second embodiment A first resistor 38 obtained by dividing the resistor 30 in the third embodiment. A second resistor 39 obtained by dividing the resistor 30 in the third embodiment of the present invention. A third resistor 39 obtained by dividing the resistor 30 in the third embodiment of the present invention. The resistance 40 of the capacitor 41 connected to 37 in the third embodiment of the present invention The bypass resistance in the fourth embodiment of the present invention

Claims (4)

A voltage-controlled oscillator 1, a frequency divider 2 that receives an output of the voltage-controlled oscillator as an input, a frequency-phase comparator 3 that receives an output of the frequency divider 2 and a reference signal, and a loop filter 4. When the output of the frequency phase comparator 3 is branched into a plurality of parts, a first branch output is connected to a loop filter 4, and a second branch output is controlled by a switch 5, so that the output frequency of the voltage controlled oscillator 1 is switched. Alternatively, when the PLL composed of 1 to 5 is switched from the non-operation to the operation state, the switch 5 is turned on, the loop bandwidth of the phase-locked loop is widened by the second branch output, and the output frequency is pulled in at high speed and switched. The desired phase noise and spurious characteristics can be obtained by reducing the loop bandwidth by turning off the second branch output at a predetermined time when the subsequent output frequency is substantially stabilized. In the frequency synthesizer according to the first embodiment, the loop filter 4 includes at least a lag-lead filter 6 and a capacitor 7, and the lag-lead filter 6 includes a first resistor, a second resistor, a third resistor, and a capacitor. One end of the first resistor is connected to a first branch output of the frequency-phase comparator 3, and the other end of the first resistor is connected to one end of the second resistor. A terminal is connected to one end of the capacitor 7, the other end of the capacitor 7 is grounded, the other end of the second resistor is connected to one end of the third resistor, and the frequency phase comparison is performed via a switch 5. A frequency synthesizer connected to a second branch output of the device and the other end of the third resistor is grounded via the capacitor. 2. The frequency synthesizer according to claim 1, wherein the first resistor is divided into two or more resistors connected in series, and each division point is grounded via a capacitor. 3. The frequency synthesizer according to claim 1, wherein the second branch output is connected to the second resistor and the third resistor via the switch 5 and a bypass resistor. The output of the frequency / phase comparator (3) having a third branch output, the third branch output being controlled by a switch (8) and connected to a dividing point of the first resistor according to claim 2. The frequency synthesizer according to claim 2 or 3.

Images