JPH04196275A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the improvement of a source-drain withstand voltage, the improvement of the reliability of hot carriers, the improvement of a current driving capacity and the like by a method wherein each one part of source and drain electrode layers on one pair of low-concentration impurity regions in a substrate is formed into a single crystal region and a low-concentration impurity concentration distribution is set in each of these single crystal region. CONSTITUTION:Single crystal semiconductor regions 6b are respectively provided in each one part of source and drain electrode layers, which are respectively positioned on one pair of N-type low-concentration impurity regions 3 and consist of a polycrystalline semiconductor, and moreover, an impurity concentration distribution is set in each of these regions 6b, parts which come into contact to the upper parts of the regions 6b and polycrystalline semiconductor regions 6a, are formed as N-type high-concentration impurity regions 3b and the vicinities of insulating films 4b and the regions 3 are formed as N-type low-concentration impurity regions 3a. As a result, the regions 3 can be formed in a self-alignment manner by the diffusion of impurities fro the regions 3a in the regions 6b and moreover, a concentration distribution in the regions 3 can be arbitrarily set by forming the impurity regions in the regions 6b using an ion-implantation method. Thereby, the improvement of a source-drain withstand voltage, the improvement of the reliability of hot carries, the improvement of a current driving capacity and the like are contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an MIS type semiconductor device.

[Conventional technology]

MIS field effect transistors are one of the important components in semiconductor integrated circuit devices.

As semiconductor integrated circuit devices become more highly integrated, various structures of MIS field effect transistors have been proposed.

For example, a transistor whose source and drain are formed using diffusion of impurities from polysilicon (Polisi
There are five source drain transistors (hereinafter referred to as PSD transistors). 20PS
Since the D transistor is formed by a source-to-ruin junction or self-alignment, it has the advantage of being suitable for high integration.

Conventional PSD) A transistor will be explained.

The PSD)-transistor described below is shown, for example, in Japanese Patent Application Laid-Open No. 16573/1983.

FIG. 2 is a cross-sectional structural diagram of this PSD transistor.

A thick insulating film 2 for element isolation is formed in a predetermined region of the main surface of the p-type semiconductor substrate 1.

In the main surface region of the p-type semiconductor substrate 1 surrounded by the isolation insulating film 2, a pair of n-type impurity regions 3c, 3 are separated by a predetermined distance.
c is formed. A pair of n-type impurity regions 3c, 3c
A source/drain electrode layer 6 made of conductive polycrystalline silicon is connected to the surface of the electrode. The source/drain electrode layer 6 extends to the upper part of the isolation insulating film 2.

The main surface region of the p-type semiconductor substrate 1 sandwiched between a pair of n-type impurity regions 3c, 3c is a channel region IO of a transistor.
Configure. On the surface of the channel region 10, relatively thin insulating films 4a and 4b are formed. Further, a gate electrode 5 made of polycrystalline silicon imparted with conductivity is formed on the surfaces of the insulating films 4a and 4b. Gate electrode 5 is insulated and isolated from channel region IO by insulating film 4a and from source/drain electrode layer 6 by insulating film 4b. Further, a portion of the gate electrode 5 extends above the source/drain electrode layer 6. PSD) The surface of the transistor is covered with a thick interlayer insulating layer 7.

A contact hole 8 reaching the source/drain electrode layer 6 is formed in the interlayer insulating layer 7 . Wiring layer 9 is connected to source/drain electrode layer 6 through contact hole 8 .

The feature of such a PSD transistor structure is that the n-type impurity region 3c is formed in self-alignment with the source/drain electrode layer 6, and extends over a part of the gate electrode 5 or the upper part of the source/drain electrode layer 6. That's what I'm doing.

Since the PSD transistor is configured as described above, contact can be made on the isolation insulating film, the source/train junction area is small, and the junction capacitance is small.

As described above, the PSD transistor has a structure suitable for high integration and high speed operation.

[Problem to be solved by the invention]

However, since the conventional PSD transistor is configured as described above, a pair of n-type impurity regions 3c, 3
Since c is formed by thermal diffusion of impurities from the source/drain electrode 6 made of polycrystalline silicon, it is difficult to arbitrarily set the impurity concentration distribution compared to an n-type impurity region formed by ion implantation. It has been extremely difficult to perform so-called "drain-gate engineering" on PSD transistors, which improves source-drain breakdown voltage, hot carrier reliability, and current drive capability.

This invention was made to solve the above-mentioned problems, and it
The purpose is to obtain a semiconductor device that can be effectively applied to SD type transistors and that can improve breakdown voltage between the source and drain, improve hot carrier reliability, and improve current drive capability. .

[Means to solve the problem]

A semiconductor device according to the present invention includes a pair of second conductivity type low crystals formed at a predetermined distance in a first conductivity type single crystal region surrounded by an isolation insulating film formed on a main surface of a semiconductor substrate. A single crystal semiconductor region of a second conductivity type having the same crystal axis as the semiconductor substrate formed on the doped region, at least the low concentration region, a side surface of the single crystal semiconductor region and a main surface of the semiconductor substrate between the pair of single crystal semiconductor regions. an insulating film formed above, an electrode disposed in contact with the insulating film on the bottom and side surfaces, an electrode formed on the side of the single crystal semiconductor region and over the isolation insulating film,
Equipped with a polycrystalline semiconductor region fused with a single-crystalline semiconductor region,
The polycrystalline semiconductor region is heavily doped with a second conductivity type, and the second conductivity type impurity concentration in the single crystal semiconductor region is
It is characterized in that the concentration is set to be low from the top side to the bottom side, and from the polycrystalline semiconductor side to the side insulating film side.

[Effect]

In the semiconductor device according to the present invention, a single crystal semiconductor region is provided in the source/drain electrode layer located above at least one pair of second conductivity type impurity regions in a PSD (PSD) run transistor. By forming the impurity region using the implantation method, the impurity concentration distribution of the n-type impurity region can be set arbitrarily, and it becomes possible to perform so-called "train gate engineering" on the PSD type transistor.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a semiconductor device according to an embodiment of the present invention. In the figure, a thick isolation insulating film 2 for element isolation is formed in a predetermined region on the main surface of a p-type semiconductor substrate 1. A pair of n-type low concentration impurity regions 3, 3 are formed at a predetermined distance in a single crystal region on the main surface of p-type semiconductor substrate 1 surrounded by isolation insulating film 2.

On the pair of n-type low concentration impurity regions 3, 3 is a semiconductor substrate l.
A single crystal semiconductor region 6b having the same crystal axis is formed. This single crystal semiconductor region 6b is fused with the polycrystalline semiconductor region 6a on the isolation insulating film 2.

Further, an insulating film 4b is formed on the side wall of the single crystal semiconductor region 6b.
In addition, a gate insulating film 4a is formed on the semiconductor substrate 1 between the pair of single crystal regions 6b, 6b. A gate electrode 5 is formed in contact with the upper part of the gate insulating film 4a and the side surface of the insulating film 4b. Furthermore, a portion of gate electrode 5 extends above single crystal semiconductor region 6b.

Polycrystalline semiconductor region 6a is heavily n-type doped.

The upper part of the single crystal semiconductor region 6b and the polycrystalline semiconductor region 6
The part in contact with a is an n-type high concentration region 3b, and the vicinity of the insulating film 4b of the single crystal semiconductor region 6b and the vicinity of the n-type low concentration impurity region 3 is an n-type low concentration impurity region 3a having a gentle impurity concentration gradient. be.

The surface of the transistor according to this embodiment is covered with a thick interlayer insulating layer 7. A contact hole 8 is formed in the interlayer insulating layer 7 to reach the heavily doped polycrystalline semiconductor region 6a. Wiring layer 9 is connected to polycrystalline semiconductor region 6a through contact hole 8.

In the MIS type semiconductor device of this embodiment having such a configuration, a single crystal semiconductor is used in a part of the source/train electrode layer made of a polycrystalline semiconductor located on a pair of n-type low concentration impurity regions 3°3. A region 6b is provided, and an impurity concentration distribution is provided in this single crystal semiconductor region 6b, and the upper portion thereof and the portion in contact with the polycrystalline semiconductor region 6a is an n-type high concentration impurity region 3b.

The vicinity of the insulating film 4b and the vicinity of the n-type low concentration impurity region 3 are
Since the type low concentration impurity region 3a is used, the impurity region 3 can be formed in a self-aligned manner by impurity diffusion from the low concentration n type impurity region 3a of the single crystal semiconductor region 6b. By forming the impurity region using , the concentration distribution of the impurity region 3 can be set arbitrarily.

Therefore, according to this embodiment, it is possible to improve the breakdown voltage between the source and the train, improve the reliability of hot carriers, and improve the current drive ability, making so-called "drain-gate engineering" effective for PSD transistors. I can do what I want to do.

In addition, although the NMO3 semiconductor device was illustrated in the above embodiment, it may be a PM○S semiconductor device in which the n-type impurity is replaced with a p-type impurity, and the p-type impurity is replaced with an n-type impurity.

〔Effect of the invention〕

As described above, according to the present invention, a part of the source/train electrode layer in a PSD transistor, i.e., a part in the substrate.
Since the pair of low concentration impurity regions is made into a single crystal region and a low concentration impurity concentration distribution is set in this single crystal region, P
This has the effect of making it possible to obtain a PSD-type high-performance MO3) transistor that has the advantages of an SD transistor, such as improved source-drain breakdown voltage, improved hot carrier reliability, and improved current drive capability.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. ] is a p-type semiconductor substrate, 2 is an isolation insulating film, 3 is a low concentration n-type impurity region in the semiconductor substrate, 3a is a low concentration n-type impurity region, 3b is a high concentration n-type impurity region, 4a is a gate insulating film, 4b is an insulating film, 5 is a gate electrode, 6a is a polycrystalline semiconductor region, 6b is a single crystal semiconductor region, 7 is an interlayer insulating layer, 8 is a contact hole, and 9 is a wiring. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A MIS type semiconductor device formed on the main surface of a semiconductor substrate, in which a single crystal region of a first conductivity type surrounded by an isolation insulating film formed on the main surface of the semiconductor substrate is separated by a predetermined distance. a pair of low-concentration regions of a second conductivity type formed by using a semiconductor substrate; an insulating film formed on a side surface of a semiconductor region and on the main surface of the semiconductor substrate between a pair of single crystal semiconductor regions; an electrode disposed with a bottom surface and a side surface in contact with the insulating film; and the single crystal semiconductor region. a polycrystalline semiconductor region fused with the single crystal semiconductor region formed on the side of the isolation insulating film, the polycrystalline semiconductor region being heavily doped with a second conductivity type; The second conductivity type impurity concentration in the single crystal semiconductor region is set to be low from the top to the bottom, and to be low from the highly doped polycrystalline semiconductor side to the side insulating film side. A semiconductor device characterized by: