JPH0411771A - Polycrystalline silicon transistor and semiconductor device - Google Patents

Abstract

PURPOSE:To obtain desired characteristics by providing gate electrodes on and underneath a polycrystalline silicon layer, and providing offsets for one to source region and for the other drain region. CONSTITUTION:A lower gate electrode 1 is provided under a polycrystalline silicon layer 2 through an insulating film, and an offset is provided to one of a source region 4 and a drain region 5. An upper gate electrode 3 provided above the layer 2 through an insulating film is provided with an offset to the other region not provided with an offset to the electrode 1. Then, the layer 2 can increase an ON current and decrease an OFF current to reduce variations in ON.OFF current characteristics due to a deviation. Thus, stable transistor characteristics are obtained to suppress an irregularity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Fields] The present invention is applicable to polycrystalline silicon transistors in which a source region and a drain region are formed in a polycrystalline silicon layer formed on a substrate, and as a load element of a static memory cell. The present invention relates to a semiconductor memory device using polycrystalline silicon transistors.

[Prior Art] FIG. 4 is a sectional view showing an example of a conventional polycrystalline silicon transistor. SiO2 is formed on the polycrystalline silicon layer 32.
A gate electrode 33 is patterned through the film 39. The polycrystalline silicon layer 32 except for the region immediately below the gate electrode 33 has source/drain regions 34 and 35.
are formed at appropriate length intervals.

In this way, the conventional polycrystalline silicon transistor is a general SOI (S111con On In5ula
tor or Sem1 conductor On In5
It has a structure between a transistor with an ulator structure and an inter-circuit structure.

In order to reduce the off-state current of polycrystalline silicon transistors, the inventors proposed a polycrystalline silicon transistor in which the gate electrode is offset from the source or drain region (Nikkei Microdevice 3
Monthly issue 1988, pp. 123-130).

FIG. 5 is a sectional view showing this polycrystalline silicon transistor.

The polycrystalline silicon layer 32 has source/drain regions 44 .
45 is formed, and a gate electrode 33 is formed on this polycrystalline silicon layer 32 via Si0211E39. In this polycrystalline silicon transistor, the source/drain region 45 and the gate electrode 33 are separated by an offset amount S3 in plan view.

In a polycrystalline silicon transistor having a gate electrode offset with respect to the source/drain region in this way, by optimizing the offset amount S3 etc., it can be compared to the polycrystalline silicon transistor shown in FIG. As a result, the off-state current can be reduced to about 1/10 without substantially reducing the on-state current.

By the way, polycrystalline silicon transistors have a relatively small off-state current and a large on-state current. For this reason, it has been proposed to use polycrystalline silicon transistors as load elements in static memory cells (IEEE E
electron Device Letters.

EDL-4272-274 pages 1383). The inventors also proposed applying polycrystalline silicon transistors to large-capacity static memories (VLSI
5YIIIPOSIυM ON VLSI CIRC
lllTS DEGEST 0FTECHNICAL
PAPER pp. 549-50 1988).

[Problems to be Solved by the Invention] However, the conventional polycrystalline silicon transistor shown in FIG. 4 has a drawback in that the off-state current is not sufficiently reduced. Furthermore, although the polycrystalline silicon transistor with the offset gate structure shown in FIG. 5 has an improved ratio of on-current to off-current compared to the polycrystalline silicon transistor without the offset gate structure, it has the following problems. .

That is, it is difficult to maintain the offset amount S3 constant due to variations in the manufacturing process. Therefore, it is not possible to stably obtain predetermined transistor characteristics. especially,
There are large variations in the off-state current characteristics of transistors. Furthermore, the on-current is slightly reduced compared to a polycrystalline silicon transistor that does not have an offset structure.

On the other hand, a transistor used as a load element of a static memory cell is required to have an extremely small off-state current (leakage current) and a large on-state current. In particular, in large-capacity static memories, it is necessary to minimize the off-state current and increase the on-state current per unit length, and conventional polycrystalline silicon transistors are insufficient. Therefore, a conventional semiconductor memory device including a polycrystalline silicon transistor has a problem in that standby current (off-state current of a load element of a memory cell) increases when the capacity of a static memory increases.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a polycrystalline silicon transistor that can easily obtain predetermined transistor characteristics, has a small off-state current and a large on-state current, and a semiconductor memory device equipped with this polycrystalline silicon transistor and has a small standby current. do.

[Means for Solving the Problems] A polycrystalline silicon transistor according to the present invention includes a polycrystalline silicon layer provided with a source region and a drain region,
a lower gate electrode disposed below the polycrystalline silicon layer via an insulating film and offset from one of the source region and the drain region;
An upper gate electrode is provided above the polycrystalline silicon layer with an insulating film interposed therebetween and offset from the other of the source region and the drain region.

A semiconductor memory device according to the present invention includes a polycrystalline silicon layer provided with a source region and a drain region, and one of the source region and the drain region disposed below the polycrystalline silicon layer with an insulating film interposed therebetween. a lower gate electrode provided with an offset with respect to a region thereof; and a lower gate electrode provided with an offset with respect to the other region of the source region and the drain region, which is disposed above the polycrystalline silicon layer with an insulating film interposed therebetween. The static memory cell is characterized in that a polycrystalline silicon transistor constituted by an upper gate electrode exists as a load element of the static memory cell.

[Operation] In the polycrystalline silicon transistor according to the first invention of the present application, a lower gate electrode and an upper gate electrode are provided respectively below and above the polycrystalline silicon layer in which the source region and the drain region are provided. The lower gate electrode is offset from one of the source and drain regions, and the upper gate electrode is offset from the other of the source and drain regions. There is. As described above, since the polycrystalline silicon transistor according to the present invention has two gate electrodes, the on-current is extremely large compared to the conventional transistor. Further, since both of these two gate electrodes are offset from the source region or the drain region, the off-state current is small.

Furthermore, if misalignment (positional misalignment) occurs during manufacturing,
Although the offset amount of one gate electrode decreases and the off-state current increases, the offset amount of the other gate electrode remains unchanged or increases.

Therefore, the amount of increase in off-state current when misalignment occurs is smaller than in conventional polycrystalline silicon transistors.

A semiconductor memory device including a polycrystalline silicon transistor according to the second invention of the present application has a small standby current because the polycrystalline silicon transistor having the above-described structure is used as a load element of a static memory cell.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing a polycrystalline silicon transistor according to an embodiment of the present invention.

A lower gate electrode 1 is formed in a predetermined shape on the soil of a substrate (not shown), and the substrate including the gate electrode 1 is covered with a SiO2 film 8.

A polycrystalline silicon layer 2 is formed on this Sio2 film 8, and in this polycrystalline silicon layer 2, source/drain regions 4.5 doped with impurities at a high concentration are arranged at appropriate intervals. They are formed spaced apart from each other. A 5i02 film 9 is formed on this polycrystalline silicon layer 2, and an upper gate electrode 3 is selectively formed on this SiO2 film θ. This upper gate electrode 3 is electrically connected to the lower gate electrode 1.

The lower gate electrode 1 is offset from the source/drain region 4 by an offset amount S2 in plan view, and serves as an offset gate electrode with respect to the source/drain region 4. Further, the upper gate electrode 3 is offset from the source/drain region 5 by an offset amount SI in plan view, and serves as an offset gate electrode with respect to the source/drain region 5.

Since the polycrystalline silicon transistor according to this embodiment has two gate electrodes, an on-current that is more than twice that of a conventional polycrystalline silicon transistor can be obtained. Furthermore, since one of the gate electrodes 1 and 3 serves as an offset gate electrode with respect to the source region, and the other serves as an offset gate electrode with respect to the drain region, off-state current is small.

Next, a method for manufacturing a polycrystalline silicon transistor according to this example will be described.

First, the normal MOS FET (Metal O
xideSemiconductor Field E
A gate electrode 1 made of polycrystalline silicon is formed on a substrate in the same manner as in the method for manufacturing a gate electrode of FFECT Transistor. This gate electrode 1 is, for example, an ordinary SOI-structured MOS formed on a silicon substrate.
It may also serve as the gate electrode of the FET.

Next, by CVD (vapor phase growth) method, S is applied to the entire surface of the substrate.
An in2 film 8 is deposited. After that, S on the gate electrode 1
The in2 film 8 is removed to expose the gate electrode 1. Then, by the CVD method, Sin2 is again deposited on the gate electrode 1.
A film 8 is deposited to form the gate oxide.

Next, an amorphous silicon film is formed to a predetermined thickness (several 10 to 1000 layers) by low pressure CVD.

Thereafter, a polycrystalline silicon layer 2 is formed by subjecting this amorphous silicon film to a heat treatment to make it crystallized.

Next, an impurity such as phosphorus or arsenic is implanted into this polycrystalline silicon layer 2 at a predetermined dose by ion implantation to make this polycrystalline silicon layer 2 an N type.

Next, a 5in2 film 9 as a gate oxide film is formed above the polycrystalline silicon layer 2 by CVD. At this time, the thickness of this gate oxide film (Sin2 film 9) may be different from the thickness of the gate oxide film (Sin2 film 8) below the polycrystalline silicon layer 2.

Next, a gate electrode 3 is formed above the polycrystalline silicon layer 2, similar to a normal MOSFET. The upper gate electrode 3 is formed, for example, at a position offset by 0.2 to 0.3 μm in the gate length direction with respect to the lower gate electrode 1 and has the same gate length.

Next, a resist film is selectively formed in contact with one side of the upper gate electrode 3.

Thereafter, using the upper gate electrode 3 and the resist film as masks, boron is implanted into the polycrystalline silicon layer 2 by ion implantation to form source/drain regions 4.5. The acceleration energy and implantation amount of boron at this time are determined by the thickness of the polycrystalline silicon layer 2, the mass of the impurity to be implanted, the heat treatment conditions, etc., as in the case of manufacturing the source/drain region of a normal P-type MO8FET. do. Note that at this time, the upper gate electrode 3 serves as a mask, and the lower gate electrode 1
is inevitably provided with an offset with respect to the source/drain region 4.

In this way, the polycrystalline silicon transistor according to this example can be manufactured.

Next, changes in transistor characteristics when misalignment occurs during manufacturing will be described.

First, in FIG. 1, a case will be described in which source/drain region 4 is a source region and source/drain region 5 is a drain region.

When misalignment occurs and the offset amount SI becomes large, the off-state current of the polycrystalline silicon transistor becomes even smaller. At this time, when the lower gate electrode 1 and the upper gate electrode 3 are in a predetermined positional relationship and misalignment occurs only on the drain region S side, the on-current of the transistor decreases slightly compared to when there is no misalignment. However, since two gate electrodes are provided, it is possible to obtain a larger on-current than the conventional one. In this case, since the offset of the gate electrode 1 with respect to the source region 4 is substantially formed by a self-alignment line, no misalignment occurs in the source region 4.

Furthermore, if the lower gate electrode 1 is formed at a predetermined position and the upper gate electrode 3 is misaligned, thereby increasing the offset amount S2, the drain region 5 will have an overlapping structure with respect to the lower gate electrode 1. . At this time, although the on-current due to the lower gate electrode 1 is slightly reduced due to the source resistance, a larger on-current can still be obtained than in the conventional case. On the other hand, since the upper gate electrode 3 is an offset gate electrode with respect to the drain region, the off-state current is reduced.

Furthermore, when misalignment occurs in the direction in which the offset amount S1 decreases, if the lower gate electrode 1 and the upper gate electrode 3 are in a predetermined positional relationship, the two gates disposed above and below the polycrystalline silicon layer 2 The on-state current increases due to the electrodes 1 and 3. At this time, although the effect of reducing the off-state current is reduced, since the lower gate electrode 1 serves as an offset gate electrode with respect to the source region 4, the off-state current is reduced compared to the conventional case.

Furthermore, when the offset amount S2 decreases due to misalignment of the upper gate electrode 3, the offset amount S2 of the lower gate electrode 1 with respect to the source region 4 decreases, so that the on-current increases. At this time, although the off-state current increases because the offset S1 of the upper gate electrode 3 with respect to the drain region 5 decreases, the off-state current is still smaller than in the conventional case.

In this way, in both cases, not only are the on-current and off-current characteristics better than in the past, but one of the on-current and off-current characteristics is further improved.

Next, a case where the source/drain region 4 is a drain and the source/drain region 5 is a source will be described.

In this case as well, the offset amount S2 of the lower gate electrode 1 with respect to the drain region 4 is determined by the self-alignment of the upper gate electrode 3. When the upper gate electrode 3 and the lower gate electrode 1 have a predetermined positional relationship, the lower gate electrode 1
The offset amount S2 with respect to the drain region 4 is always constant. Therefore, the off-state current does not become larger than in the conventional case.

The upper gate electrode 3 is moved in the direction in which the offset amount S2 increases.
If the lower gate electrode 1 is displaced, the off-state current is reduced by the lower gate electrode 1. At this time, although the on-current is reduced compared to the case where there is no misalignment, the presence of the upper gate electrode 3 makes it possible to obtain a larger on-current than in the past.

Similarly, if the upper gate electrode 3 is displaced in the direction in which the offset amount S2 becomes smaller, although the off-current increases due to the lower gate electrode 1, the upper gate electrode 3
Since the electrode is an offset gate electrode with respect to the source region 5, the off-state current is smaller than in the conventional case.

As described above, the polycrystalline silicon transistor according to this embodiment has better on-current and off-current characteristics than conventional polycrystalline silicon transistors even if misalignment occurs in any direction during manufacturing. .

FIG. 2 is a plan view showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 3 is a sectional view taken along the line ■--■ in FIG.

This semiconductor memory device uses the polycrystalline silicon transistor shown in FIG. 1 as a load element of a static memory cell.

An N+ diffusion layer 11 consisting of a source region 24 and a drain region 25 of a drive transistor is selectively formed on the surface of a silicon substrate (P well layer) 23. Further, on the silicon substrate 23, an SiO2 film 2 is provided as a gate oxide film.
A gate electrode 12 is selectively formed through the gate electrode 1 .

This gate electrode 12 is the gate electrode of the drive transistor and is also the lower gate electrode of the polycrystalline silicon transistor. This drive transistor also includes an N- region 27 connected to the source region 24 and drain region 25.
is provided, so this drive transistor is L
D D (Lightly Doped Draln)
) structure.

A SiO2 film 2 is formed on the SiO2 film 21 and the gate electrode 12.
It has a two-film type 2, and a crystalline silicon layer 13 is selectively formed on the SiO2 film 22. In this polycrystalline silicon layer 13, source/drain regions 13a and 13b of a polycrystalline silicon transistor are selectively formed.

Note that the gate electrode 12 is connected to the source and
An offset is provided with respect to drain region 13b.

SiO2 is formed on the SiO film 22 and the polycrystalline silicon layer 13.
A film 26 has a film shape 6, and a gate electrode 14 is selectively formed on this SiO2 film 22 as an upper gate electrode of a crystalline silicon transistor. As shown in FIG. 3, this gate electrode 14 is connected to the source φ drain region 13a.

An offset is provided.

Further, an aluminum wiring 19 is formed in a predetermined shape on the SiO2 film 26 film type six-tooth electrode 14 via an insulating film (not shown).

A contact section 16 is selectively provided between the polycrystalline silicon layer 13 and the N'' diffusion layer 11, and the N+'' diffusion layer 11 and the gate electrode 1 are connected via this contact section 16.
2 and polycrystalline silicon layer 13 are selectively connected. Further, a contact portion 17 is selectively formed between the polycrystalline silicon layer 14 and the gate electrode 13, and the polycrystalline silicon layer 13 and the gate electrode 14 are selectively connected via this contact portion 17. has been done. Further, a contact portion 8 is selectively formed between the aluminum wiring layer 17 and the N+ diffusion layer 11, and the aluminum wiring 17 and the N+ diffusion layer 11 are selectively connected via this contact portion 18. has been done.

A semiconductor memory device equipped with a polycrystalline silicon transistor according to this embodiment is configured as described above, and the polycrystalline silicon transistor described in the first embodiment is provided as a load element of a static memory cell. . As a result, even in a large-capacity static memory cell, the standby current is significantly lower than in the past. In addition, variations in characteristics due to misalignment during manufacturing are suppressed, and stable characteristics can be obtained.

Next, a method for manufacturing the semiconductor memory device according to this embodiment will be explained.

First, an N-type MO8FE is manufactured in the same manner as in the manufacturing method of a semiconductor memory device having an N-type MO8FET with a normal LDD structure.
A 5i02 film 21 as a T gate oxide film, a gate electrode 12, an N- region 27, side walls and source/drain regions 24 and 25 are formed. And SiO2 film 2
A SiO2 film 22 is formed on the gate electrode 1 and the gate electrode 12.

Next, this SiO2 film 22 is etched back to remove the 5iO9 film 22 on the gate electrode 12.

Thereafter, the SiO3 film 22 is again formed to a predetermined thickness using the CVD method. This SiO2 film 22 covers the gate electrode 1
This is the gate oxide film for No. 2. Thereafter, a contact portion 16 reaching the N+ diffusion layer 11 from the SiO2 film 22 is formed at a predetermined position.

Next, a polycrystalline silicon layer is formed over the entire surface to a predetermined thickness. Then, ion implantation is used to introduce phosphorus or the like into this polycrystalline silicon layer to make this polycrystalline silicon layer N-type. Then, using photolithography technology,
This polycrystalline silicon layer is patterned into a predetermined shape to form a polycrystalline silicon layer 13.

Next, using the CVD method, S is formed as a gate oxide film over the entire surface.
i 02 wX26 is deposited to a predetermined thickness.

Then, the contact portion 1 is selectively attached to this SiO2 film 26.
form 7. Thereafter, a gate electrode 14 is selectively formed on this 5in2 film 28.

Next, using an ion implantation method, a polycrystalline silicon layer 1 is formed.
For example, boron is selectively implanted into the polycrystalline silicon layer 13 to form source/drain regions 13a and 13b of polycrystalline silicon transistors. Thereafter, an insulating film, aluminum wiring, etc. are formed in the same manner as in the conventional method, and the above-described semiconductor memory device is completed.

[Effects of the Invention] As explained above, according to the present invention, gate electrodes are provided respectively above and below the polycrystalline silicon layer in which the source region and the drain region are formed, and one of the gate electrodes is Since an offset is provided with respect to the source region and the other is provided with an offset relative to the drain region, the polycrystalline silicon transistor according to the present invention has a higher on-current than a conventional polycrystalline silicon transistor. Large size and low off-state current. Further, there is little change in on-current and off-current characteristics due to misalignment during manufacturing, and stable transistor characteristics can be obtained.

On the other hand, the semiconductor memory device according to the present invention has the above-mentioned polycrystalline 7
Since a recon transistor is used as a load element for a static memory cell, standby current is small even if the capacity is large. It also has the effect of suppressing variations in characteristics caused during manufacturing.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a polycrystalline silicon transistor according to an embodiment of the present invention, FIG. 2 is a plan view showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 4 is a sectional view showing an example of a conventional polycrystalline silicon transistor, and FIG. 5 is a sectional view showing another conventional polycrystalline silicon transistor. 1.3, 12.14, 33; Gate electrode, 2°13.3
2; Polycrystalline silicon layer, 4, 5.13a. 13b, 24, 25.34.35.44, 45; Source/drain region, 8.9, 21.22.26 v 39
:S 102 film, 16.17.18; contact part,
19; Aluminum wiring, 23; Silicon substrate, 27;
N-region

Claims (2)

[Claims] (1) A polycrystalline silicon layer provided with a source region and a drain region, and a polycrystalline silicon layer arranged below this polycrystalline silicon layer with an insulating film interposed therebetween and offset with respect to one of the source region and the drain region. and an upper gate electrode arranged above the polycrystalline silicon layer with an insulating film interposed therebetween and offset from the other of the source region and the drain region. A polycrystalline silicon transistor comprising: (2) A polycrystalline silicon layer provided with a source region and a drain region, and a polycrystalline silicon layer arranged below the polycrystalline silicon layer with an insulating film interposed therebetween and offset with respect to one of the source region and the drain region. and an upper gate electrode arranged above the polycrystalline silicon layer with an insulating film interposed therebetween and offset from the other of the source region and the drain region. 1. A semiconductor memory device comprising a polycrystalline silicon transistor configured as a load element of a static memory cell.