JPH04195991A - Display device and information processor using the same - Google Patents

Abstract

PURPOSE:To attain reduction in data-hold current, lower cost and to improve operation convenience by reducing the number of refresh cycle per a time unit through a refresh control circuit in the period of power source interruption less than the actions in the period other than the power source interruptions in a display control circuit. CONSTITUTION:This display device consists of a central processing unit (CPU) 1, main memory 2, display control circuit (VIC) 3 with a built-in refresh control circuit, picture memory (VRAM) 4, and liquid crystal display (LCD) 5. And, the display device 5 is provided with the refresh control circuit 9 which selects refresh cycle for a time unit shorter than a prescribed cycle per second in its display circuit. Consequently, the number of times of refresh start/stop at the memory 4 and at an interface part with the memory 4 is reduced. Thus, a display data is held in a low electric consumption, and the display device having a resume function with the low cost and simple construction is obtained.

Description

[Detailed Description of the Invention] Industrial Application Field This invention has a so-called resume function that stores the working state when the power is turned off using a battery, and allows the previous working state to be continued when the power is turned on again. The present invention relates to operations used in word processors, personal computers, etc., and information processing apparatuses using the same.

Conventional technology In recent years, information equipment has become more sophisticated, and if for some reason the power is cut off quickly during information processing and the information processing is resumed, the display screen remains in the same state and cannot be reproduced. Increasingly, there are many devices that have a so-called resume function.

Similar requests regarding image display are increasing.

In this display circuit, a dual-port image memory is used in the frame buffer for storing display data, which can independently perform serial output to the display device and parallel writing from the central processing unit. It is known to improve memory access efficiency. For a typical image memory, for example, 199
0th Edition Toshiba Semiconductor Data Book M OS Memory (RAM
, Module), pages 642 to 674.

Problems to be Solved by the Invention In the above-mentioned conventional technology, when configuring a display circuit using an image memory having internal dynamic memory cells, it is possible to maintain display data, which is necessary for the resume function, with low power consumption. No thought has been given to making it a reality,
Since the external refresh control circuit needs to be kept running at all times to back up display data, the display power is mostly consumed.

Furthermore, the image memory used itself does not take into consideration battery backup of data. For example, the minimum data retention current in the dual port memory TC524256P-10, i.e. the maximum refresh interval (refresh time is 8m5ec, refresh cycle 51
2 cycles, 6 refresh cycles per unit time
There is no regulation regarding the refresh current value at 4000 cycles/sec). In addition, the standby current is up to 10mA
It is.

Therefore, in a battery-powered system using such an image memory, the power consumption during so-called resume is high, and the time for the resume function to operate normally is short, or the battery capacity needs to be large, which increases the weight and cost of the set. The problem arises.

Further, if a static memory is used as the memory, it is possible to reduce the power consumption required for data backup, but there is a problem in that the cost of the memory becomes extremely large.

It is also possible to transfer and save the data in the image memory to another memory that is backed up with low power consumption, but there are problems in that the processing for transfer is complex and the time required to restore the image is long. be.

The present invention solves the above problems by realizing an inexpensive and easy-to-use display device and image memory with reduced data retention current, and by using the same, a low-cost and simple configuration suitable for battery operation. The purpose of the present invention is to provide an information processing device having a resume function.

Means for Solving the Problems The present invention achieves the above-mentioned objects, and it is a display circuit that generally uses a refresh cycle per unit time when retaining image data at a so-called resume time for an image memory having dynamic memory cells. 04
This display device is provided with a refresh control circuit that performs refresh with a refresh time and refresh cycle having a value smaller than 000 cycles 2 seconds.

Alternatively, a display device is configured using an image memory having a dynamic memory cell with a built-in cell refresh circuit.

Furthermore, using the above display device, when the power switch is turned off, the display device is backed up by the battery, and when the power switch is turned on again, a resume function is provided that restores the display screen that was displayed when the power switch was turned off. This is an information processing device that realizes this.

Operation The display device of the present invention having the above configuration has a refresh cycle per unit time of less than 64,000 cycles/second (by providing the display circuit with a refresh control circuit that selects refresh cycles, refresh activation can be performed at the memory itself and at the interface with the memory). 'It works to reduce current consumption by reducing the number of stops and the refresh power supply.

Furthermore, by providing a self-refresh circuit inside the image memory, the refresh cycle can be further extended and set to a time that suits the actual data retention characteristics of the device, and the data retention current can be further reduced. Furthermore, since there is no need to generate a refresh timing in an external circuit during refresh, the display device is simplified and power consumption in the external circuit and peripheral circuits inside the memory is reduced.

By using a display device that consumes less power when holding data, display data can be stored for a long time using a battery, and by using this display device in an information processing device, a resume function can be easily realized.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
In order to realize the resume function, we will mainly explain the refresh control function and image memory self-refresh circuit that are necessary.

FIG. 1 shows a schematic block diagram of a part of an information processing device mainly including a display device according to an embodiment of the present invention. As a component, the central processing unit (hereinafter referred to as rcP)
UJ) 1, a display control circuit (hereinafter referred to as rVIcJ) that includes a main memory 2 and a refresh control circuit.
3 and image memory (hereinafter referred to as 'V RAM J) 4
and a liquid crystal display device (hereinafter referred to as rLCDJ). The V RAM 4 is composed of a dual port memory, and although detailed explanation will be omitted since it deviates from the gist of the present invention, output to the LCD 5, that is, reading from the VRAM 4 and writing from the CPUI side through the VIC 3 is possible. This can be done independently, and the VIC3 has a circuit that outputs display addresses to the VRAM4, a circuit that writes straight lines and patterns to VRA14 according to instructions from the CPUI, and the like.

FIG. 2 shows the refresh control section in the VRAM 4 and VIC 3, and the timing chart in FIG. 3 shows the sequence for putting the VRAM 4 into self-refresh mode at the time of resume and the sequence for leaving the self-refresh mode. In VIC3, the resume state can be accessed from the outside,
In other words, the R8D~1 signal 6 indicating that display data needs to be saved is applied, and is set to a high level at the time of resume. For refresh during normal operation, CAS before RAS refresh is inserted at regular intervals as shown in FIG. RTIM R8DM signal 6
Internal signal R of refresh control circuit 9 highlighted by signal 8
The self-refresh mode is set when the FL signal 10 is at a high level.

RASII is a row address strobe, and CAS12 is a column address strobe. In this example, RAS
If CAS12 is brought down while II is at high level, and then RAS 11 is brought down, self-refresh is performed. In self-refresh mode, refresh address AO to A8 and RASl for each refresh timing
Since the settings of CAS12 and other control terminals can be fixed at a level at which no through current flows, the operation of the refresh control circuit 9 can be minimized.

When the resume is completed, that is, the R3DM signal 6 becomes low level, the RTIM signal 8 is set to high level, and the RFL
The self-refresh mode is ended by setting the signal IO to a low level. Thereafter, CAS12 and RASII are turned on to perform precharging for a certain period of time while R and TIM signals 8 are at high level, and then the normal operation mode is returned to.

Next, FIG. 4 shows a schematic block diagram of the inside of the VRAM 4 in which a refresh control circuit that performs the above operation is incorporated. The VRAM 4 includes a dynamic memory cell block (hereinafter referred to as rRAMJ) 13, a static memory cell block (hereinafter referred to as rSAMJ) 14, and R
Transfer gate 15 from AM13 to SAM14, S A
It is composed of a selection circuit 5EL16 with M14 output. In addition, the signal L TE A O-A 8 is VRAM4 address power 17, DT/'OE is data transfer/' output enable 18, WB, 'WE is write pervi/so/' write enable 19, Wl, /01 ~W4/104 is write mask/data input/output 20.SC is serial clock 2
1.5E is serial enable 22.5101~5I0
4 is a serial data input/output 23.

Since RA'V113 is implemented using dynamic memory cells, refresh is required for data retention, but as mentioned above, VRAM4 has a built-in self-refresh function, which reduces data retention power. Various measures can be taken to achieve this goal.

The self-refresh circuit 24 is composed of a refresh address counter 25 that automatically generates refresh addresses and a refresh timer 26 that automatically generates refresh timing.The refresh timer 26 internally generates a clock at regular intervals and synchronizes with the clock. The value of the refresh address counter 25 is updated and given to the memory cell as a row address, thereby performing refresh. Since the same refresh address counter 25 is used for the CAS-before-RAS refresh during normal operation and the self-refresh during resume, no mismatch occurs in refresh.

If you extend the refresh time with a constant refresh cycle, the refresh current per unit time will decrease, and if you increase the number of memory cells that are simultaneously refreshed with a constant refresh time and reduce the refresh cycle, the current consumed by peripheral circuits in the memory will decrease. can be reduced. In other words, in the conventional dual port memory, the number of refresh cycles per unit time is 64,000 cycles/second, but by selecting a smaller number of refresh cycles per unit time, the data retention current can be reduced.

Furthermore, VRAM4 is a reference voltage generation circuit A (hereinafter referred to as rVR).
EF (A) J) 27 and group! 1! Voltage voltage circuit B
(hereinafter referred to as "VREF(B)J") 28 generates a negative substrate potential, reduces the junction capacitance component, and enables high-speed operation, but during standby and self-refresh, most of the peripheral circuits in V RAM 4 Since it does not operate, only VREF (B) 28, which consumes less power, is selected and operated.

In the embodiment, when the power switch is turned off by a battery backup circuit (not shown), when the display device and image memory according to the above embodiments are used, the data retention power is reduced, so it is only necessary to back up the data, and there is no need to use static memory as the image memory. Display devices with a simple configuration consisting of an image memory with large-capacity, low-cost dynamic memory cells and a display device with a resume function do not require complicated configurations to transfer and save data to other low-power-backed memories. An information processing device using this can be realized.

The effects obtained by the embodiment in which the above refresh control circuit is incorporated are summarized as follows.

That is, (1) in the dual port memory, since the self-refresh circuit is built-in, the operation of the external circuit can be minimized compared to when refresh control is performed externally, and the power consumption of the entire display circuit can be reduced.

(2) In a dual port memory, since a self-refresh circuit is built in, most of the peripheral circuits of the memory are also placed in a standby state, and the standby current/data retention current can be reduced, compared to when refresh control is performed externally.

(3) Refresh cycle time per unit time is 64
Since it can be set to less than 000 cycles/sec, the data retention current can be reduced.

(4) Dual-port memory is equipped with multiple internal reference voltage generation circuits, and data retention current can be reduced by selecting and operating only the reference voltage generation circuit with low power consumption during standby and self-refresh. .

(5') At the same time as using a dual port memory in the display circuit, the power required for data retention in the dual port memory and display circuit is reduced by the methods described in (1) to (4) above, and the power switch is turned off. By sometimes providing battery backup, an information processing device having a resume function can be realized at low cost and easily.

Although the present invention has been specifically explained based on the embodiments above, the present invention is not limited to the case where a refresh circuit is built-in as in the above-mentioned embodiments, and various changes can be made without departing from the spirit thereof. Needless to say.

For example, it goes without saying that unnecessary DC buses are disconnected during standby and refresh to reduce data retention power, and dual-port memory, which only has the normal refresh mode CAS-before-RAS refresh function, has a soft error rate and After measuring the data retention current value, standby current value, etc., select one that can reduce the number of refresh cycles per unit time, and then provide a refresh timer on the display circuit side that reduces the number of refresh cycles per unit time. .

In addition, when data is retained, the data retention voltage may be set low so that it can be backed up by a single cell battery. It is also possible to create a configuration that can further save power by supplying power only to the circuit.

In addition, by ignoring the lower bits of the built-in address counter only during self-refresh and CAS Hi-FOR RAS refresh, and increasing the number of memory mats that can be refreshed at the same time, the number of refresh cycles per unit time is reduced, and peripherals that become active in each cycle are Data retention power may be reduced by reducing the number of times the circuit unit operates. In this case, during normal operation, the number of memory mats that can be refreshed at the same time does not increase, so only the data retention current can be reduced without increasing power consumption during operation.

Furthermore, the refresh cycle during self-refresh may be set to the maximum refresh cycle suitable for the capability of the device by trimming the number of bits of the refresh address counter during manufacturing.

Also, ICAS/
Even in 2WE dynamic random access memory, no consideration has been given to achieving display data retention required for the resume function with low power consumption, and sufficient specifications are not available for reducing data retention current and standby current. Therefore, a display circuit using this may also have a reduced number of refresh cycles per unit time or may have a built-in self-refresh circuit, as in the case of using the above-mentioned dual port memory.

Furthermore, it goes without saying that the circuit, timing, and terminals for realizing refresh can be changed in various ways depending on differences in internal circuits and devices.

The present invention can be widely used in display circuits and display memories of information processing circuits such as word processors and personal computers that can be operated by battery.

Effects of the Invention As is clear from the above description, the following effects can be obtained by applying the display device of the present invention to an information processing device.

In other words, compared to image memory with a conventional dynamic memory cell structure that does not consider reducing data retention power, displays that reduce the number of refresh cycles per unit time or have a self-refresh circuit built into the memory By configuring the device and image memory, display data can be held with low power consumption.

This also makes it possible to implement a resume function that returns the display screen when the power switch is turned off by simply retaining the display screen in the Hayabusa with a backup power supply, and returns it when the power switch is turned on again, eliminating the need to use static memory as image memory. To provide a display device having a resume function that is inexpensive and has a simple configuration, and an information processing device using the same, which eliminates the need to transfer and hold data to another memory backed up with low power consumption. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a part of an information processing device mainly including a display device according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram of a refresh control section of a display control circuit and a video memory of the same embodiment. 3 are timing charts showing refresh mode setting/cancellation in the same embodiment, and FIG. 4 is a schematic block diagram of the image memory in the same embodiment. I: central processing unit, 2: main memory, 3: display control circuit, 4: image memory, 5: liquid crystal Display device, 7...
- Timing generation circuit, 9... Refresh control circuit. Agent's name: Patent attorney Akira Okaji, and 2 others/--v Kwahama Taikiku'' 1 2.-Main memory 3-@ H5 Tomo 1 Maki Ul Tsubaki 4 Image memo ts 2 Figure SDr-I

Claims (4)

[Claims] (1) Dynamic memory that stores image data,
The display control circuit includes a refresh control circuit for refreshing the memory, and a display control circuit having a resume function for retaining image data accumulated in the memory during a power-off period, and the display control circuit A display device that reduces the number of refresh cycles per unit time by the refresh control circuit during a power cutoff period compared to operations other than the power cutoff period. (2) The display device according to claim 1, wherein the refresh control circuit refreshes the memory by increasing the number of memory cells that can be refreshed simultaneously during a power-off period. (3) The memory has a self-refresh circuit, and the self-refresh circuit performs refresh operations during a power-off period by reducing the number of refresh cycles per unit time compared to operations other than the power-off period. The display device according to claim 1. (4) The display device according to any one of claims 1, 2, and 3, wherein the display control circuit operates at the same number of refresh cycles per unit time as the operation during the power cutoff period during a period other than the power cutoff period. (5) The display device according to any one of claims 1, 2, 3, and 4 is provided, and when the power is turned on again, the display screen that was displayed on the display device immediately before the power was turned off is
An information processing device comprising a resume means for displaying on the display device.