JPH0628053A - Electronic apparatus having stand-by mode - Google Patents

Abstract

PURPOSE:To considerably suppress power consumption to a low level at the time of a standby mode by switching clocks to be used for an operation mode and the stand-by mode. CONSTITUTION:In the stand-by mode, a VA power supply is disconnected and only VL power is supplied from a power supply control part 7. During the period, the operation of a clock generator 1 and an MPU 5 receiving VA power supply is stopped. Operation required in the stand-by mode is only refreshment operation to a DRAM 6. Since highly accurate timing is not required for the refreshment operation, the accuracy of a VCO oscillator 2 is sufficient for clocks and a clock selecting circuit 3 selects CLKVCO and outputs the selected CLKVCO to a memory controller 4. The controller 4 drives a timer and executes refreshment operation, so that power consumption in the stand-by mode can be suppressed to a low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for battery operation, which has a function called a resume function. The resume function is a function of retaining the internal state of the device at the time when the power is turned off and immediately restoring it when the power is turned on next time. As a result, the previous work can be immediately continued at the same time when the power is turned on.

The resume function is realized by having an operation mode in a normal operation state and a standby mode in which a content of a memory and a part of hardware is backed up. Normally, in the standby mode, the device operates on a battery power source, so how to reduce the power consumption of the battery is an important issue.

[0003]

2. Description of the Related Art Conventionally, in order to suppress the operating power in the standby mode, a memory that needs to be backed up in the standby mode has been composed of static elements that do not require active signal changes. For example, the memory S
If the RAM (static RAM) is used, the memory contents can be retained only by supplying a backup current.

However, SRAM is generally expensive,
In many cases, MPUs, I / O controllers, etc. are dynamic elements rather than static elements. By the way, DRAM (Dynamic RA)
The use of M) requires periodic memory access called refresh. Usually, the refresh is performed by the memory controller.

FIG. 2 is a diagram for explaining refresh. In FIG. 2, the memory controller 11 has a counter or a timer inside, and outputs a refresh request signal (REFREQ) to the internal refresh controller at a predetermined time interval.

The refresh control section confirms that the memory read / write control section is not accessing the memory 12, and performs the memory refresh by the CAS signal and the RAS signal. The above explanation is for CAS Before R
The AS refresh method has been taken as an example, but of course there is another method.

However, whichever refresh method is used, the counter / timer for generating the refresh request is operated, or the refresh control unit is set to CAS / RA.
In order to output the S signal, a clock (CL
K) A signal is required. In FIG. 2, the clock signal is generated by the oscillator 10.

This clock signal is also used for MPU and the like. The clock signal used by the MPU is a few nS (1 ×
It is general that a high accuracy of about 10 ⁻⁹ seconds) is required, and an oscillator for that purpose is composed of a crystal oscillator called a clock generator and a high-speed drive element integrated with each other.

This clock generator has a very high performance, but on the other hand, it consumes a large amount of power and is 30 mA at 5V.
(MAX). On the other hand, the DRAM backed up in the standby mode has been extremely low in power consumption in recent years, and the power consumption is about 300 μA.

[0010]

That is, in the standby mode, most of the electric power of the battery is consumed only by generating the clock signal. Therefore, when the standby mode time becomes long, there is a problem that the battery does not have power and the resume function cannot be used.

In consideration of the above-mentioned problems of the prior art, the present invention uses an inexpensive DRAM as the memory that needs to retain the contents in the standby mode in the device having the resume function, and also in the standby mode. An object of the present invention is to provide a means for reducing the power consumption in the standby mode while using the dynamic element in the hardware that needs to be operated in the mode.

[0012]

According to the invention, the above mentioned objects are achieved by means of the patent claims.

That is, according to the present invention, an operation mode is provided in an apparatus having a standby mode for backing up a memory or the like and an operation mode when the apparatus is used so that the apparatus can be used immediately after the power is turned on. In an electronic device having a standby mode, sometimes a means for supplying a first clock whose strict cycle and pulse width are specified and a means for supplying a second clock with a relatively low accuracy in the standby mode are provided. is there.

[0014]

In the normal operation mode, the present invention uses the high-precision clock generator required by the MPU to generate a high-precision clock signal, and in the standby mode, the power consumption is low but with low power consumption. A VCO oscillator,
An RC oscillator or the like is used to generate a clock signal of relatively low accuracy.

That is, by switching the clock used between the operation mode and the standby mode, the power consumption in the standby mode is significantly reduced. Hereinafter, the operation of the present invention will be described in detail with reference to Examples.

[0016]

FIG. 1 is a diagram showing an embodiment of the present invention.
In FIG. 1, the clock generator 1 is highly accurate but consumes a large amount of power. The power supply is a normal power supply (VA), which is cut off in the standby mode. On the other hand, the VCO oscillator 2 has low accuracy but low power consumption. Since the power source is the constant power source (VL), it is supplied even in the standby mode.

The clock selection circuit 3 selects either one of the clock (CLKOSC) from the clock generator and the clock (CLKVCO) from the VCO oscillator. Then, the selected clock is output to the memory controller 4 and the MPU 5. Normally, CLKOSC is selected in the operation mode, and CLKVCO is selected in the standby mode.

The memory controller 4 reads or writes data from the memory 6 in response to a request from the MPU 5. Further, it has a counter or a timer inside, and refreshes the memory 6 at regular time intervals.

The MPU 5 executes the program while accessing the memory 6. Since the power source is VA, there is no power supply in the standby mode. As described above, when the MPU 5 operates, a highly accurate clock signal with an accuracy of several nS is required.

In the operation mode, the power source control unit 7 outputs V
A and VL power supplies are supplied. In addition, the clock selection circuit 3
Selects the CLKOSC generated by the clock generator 1 and supplies a highly accurate clock to the memory controller 4 and the MPU 5. At this time, the memory controller 4
The reason why the highly accurate clock is supplied to is because the response signal from the memory controller 4 to the MPU 5 also requires highly accurate timing.

On the other hand, in the standby mode, the VA power supply is cut off, and the power supply control section 7 supplies only the VL power supply. During this time, the operations of the clock generator 1 and the MPU 5 which are supplied with the VA power supply are stopped. The operation required in the standby mode is only refreshing the DRAM 6.

In the standby mode, high precision timing is not required for the refresh operation.
As for the clock, the accuracy of the VCO oscillator 2 is sufficient. Therefore, the clock selection circuit 3 selects CLKVCO and outputs it to the memory controller 4. The memory controller 4 operates a timer (counter) by the CLKVCO and performs a refresh operation at regular time intervals.

In the present embodiment, the MPU 5 was mentioned as a typical element that requires a highly accurate clock, but the same applies to the I / O controller and other elements. Further, although the DRAM 6 has been mentioned as a typical element that requires a low-precision clock, it goes without saying that this also includes other elements that may be operated with a low-precision clock.

[0024]

As described above, according to the present invention,
Since the high-precision clock is used in the normal operation mode, it is possible to guarantee the operation of an element such as an MPU that requires the high-precision clock. On the other hand, in the standby mode, since the VCO oscillator or the like which has low accuracy but low power consumption is used, it is possible to suppress the power consumption in the standby mode to be low.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating refresh.

[Explanation of symbols]

 1 Clock Generator 2 VCO Oscillator 3 Clock Selection Circuit 4, 11 Memory Controller 5 MPU 6, 12 Memory 7 Power Supply Control Section 10 Oscillator

Claims (1)

[Claims] 1. A device having a standby mode for backing up a memory or the like so that the device can be used immediately after the power is turned on, and an operation mode when the device is used. An electronic device having a standby mode, which is provided with a means for supplying a first clock whose period and pulse width are defined and a means for supplying a second clock with a relatively low accuracy in the standby mode. .