JP2010061393A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer refreshing a register without increasing a dark current. <P>SOLUTION: The microcomputer includes: an operation mode switch means for switching a CPU operation mode between a normal operation mode in which a CPU operates and a sleep mode in which the CPU does not operate; a main clock generation means for generating a main clock for operating the CPU; a sub-clock generation means which is disposed separately from the main clock generation means to generate a sub-clock; a first storage means for storing CPU state information including a setting state and an operation state of the CPU; a second storage means for storing CPU state information for refresh; a refresh signal generation means for generating a refresh signal at preset timing based on the sub-clock; and a data refresh means for reading the CPU state information stored in the second storage means to write it in the first storage means on the basis of the refresh signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a microcomputer, and more particularly to a register / memory refresh operation when a CPU is stopped.

  A lot of electronic control devices (hereinafter abbreviated as ECU: Electronic Control Unit) have been installed in vehicles in accordance with electronic control of each part. However, power consumption has increased and the burden on the battery has increased. ing. Therefore, by using a microcomputer that can be switched between the normal operation mode and the sleep mode that consumes less power than the normal operation mode, when the ECU is not operating, the microcomputer is set to the sleep mode. Power consumption is suppressed.

  Conventionally, in the sleep mode, to prevent system malfunction due to changes in the memory contents of the registers that hold settings related to CPU operation due to the effects of noise (register data corruption), register refresh is performed periodically. Yes. FIG. 8 shows a timing chart of an embodiment of register refresh according to the prior art. When the register refresh timing Tm arrives, the CPU state is switched from the sleep mode (CPU stopped state) to the normal mode (CPU operating state), and the register refresh Rm is performed. Then, after performing the register refresh Rm, the CPU state is switched from the normal mode to the sleep mode.

  Also in an optical disk reproducing apparatus, a refresh circuit has been devised that reduces power consumption while retaining the contents of a DRAM when processing is suspended in a sleep mode (see Patent Document 1).

JP 2000-260179 A

  In the example of FIG. 8, register data corruption is avoided by performing a register refresh Rm using the main clock during the CPU operation. In order to reduce the dark current (current consumption when the ECU is not operating), it is effective to increase the register refresh timing, that is, the low power consumption operation time Tm. However, since the register refresh interval (i.e., Tm) during the CPU operation becomes long, the probability of adverse effects on the system due to garbled register data increases. For this reason, active low power consumption operation cannot be performed, which contributes to an increase in dark current.

  With the above problem as a background, an object of the present invention is to provide a microcomputer capable of refreshing a register without increasing dark current.

Means for Solving the Problems and Effects of the Invention

  A microcomputer for solving the above-described problem is an operation of switching a CPU that executes a program and an operation mode of the CPU between a normal mode in which the CPU is operating and a sleep mode in which the CPU is stopped. A mode switching unit, a main clock generating unit that operates in a normal mode and generates a main clock for operating the CPU, a sub clock generating unit that is provided separately from the main clock generating unit and generates a sub clock; First storage means for storing CPU state information including the CPU setting state and operation state, second storage means for storing CPU state information for refresh, and timing determined in advance based on the subclock in the sleep mode Refresh signal generating means for generating a refresh signal at the Zui and reads the CPU state information stored in the second storage means, characterized in that it comprises a data refreshing means for writing in the first storage means.

  In the above configuration, the main clock is stopped during the low power consumption operation (sleep mode), but the sub clock continues to operate. By utilizing this, it is possible to realize the refresh of the register (first storage means) during the low power consumption operation. As a result, there is no fear of register data being garbled during the low power consumption operation, and the dark current can be reduced by performing the active low power consumption operation. In the above configuration, refresh is not executed during CPU operation. For this reason, during CPU operation, there is no effect on register rewriting by software, so that the operation of the ECU is not affected.

  The first storage means in the microcomputer of the present invention is configured to include a volatile memory, and the second storage means is configured to include a nonvolatile memory.

  When data is held using a volatile memory, a data holding voltage is always applied, but data corruption cannot be reliably prevented. In addition, the non-volatile memory is less likely to be garbled and is suitable for holding refresh data. With the above configuration, even when a volatile memory is used as a register or the like, the possibility of register data being garbled becomes smaller. In addition, when the RAM is used as the first storage unit, there is less concern about data corruption.

  The refresh signal generating means in the microcomputer of the present invention includes a main clock detecting means for detecting the main clock, and does not generate a refresh signal when the main clock is detected, and generates a refresh signal when the main clock is not detected. Configured to do.

  With the above configuration, refresh is not executed during CPU operation. On the other hand, it is reliably executed in the sleep mode. For this reason, during CPU operation, there is no effect on register rewriting by software, so that the operation of the ECU is not affected.

  The second storage means in the microcomputer of the present invention stores CPU status information for backup in advance, and the data refresh means reads the CPU status information for backup from the second storage means, It is configured to write to one storage means.

  With the above structure, the contents of data can be recovered even when data corruption occurs in a register or the like.

  The second storage means in the microcomputer of the present invention stores the CPU status information stored in the first storage means immediately before the operation mode of the CPU is switched from the normal mode to the sleep mode, and the data refresh means Is configured to read from the second storage means the CPU status information immediately before switching from the normal mode to the sleep mode and write it to the first storage means.

  With the above configuration, even when data corruption occurs in a register or the like, the data contents can be restored, and when the sleep mode is switched to the normal mode, the CPU is switched from the normal mode to the sleep mode. Since it operates from the immediately preceding state, the operation of the ECU can be made smooth.

  The microcomputer of the present invention further comprises CPU state information comparing means for comparing the contents of the CPU state information stored in the first storage means with the contents of the CPU state information stored in the second storage means, and the data The refresh unit is configured to read the CPU state information from the second storage unit and write it to the first storage unit based on the comparison result of the contents of the CPU state information.

  With the above configuration, the refresh target can be selected and limited, so that the refresh time can be shortened. In addition, since writing is not performed in an area that does not require refreshing, data is not garbled during writing.

  Further, the data refresh means in the microcomputer of the present invention is different when the contents of the CPU status information stored in the first storage means and the contents of the CPU status information stored in the second storage means are different. Only the content of the CPU status information that is supposed to be read is read from the second storage means and written to the first storage means.

  With the above configuration, since only the contents different from the contents of the CPU state information are rewritten, the time required for refresh can be shortened. In addition, since writing is not performed in an area that does not require refreshing, data is not garbled during writing.

  In the data refresh means in the microcomputer of the present invention, at least one or more of the contents of the CPU status information stored in the first storage means and the contents of the CPU status information stored in the second storage means are different. When the data is stored in the first storage unit, data resetting information for rewriting the content of the first storage unit to a predetermined content is written when the mode is switched from the sleep mode to the normal mode.

  With the above configuration, when data corruption occurs in the sleep mode, the data is not refreshed, but when the sleep mode is switched to the normal mode, the data is substantially refreshed and the dark current increases. Therefore, the operation of the ECU is not affected.

  Further, the sub clock generation means in the microcomputer of the present invention is configured to include a CR oscillation circuit.

  The CR oscillation circuit is composed of C (capacitor), R (resistance), transistor, operational amplifier or the like, and does not require a crystal oscillator. With the above configuration, it is possible to configure the sub clock generation means at a relatively low cost. Further, since the CR oscillation circuit can be integrated, it can be incorporated in a microcomputer. Furthermore, since current consumption is small compared to an oscillation circuit using a crystal oscillator, it is suitable for operation in a sleep mode.

  The microcomputer of the present invention will be described below with reference to the drawings. The microcomputer of the present invention is used in, for example, an ECU mounted on a vehicle. When the vehicle has a large amount of dark current, battery consumption is accelerated. Therefore, by using the microcomputer of the present invention, dark current can be reduced and battery consumption can be suppressed.

  FIG. 1 shows a microcomputer (hereinafter abbreviated as a microcomputer) 1 and its peripheral configuration. The microcomputer 1 stores, as basic components, a CPU 11 that executes a program, a register 12 that includes a DRAM or SRAM for selecting and setting functions and operation modes of the microcomputer 1, and programs and data. ROM 13, RAM 14 for temporarily storing the calculation result by CPU 11, EEPROM 15 (Electrical Erasable & Programmable Read Only Memory), or a memory 15 constituted by a nonvolatile storage medium such as a flash memory Are connected via the data bus 24.

  The CPU 11 corresponds to the operation mode switching means of the present invention, the register 12 corresponds to the first storage means of the present invention, the ROM 13 corresponds to the second storage means of the present invention, and the RAM 14 corresponds to the first storage means of the present invention. The memory 15 corresponds to the second storage means of the present invention. Further, at least a part of the information stored in the register 12 corresponds to the CPU state information of the present invention, and at least a part of the information stored in the RAM 14 also corresponds to the CPU state information of the present invention.

  The microcomputer 1 includes a main oscillation circuit 16 that generates a main clock signal (for example, several MHz to several tens of MHz) that is an operation clock of the CPU 11 with an oscillation element 23 provided outside the microcomputer 1, and the main clock signal. And a sub oscillation circuit 18 that generates a sub clock signal (for example, several tens of KHz) having a low frequency. The main oscillation circuit 16 corresponds to the main clock generation means of the present invention. The sub oscillation circuit 18 corresponds to the sub clock generation means of the present invention.

  Further, the microcomputer 1 includes a refresh control unit 19 that performs a refresh operation of a register or the like. The refresh control unit 19 is configured by, for example, a PLD (Programmable Logic Device), and performs a refresh operation based on a signal from the refresh signal generation unit 17 generated based on the states of the main clock signal and the sub clock signal. I do. The refresh controller 19 corresponds to the memory data refresh means and CPU status information comparison means of the present invention.

  FIG. 10 shows the configuration of the refresh signal generation unit 17. The refresh signal generator 17 includes a detection circuit 17a that detects a main clock from the main oscillation circuit 16, a switch circuit 17b that connects / disconnects a path between the sub oscillation circuit 18 and the frequency divider circuit 17c, and a sub oscillation circuit 18 A frequency dividing circuit 17c that divides the sub clock is included. The refresh signal generator 17 corresponds to the refresh signal generator of the present invention. The detection circuit 17a corresponds to the main clock detection means of the present invention.

  When the detection circuit 17a detects the main clock, the switch circuit 17b is turned off, the path between the sub oscillation circuit 18 and the frequency dividing circuit 17c is cut off, and no signal is output from the frequency dividing circuit 17c. On the other hand, when the main clock is not detected, the switch circuit 17b is turned on, the path between the sub oscillation circuit 18 and the frequency dividing circuit 17c is connected, and the sub clock is divided from the frequency dividing circuit 17c. Is output.

  Returning to FIG. 1, the CPU 11 executes a specific command to stop the operation mode of the microcomputer 1, at least the normal operation mode in which the CPU 11 and the main oscillation circuit operate, and the operation of the CPU 11 and the main oscillation circuit 16. It is possible to control to switch to the sleep mode, which consumes less power than the operation mode.

  Therefore, the refresh signal generation unit 17 outputs a signal obtained by dividing the sub clock only in the sleep mode.

  The microcomputer 1 includes an input / output unit including a driver 20 for driving an external actuator such as a motor and an LCD, a serial communication unit 21 for serial communication, and a general-purpose input / output port for inputting / outputting signals to / from the outside. 22 etc. may be included.

  The power supply circuit 25 is for supplying power to each part of the microcomputer 1 from an external power supply device such as a battery (connection to each part is omitted).

FIG. 2 shows a configuration example of the sub oscillation circuit 18. The sub oscillation circuit 18 is configured by a known CR oscillation circuit. FIG. 2 shows an example in which the sub oscillation circuit 18 is configured by a Wien bridge type oscillation circuit. In addition, a Salza oscillation circuit or a phase shift oscillation circuit may be used. In the example of FIG. 2, resistors R1 and R2, capacitors C1 and C2, and an operational amplifier OP are basic components of the oscillation circuit. The resistor R3 is for amplitude stabilization, and the resistor R4 is a resistor for amplitude adjustment. The oscillation frequency f of the sub clock signal output from the output terminal SIN OUT is f = 1 / {2π × (C1 × C2 × R1 × R2) ^1/2 }.

  FIG. 3 shows an operation flow of the microcomputer 1 in the data refresh operation. First, it is determined whether or not an instruction for shifting to the sleep mode has been executed. When the sleep mode transition command is executed (S11: Yes), at least the operations of the CPU 11 and the main oscillation circuit 16 are stopped, and the normal mode is shifted to the sleep mode (S13). Step S12 will be described later. During the sleep mode, the main oscillation circuit 16 is stopped, but the sub oscillation circuit 18 is operating. Further, the sub oscillation circuit 18 is preferably stopped in the normal mode from the viewpoint of reducing power consumption.

  During the sleep mode, it is determined whether or not an instruction for shifting to the normal mode has been executed. For example, when data is received by the serial communication unit 20 during the sleep mode or when a predetermined signal is detected by the input / output unit 22, a wake-up signal is sent from the serial communication unit 20 or the input / output unit 22 to the CPU 11. It is done. This wake-up signal corresponds to a normal mode transition command. When the normal mode shift command is executed (S14: Yes), the main oscillation circuit 16 and the CPU 11 are started to shift from the sleep mode to the normal mode (S17).

  On the other hand, when the normal mode transition command is not executed and the sleep mode is continuing (S14: No), it is determined whether or not the refresh timing (corresponding to Rs in FIG. 9) has arrived. Although both the main clock and the sub clock are input to the refresh signal generation unit 17, as described above, when the main oscillation circuit 16 is operating and the main clock is input (that is, in the normal mode). Outputs nothing to the refresh control unit 19. On the other hand, when the main oscillation circuit 16 is stopped and the main clock is not input (that is, in the sleep mode), for example, frequency division processing is performed based on the sub clock and a refresh timing signal is output to the refresh control unit 19. To do.

  When the refresh timing arrives (S15: Yes), for example, a data refresh operation (S16) of the register 12 is executed (described later).

  With reference to FIG. 4, the data refresh operation corresponding to step S16 in FIG. 3 will be described by taking the refresh of the contents stored in the register 12 as an example. This operation is performed in the refresh control unit 19. First, one or a plurality of refresh information stored in advance in the ROM 13 is read (S31).

  FIG. 5 shows an example of refresh information stored in the ROM 13. The refresh information is stored in association with the register address and the data which is the setting content. Returning to FIG. 4, the refresh control unit 19 designates an address included in the refresh information, and writes data associated with the address to the register 12 (S32).

  Then, when the writing of all the data, or a predetermined address range or a predetermined number of data is completed (S33: Yes), this operation is terminated.

  In the example of FIG. 4, the register is refreshed using the refresh information stored in advance in the ROM 13. However, the data immediately before the microcomputer 1 enters the sleep mode is stored, and the stored content is used as the refresh information. May be. The outline of the operation will be described below.

  First, in the operation of the microcomputer 1 in FIG. 3, it is determined whether or not an instruction to shift to the sleep mode is executed, and when the sleep mode shift instruction is executed (S11: Yes), the data in the register 12 is stored in the memory 15. (S12). Thereafter, the operations of the CPU 11 and the main oscillation circuit 16 are stopped and the normal mode is shifted to the sleep mode (S13). The subsequent operation is the same as in FIG.

  In the data refresh operation of FIG. 4, refresh information is read from the memory 15 instead of the ROM 13 in step S31. Other operations are the same as those in FIG.

  In the configuration where the refresh operation is performed using the refresh information stored in the memory 15, the RAM 14 can be refreshed in addition to the register 12. The RAM 14 may be composed of SRAM or DRAM capable of holding data at least in a part of the area. Therefore, data corruption may occur in these areas of the RAM 14 during the sleep mode. The outline of the operation will be described below.

  First, in the operation of the microcomputer 1 in FIG. 3, it is determined whether or not an instruction to shift to the sleep mode is executed, and when the sleep mode shift instruction is executed (S11: Yes), the data in the RAM 14 is stored in the memory 15. Retreat (S12). Thereafter, the operations of the main oscillation circuit 16 and the CPU 11 are stopped, and the normal mode is shifted to the sleep mode (S13). The subsequent operation is the same as in FIG.

  In the data refresh operation of FIG. 4, refresh information is read from the memory 15 instead of the ROM 13 in step S31, and the read data is written to the RAM 14 in step S32. Other operations are the same as those in FIG.

  With reference to FIG. 6, another example of the data refresh operation corresponding to step S <b> 16 in FIG. 3 will be described by taking the refresh of the contents stored in the register 12 as an example. First, for example, one piece of refresh information (ROM data) stored in advance in the ROM 13 is read (S51). Next, the data (register data) of the register 12 corresponding to the address included in the read fresh information is read (S52).

  Then, the contents of the read ROM data and register data are compared (S53). As a result of the comparison, if the two match (S54: Yes), since data corruption has not occurred, the process proceeds to step S56 (described later). On the other hand, when the two do not match (S54: No), it is determined that data corruption has occurred, and the read ROM data is written into the corresponding address area of the register 12 (S55). At this time, a predetermined data (initialization code: data resetting information of the present invention) may be written in a predetermined area of the register 12.

  Then, when the writing of all the data, or a predetermined address range or a predetermined number of data is completed (S56: Yes), this operation is terminated.

  The transition operation to the normal mode of the microcomputer 1 in a configuration in which predetermined data (initialization code) is written in a predetermined area of the register 12 will be described with reference to FIG. This operation is based on the premise that the microcomputer 1 is in the sleep mode.

  First, as in FIG. 3, it is determined whether or not an instruction for shifting to the normal mode has been executed. When the normal mode shift command is executed (S71: Yes), the main oscillation circuit 16 and the CPU 11 are started to shift from the sleep mode to the normal mode (S72). Next, the contents of a predetermined area of the register 12 are read (S73).

Then, it is determined whether or not the read content is an initialization code. When it is an initialization code (S74: Yes), all the contents of the register 12 or the contents of a predetermined range are initialized (S75). Any of the following initialization methods may be used.
Write register initialization data (may be refresh information) stored in advance in the ROM 13 to the register 12.
A register initialization process included in a program stored in the ROM 13 and executed by the CPU 11 is executed, and initialization data included in the register initialization process is written to the register 12.

  In the configuration of FIG. 6 as well, it is possible to store data immediately before the microcomputer 1 shifts to the sleep mode and use the stored contents as refresh information. In this case, in FIG. 3, step S12 is executed to save the register data in the memory 15 and create refresh information. In step S51 of FIG. 6, the refresh information stored in the memory 15 is read out.

  Also in the configuration of FIG. 6, the RAM 14 can be refreshed. In this case, in FIG. 3, step S12 is executed to save the data in the RAM 14 in the memory 15 and create refresh information. In step S51 of FIG. 6, the refresh information stored in the memory 15 is read, and in step S52, data in the RAM 14 is read.

  In the configuration of FIG. 6, when the refresh information stored in the memory 15 and the data in the RAM 14 are compared with each other and the contents are different and data corruption occurs (S54: No), the same as the register 12 Alternatively, an initialization code may be written in a predetermined area of the RAM 14 to perform a RAM initialization process as shown in FIG.

  FIG. 8 shows a timing chart relating to a register refresh operation according to the prior art. FIG. 9 is a timing chart regarding the register refresh operation according to the configuration of the present invention. In the example of FIG. 8, the CPU 11 must be operated every time the register refresh Rm is performed, and the low power consumption operation time Tm does not continue, and the total time of Tm does not increase. Since it is not necessary to operate the CPU 11 to perform the refresh Rs, the low power consumption operation time Ts can be made longer than the Tm in FIG. Of course, the data in the RAM 14 can be refreshed in the same manner.

  In the example of FIGS. 3 to 6 described above, only the register 12 or only the RAM 14 is refreshed, but both the register 12 and the RAM 14 may be refreshed. For example, in FIG. 4, first, the register 12 is refreshed, and then the RAM 14 is refreshed. Of course, the refresh operation of the register 12 and the refresh operation of the RAM 14 may be made separate.

  Further, when the refresh timing (Rs) arrives, the refresh of the register 12 and the refresh of the RAM 14 may be performed alternately.

  Although the embodiments of the present invention have been described above, these are merely examples, and the present invention is not limited to these embodiments, and the knowledge of those skilled in the art can be used without departing from the spirit of the claims. Various modifications based on this are possible.

The figure which shows the structural example of a microcomputer. The figure which shows the structural example of a sub oscillation circuit. The flowchart explaining data refresh operation | movement. FIG. 4 is a flowchart for explaining details of a data refresh operation of FIG. 3. The figure which shows an example of refresh information. The flowchart explaining another example of data refresh operation | movement. The flowchart explaining operation | movement of the microcomputer at the time of register initialization. 9 is a timing chart showing an example of register refresh operation according to the prior art. 6 is a timing chart showing an example of register refresh operation according to the configuration of the present invention. The figure which shows the structural example of a refresh signal production | generation part.

Explanation of symbols

1 Microcomputer (microcomputer)
11 CPU (operation mode switching means)
12 registers (first storage means)
13 ROM (second storage means)
14 RAM (first storage means)
15 Memory (second storage means)
16 Main oscillation circuit (main clock generation means)
17 Refresh signal generator (refresh signal generator, CPU status information comparator)
17a Detection circuit (main clock detection means)
17b switch circuit 17c frequency dividing circuit 18 sub oscillation circuit (sub clock generation means)
19 Refresh control unit (memory data refresh means)
23 Oscillator

Claims (9)

A CPU for executing the program;
An operation mode switching means for switching an operation mode of the CPU between a normal mode in which the CPU is operating and a sleep mode in which the CPU is stopped;
A main clock generating means which operates in the normal mode and generates a main clock for operating the CPU;
A sub-clock generating means that is provided separately from the main clock generating means,
First storage means for storing CPU state information including a setting state and an operation state of the CPU;
Second storage means for storing the CPU status information for refresh;
Refresh signal generating means for generating a refresh signal at a predetermined timing based on the sub-clock in the sleep mode;
Data refresh means for reading out the CPU status information stored in the second storage means based on the refresh signal and writing it to the first storage means;
A microcomputer comprising: The first storage means includes a volatile memory,
The microcomputer according to claim 1, wherein the second storage unit includes a nonvolatile memory. The refresh signal generation means includes main clock detection means for detecting the main clock,
3. The microcomputer according to claim 1, wherein the refresh signal is not generated when the main clock is detected, and the refresh signal is generated when the main clock is not detected. In the second storage means, CPU status information for backup is stored in advance,
4. The microcomputer according to claim 1, wherein the data refresh unit reads out the CPU status information for backup from the second storage unit and writes it to the first storage unit. 5. The second storage means stores the CPU state information stored in the first storage means immediately before the operation mode of the CPU is switched from the normal mode to the sleep mode,
5. The data refresh unit according to claim 1, wherein the data refresh unit reads out the CPU state information immediately before switching from the normal mode to the sleep mode from the second storage unit, and writes the read CPU state information into the first storage unit. 2. The microcomputer according to item 1. CPU status information comparing means for comparing the contents of the CPU status information stored in the first storage means with the contents of the CPU status information stored in the second storage means,
6. The data refresh unit according to claim 1, wherein the data refresh unit reads out the CPU state information from the second storage unit based on a comparison result of the contents of the CPU state information and writes the CPU state information in the first storage unit. The microcomputer according to item.   The data refresh means is different when the contents of the CPU status information stored in the first storage means and the contents of the CPU status information stored in the second storage means are different. 7. The microcomputer according to claim 6, wherein only the contents of the CPU status information are read from the second storage means and written to the first storage means.   The data refresh means, when the content of the CPU status information stored in the first storage means and the content of the CPU status information stored in the second storage means are different from each other, 7. The data reset information for rewriting the contents of all CPU state information stored in the first storage means to predetermined contents when the sleep mode is switched to the normal mode. A microcomputer according to 1.   The microcomputer according to any one of claims 1 to 8, wherein the sub-clock generation means includes a CR oscillation circuit.

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