KR101031417B1 - Micro Processor Unit with non-volatile memory register and control method therefor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor device and a control method having a nonvolatile register. In particular, the present invention relates to data in a microprocessor unit (MPU) that is divided into a memory register area and a control logic area. Disclosed is a technique for providing high-speed operation by providing a nonvolatile memory register that is not erased. To this end, the present invention non-volatilely stores various contents including a command signal, an address, and data for executing a program command in a nonvolatile ferroelectric register, and a separate reset interrupt signal does not occur after a power-on operation. And a control logic area for performing data processing based on various contents stored in the nonvolatile memory register area.

Description

Microprocessor unit with non-volatile memory register and control method therefor}

1 is a block diagram of a conventional microprocessor device having a volatile register.

2 is a flowchart of a system boot operation of a microprocessor device having a conventional volatile register.

3 is a schematic diagram of a microprocessor device having a nonvolatile register in accordance with the present invention;

4 is a system boot operation flow diagram of a method of controlling a microprocessor having a nonvolatile register in accordance with the present invention.

5 is a flowchart of a power-on reset operation of a microprocessor control method having a nonvolatile register according to the present invention;

6 is a detailed circuit diagram of a nonvolatile memory register of a microprocessor device having a nonvolatile register according to the present invention.

7 is an operation timing diagram in a power-on reset mode of a microprocessor device having a nonvolatile register according to the present invention.

8 is an operation timing diagram at reset interrupt of a microprocessor device having a nonvolatile register according to the present invention;                 

9 is an operation timing diagram for updating register contents of a microprocessor device having a nonvolatile register in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor device and a control method having a nonvolatile register, and more particularly, to a microprocessor unit having a nonvolatile memory register that does not erase data even when the power is turned off. It is a technology that enables high speed operation.

1 is a configuration diagram of a microprocessor device having a conventional volatile memory register.

The conventional microprocessor device includes a central processor unit (CPU) to perform data processing, and includes a volatile memory register area 10 for storing temporary data and a control logic area 30 related to data processing.

Herein, the volatile memory register area 10 includes an instruction register (IR) 11, a program counter (PC) 12, a stack pointer (SP) 13, and an index register (Index). Register 14, Address Register 15, Data Register 16, Accumulator 17, Flag Register 18, State Register 19 and other registers. Other registers 20.                         

In addition, the control logic region 30 may include a command decoder 31, an arithmetic logic unit 32, a bus interface unit 33, a clock generator 34, and the like. With control logics 35.

2 is a flowchart of a system booting operation of a microprocessor device having a conventional volatile register.

When the system is in the power-on state (step S1), a reset signal RS is generated (step S2) and the microprocessor is initialized. (Step S3) An operating system boot operation in which the system operation becomes an initialization state. (Step S4).

However, since the conventional microprocessor device includes a volatile memory register region 10 in which data is erased at power-off, a separate system booting process is required when the power-off state is performed at power-off. Accordingly, there is a problem that not only the performance of the microprocessor device is degraded but also the system operation speed is slowed.

The present invention has been made to solve the above problems, and in particular, a high speed operation of a microprocessor unit (MPU) is possible by including a nonvolatile memory register which does not erase data even when the power is turned off. The purpose is to make it.

A microprocessor device having a nonvolatile register of the present invention for achieving the above object stores a variety of contents including a command signal, an address and data for executing a program instruction in a nonvolatile ferroelectric register, and power-on operation. A nonvolatile memory register region which maintains a power-off state when no separate reset interrupt signal is generated later; And a control logic area for performing data processing based on various contents stored in the nonvolatile memory register area.

In addition, the method of controlling a microprocessor having a nonvolatile register according to the present invention includes: a first step of recovering data stored in a nonvolatile memory register area by a reset signal input during a power-on operation of a system; And a second step of entering a power-off state to perform an operating system operation after completion of data recovery.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a microprocessor device having a nonvolatile register according to the present invention.

The present invention includes a central processor unit (CPU) for performing data processing, storing temporary data, and a nonvolatile memory register area 100 in which data is not erased when the power is turned off, and a control logic area related to data processing. 300.

Herein, the nonvolatile memory register area 100 includes an instruction register (IR) 110, a program counter (PC) 120, a stack pointer (SP) 130, and an index register ( Index Register 140, Address Register 150, Data Register 160, Accumulator 170, Flag Register 180, State Register 190 and others. Other registers.

The nonvolatile memory register area 100 includes a contents transition detection unit 210 and an update block 220.

Here, the content transition detection unit 210 detects when data of a specific content is changed in each of the registers 110 to 200 and outputs a content transition detection signal CTD. The update block 220 generates write adjustment signals for restoring the changed data in the nonvolatile registers 110 to 200 when the content transition detection signal CTD is activated.

In addition, the control logic area 300 may include a command decoder 310, an arithmetic logic unit 320, a bus interface unit 330, a clock generator 340, and the like. Control logics 350.

In the present invention having such a configuration, the reset signal RS_PWR is activated and initialized when the power is turned on in the off state. The reset reset signal RS_OS is generated by the reset interrupt signal RS_IN described later to initialize the system.

4 is a flowchart illustrating a system booting operation of a method of controlling a microprocessor having a nonvolatile register according to the present invention.

First, when the system is in a power-on state (step S10), a reset signal RS_PWR is generated (step S11), and the microprocessor retrieves data stored in the nonvolatile memory register area 100 (step S12). )

Thereafter, the operating system booting operation in which the system operation is initialized is skipped and the previous power-off state is entered (step S13). The operation proceeds immediately from the power-off state of the system. (Step S14).

5 is a flowchart illustrating a power-on reset operation of a method of controlling a microprocessor having a nonvolatile register according to the present invention.

First, when the system is in the power-on state (step S20), a reset signal RS_PWR is generated (step S21), so that the program counter 120 is set to the start address of the nonvolatile memory register recovery command. (Step S22) The program counter 120 is set to the first address of an instruction program for restoring data in the nonvolatile memory register area 100.

Thereafter, when the data in the nonvolatile memory register has been recovered (step S23), it is switched to the power-off state so that the previous state can continue. (Step S24)

Subsequently, if the reset interrupt signal RS_IN is generated while the system operation is in progress in the operating system area (step S25), the operating reset signal RS_OS is generated (step S26). Accordingly, the program counter 120 moves to the start address of the operating system. Is set (step S27), the operating system is rebooted from the beginning (step S28).

That is, unless the reset interrupt signal RS_IN is generated, the previous state continues, and only when the reboot operation is required, the reset interrupt signal RS_IN is activated to perform the reboot operation.

6 is a detailed circuit diagram of a nonvolatile memory register region 100 of a microprocessor device having a nonvolatile register according to the present invention. All registers 110 to 200 included in the nonvolatile memory register area 100 have the same configuration, and the command register 110 will be described as an embodiment in the present invention.

The command register 110 includes a pull-up section 111, a P-latch section 112, an input / output section 113, a nonvolatile ferroelectric capacitor section 114, an N-latch section 115, and a pull-down section 116. It is provided.

Here, the pull-up unit 111 includes a PMOS transistor P1 connected between the power supply voltage VCC applying terminal and the P-latch unit 112 to which the pull-up enable signal ENP is applied through the gate terminal. The P-latch section 112 includes PMOS transistors P2 and P3 positioned between the pull-up section 111 and the input / output section 113 and having a gate terminal cross-coupled thereto.

The input / output unit 113 includes NMOS transistors N1 and N2 connected between the data input terminals / D and D and the nodes ND1 and ND2 to which the write enable signal ENW is applied through a common gate terminal.

The nonvolatile ferroelectric capacitor 114 includes ferroelectric capacitors FC1 and FC2 connected between the nodes ND1 and ND2 and the cell plate signal CPL applying terminal. Ferroelectric capacitors FC3 and FC4 are connected between nodes ND1 and ND2 and the ground voltage terminal to control the load across the resistor.

The N-latch portion 115 includes NMOS transistors N3 and N4 which are positioned between the nonvolatile ferroelectric capacitor portion 114 and the pull-down portion 116 and whose gate terminals are cross coupled.

The pull-down unit 116 includes an NMOS transistor N5 connected between the N-latch unit 115 and the ground voltage terminal to which the pull-down enable signal ENN is applied through the gate terminal. The output signals RE_m and / REB_m of the register are output through the nodes ND1 and ND2 at both ends of the register.

FIG. 7 is an operation timing diagram of sensing and reading data stored in the nonvolatile memory register area 100 in the power-on reset mode according to the present invention.

First, when the power supply reaches the stable power supply voltage VCC level when entering the T1 section after power-on, the reset signal RS_PWR is disabled and the power-up detection signal PUP is enabled.

Thereafter, the cell plate signal CPL transitions high according to the enable of the power-up detection signal PUP. At this time, the charge stored in the ferroelectric capacitors FC1 and FC2 of the nonvolatile memory register region 100 causes a voltage difference between the nodes across the cells, that is, ND1 and ND2 by the capacitance load of the ferroelectric capacitors FC3 and FC4.

When entering the T2 section where the voltage difference occurs sufficiently at the node across the cell, the pull-down enable signal ENN is enabled high and is disabled low by the pull-up enable signal ENP to amplify the data across the cell.

Thereafter, when the data amplification of both ends of the cell is completed by entering the T3 section, the power-up check origination PUP and the cell plate signal CPL are transitioned low again. Therefore, the high data of the ferroelectric capacitor FC1 or the ferroelectric capacitor FC2 which have been destroyed is restored. At this time, the write control signal ENW is kept low to prevent external data from being written again.

8 is an operation timing diagram at the reset interrupt of a microprocessor device having a nonvolatile register according to the present invention.

First, when the reset interrupt signal RS_IN is activated, the operating reset signal RS_OS is disabled low after a predetermined time. Accordingly, the program counter 120 is set to the start address of the operating system.

9 is an operation timing diagram for updating register contents of a microprocessor device having a nonvolatile register according to the present invention.

The content transition detection unit 210 detects when the content data of the nonvolatile memory register area 100 is changed and outputs the content transition detection signal CTD to the update block 220. The update block 220 generates update adjustment signals for rewriting data in the nonvolatile memory register when the data change signal is applied from the content transition detection unit 210.

Here, the write enable signal ENW, the cell plate signal CPL, the pull-down enable signal ENN, and the pull-up enable signal ENP shown in FIG. 6 correspond to update adjustment signals.

Each of the registers in the nonvolatile memory register area 100 sets new data according to these update adjustment signals applied from the update block 220.

That is, when the register content is changed, the content transition detection signal CTD is activated. As a result, the write enable signal ENW and the cell plate signal CPL transition high to write new data to the register.

Accordingly, the new data is rewritten by the update block 220 every time the content changes so that the updated data can always be maintained even at the time of power-off.

At this time, the pull-down enable signal ENN remains high and the pull-up enable signal ENP remains low. Therefore, when the content transition detection signal CTD is input high, the inflow of the signal to the register is blocked, so that the program operation can be performed in a state in which the control command is no longer input.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

As described above, the present invention eliminates the need for a separate system booting process when entering the power-on state, thereby enabling the implementation of a microprocessor device capable of high performance and high speed operation.

Claims (12)

Non-volatile ferroelectric registers store various contents including command signals, addresses, and data for executing program instructions, and maintain a power-off state when a separate reset interrupt signal is not generated after a power-on operation. Volatile memory register area; And And a control logic area for performing data processing based on the various contents stored in the nonvolatile memory register area. The method of claim 1, wherein the nonvolatile memory register area 17. A microprocessor device having a non-volatile register comprising one or more of an instruction register, a program counter, a stack pointer, an index register, an address register, a data register, an accumulator, a flag register, and a status register. 3. The microprocessor apparatus of claim 2, wherein the program counter is set to a start address of a recovery command of the nonvolatile ferroelectric register by a reset signal input at power-on. The nonvolatile register of claim 3, wherein the nonvolatile memory register region enters a power-off state after restoring data stored in the nonvolatile ferroelectric register by a reset signal input at power-on. Having a microprocessor device. 3. The microprocessor apparatus of claim 2, wherein the program counter is set to a start address of an operating system region when an operating reset signal is activated when the reset interrupt signal is generated during system operation. 3. The nonvolatile memory register area of claim 1 or 2, wherein A content transition detector for detecting a change in data of a specific content in the nonvolatile ferroelectric register and activating a content transition detection signal; And And an update block for generating write adjustment signals for rewriting the changed data in the nonvolatile ferroelectric register upon activation of the content transition detection signal. 7. The microprocessor device of claim 6, wherein the write adjustment signals are a write enable signal, a cell plate signal, a pull up signal, and a pull down signal. 8. The method of claim 1 or 7, wherein the nonvolatile ferroelectric resistor is A pull-up unit configured to supply a pull-up voltage when the pull-up enable signal is activated; A P-latch unit for latching the pull-up voltage applied from the pull-up unit; An input / output unit configured to selectively input / output data to nodes at both ends of the register according to the state of the write enable signal; A nonvolatile ferroelectric capacitor unit for storing data applied from both nodes of the register according to the control of a cell plate signal; A pull-down unit configured to supply a pull-down voltage when the pull-down enable signal is activated; And And an N-latch portion for latching the pulldown voltage applied from the pulldown portion. The method of claim 1, wherein the control logic area A microprocessor device having a nonvolatile register, characterized in that it comprises at least one of an instruction decoder, an arithmetic logic unit, a bus interface unit, and a clock generator. Recovering data stored in the nonvolatile memory register area by a reset signal input during a power-on operation of the system; And And a second step of performing an operating system operation by entering a power-off state after completion of the recovery of the data. 12. The nonvolatile device as claimed in claim 10, wherein the first step includes setting a program counter to a start address of a command program for restoring data in the nonvolatile memory register area upon activation of the reset signal. Microprocessor control method with registers. The method of claim 10, wherein the second step Generating an operating reset signal upon activation of a reset interrupt signal during operation of the operating system so that a program counter is set to a start address of the operating system; And And rebooting the operating system.

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