JP2006243810A - Microcomputer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer system easily restorable in the event of reset during the updating of a boot program. <P>SOLUTION: The microcomputer system comprises a CPU 10, a flash memory 15, a ROM 14, a reset recording circuit 11 recording reset occurrence in response to reset occurrence during the rewriting of the flash memory 15 and outputting a reset detection signal showing the presence and absence of the recorded reset occurrence, and a switching circuit 13 connected to an output of the reset recording circuit 11 which outputs, in response to the reset detection signal showing the absence of reset occurrence, a signal for selecting the flash memory 15 as the reset-time access destination of the CPU 10, and outputs, in response to the reset detection signal showing the presence of reset occurrence, a signal for selecting the ROM 14 as the reset-time access destination of the CPU 10. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention generally relates to a microcomputer system, and more particularly to a microcomputer system that reads and starts a boot program from a flash memory.

  When power is turned on, a CPU (Central Processing Unit) mounted on the microcomputer system reads and executes a boot program instruction from a reset vector (access destination address at reset). As a storage device for storing the boot program, it is necessary to retain the stored contents even when the power is turned off. For example, a ROM (Read Only Memory) may be used.

  However, when the ROM is used, it is not easy to update the boot program. In order to update the boot program, it is necessary to remove the ROM from the circuit board and write a new boot program using a ROM writer or the like, or replace it with a ROM storing the new boot program. Such a boot program update process takes a lot of time and effort.

  If a nonvolatile memory such as a flash memory is used instead of the ROM as a storage device for storing the boot program, the boot program can be easily updated. The flash memory can be electrically rewritten, and the boot program in the flash memory can be updated by software processing executed by the CPU mounted on the system.

In the invention described in Patent Document 1, the boot program can be written easily and reliably by executing the write program and writing the boot program to the storage area of the flash memory sharing the address with the read-only memory. Can be written to flash memory. Further, in the invention of Patent Document 2, by the multiplexing structure in which programs are stored in the non-volatile memories assigned to the main area and the backup area, even if the system activation using one non-volatile memory is impossible, The system can be activated using a program in a nonvolatile memory.
JP 2003-323313 A JP 2004-013719 A

  In order to update the boot program stored in the flash memory, it is necessary to first execute an erase operation for erasing the contents of the flash memory, and then execute a write operation for writing data. If a reset occurs externally or internally for some reason during these erasing operations or writing operations, the contents of the flash memory are destroyed.

  In this case, if the CPU accesses the flash memory in response to the reset and tries to execute the destroyed boot program, the CPU runs out of control. In this state, the system cannot be started up normally, and there is no means for recovery other than removing the microcomputer LSI from the printed board and rewriting it to the flash memory.

  Since the reset during the boot program update is prohibited due to the specification of the system, the situation in which the boot program is destroyed as described above cannot occur. However, it is impossible to completely eliminate the influence of noise, and a reset operation due to noise may occur during boot program update.

  In view of the above, an object of the present invention is to provide a microcomputer system that can be easily recovered when a reset occurs during boot program update.

The microcomputer system according to the present invention records the reset occurrence in response to the reset occurrence during rewriting of the CPU, the first flash memory, the ROM, and the first flash memory, and the recorded occurrence of the reset A reset recording circuit for outputting a reset detection signal indicating the presence or absence of the CPU, and the first recording as an access destination at the time of resetting the CPU in response to the reset detection signal coupled to the output of the reset recording circuit and indicating the absence of the reset A switching circuit for outputting a signal for selecting a flash memory and outputting a signal for selecting the ROM as an access destination at the time of resetting of the CPU in response to the reset detection signal indicating that the reset has occurred; To do.

  According to at least one embodiment of the present invention, when a reset signal is generated during rewriting of flash memory (during erase processing or write access), the occurrence of the reset signal is detected and the fact is stored in a predetermined nonvolatile memory. Keep it. When the reset signal detection is recorded in the predetermined nonvolatile memory at the time of restart by the reset signal, the position of the reset vector is switched from the flash memory to the predetermined ROM, and the CPU reads the program from the ROM. to start.

  Therefore, for example, if a boot program stored in an external storage device or the like is downloaded and stored in the ROM, the boot program destroyed by the reset operation can be recovered. In this way, it is possible to provide a microcomputer system that can be easily recovered even when a reset occurs during the boot program update.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  In the present invention, in a situation where a reset vector is assigned to the flash memory, if a reset signal is generated during erase processing or write access of the flash memory, the occurrence of the reset signal is detected and this is indicated in a predetermined nonvolatile memory. Store it in. When the reset signal detection is recorded in the predetermined nonvolatile memory at the time of restart by the reset signal, the position of the reset vector is switched from the flash memory to the predetermined ROM, and the CPU reads the program from the ROM. to start. As the program in the ROM, for example, a boot program stored in an external storage device or the like is downloaded and written in the flash memory, thereby restoring the boot program destroyed by the reset operation.

  FIG. 1 is a diagram showing a memory map for explaining the operation of the present invention. The left side of FIG. 1 shows the allocation of memory space during normal operation, and the right side of FIG. 1 shows the allocation of memory space after a reset occurs during the boot program update of the flash memory. As shown on the left side of FIG. 1, for example, address spaces FEFFFF to FF0000 are assigned to a predetermined ROM, and address spaces FE0001 to FFFFFF are assigned to a flash memory. A reset vector is assigned to the address space of the flash memory. Therefore, during normal operation, when restarted by a reset signal, the CPU reads the boot program from the flash memory and executes the system startup operation.

  As shown on the right side of FIG. 1, after a reset occurs during the boot program update of the flash memory, the ROM position and the flash memory position are replaced in the memory space. That is, the reset vector is assigned to the ROM address space. Accordingly, when the boot program is destroyed, when the CPU is restarted by a reset signal, the CPU accesses the ROM and executes the program stored in the ROM. The program writes a boot program in the flash memory, and this makes it possible to recover the system.

  FIG. 2 is a diagram showing an example of the configuration of a microcomputer system according to the present invention. The microcomputer system of FIG. 2 includes a CPU 10, a reset recording circuit 11, a decoder 12, a switching circuit 13, a ROM 14, a flash memory 15, and a macro 16.

  The CPU 10 is connected to a macro such as the ROM 14, the flash memory 15, and the macro 16 via the address bus 20, the data bus 21, and the control bus 22. The CPU 10 designates a macro by an address signal via the address bus 20, exchanges data with the macro via the data bus 21, and controls the operation of the macro by a control signal via the control bus 22. As for the ROM 14 and the flash memory 15, as will be described later, the ROM 14 and the flash memory 15 are designated from the address bus 20 through the decoder 12 and the switching circuit 13 in order to exchange the position in the address space when the boot program is destroyed. It has a configuration.

  The flash memory 15 is a memory for storing a boot program, and a reset vector is assigned to the flash memory 15 during normal operation. Accordingly, when restart is performed by a reset signal during normal operation, the CPU 10 accesses the flash memory 15 and starts a boot program stored in the flash memory 15 to execute a system startup operation.

  The ROM 14 is a memory serving as a system activation source instead of the flash memory 15 when the contents of the flash memory 15 are destroyed due to a reset signal generated during the erase process or write access of the flash memory 15. In the restart by the reset signal when the contents of the flash memory 15 are destroyed, the CPU 10 accesses the ROM 14 as a destination indicated by the reset vector, and executes the program stored in the ROM 14. The program in the ROM 14 restores the boot program destroyed by the reset operation by downloading a boot program stored in, for example, an external storage device and writing the program in the flash memory 15.

  When the reset signal INITX is generated during the erase process or write access of the flash memory 15, the reset recording circuit 11 records that the reset signal has been generated in the internal nonvolatile memory. When the occurrence of the reset signal is recorded in the internal nonvolatile memory, the reset detection signal RDETECT output from the reset recording circuit 11 is asserted. Whether the flash memory 15 is being erased or being accessed for writing can be determined based on the erase signal ERASE from the flash memory 15, the address signal on the address bus 20, and the control signal on the control bus 22.

  The decoder 12 decodes the address signal of the address bus 20 to generate a signal DEC1 indicating that the ROM 14 is an access destination or a signal DEC2 indicating that the flash memory 15 is an access destination. The switching circuit 13 supplies the signal DEC1 to the ROM 14 and supplies the signal DEC2 to the flash memory 15 when the reset detection signal RDETECT is in the negated state. When the reset detection signal RDETECT is in the asserted state, the switching circuit 13 supplies the signal DEC2 to the ROM 14 and supplies the signal DEC1 to the flash memory 15. As a result, the CPU 10 can access the ROM 14 as the destination indicated by the reset vector in the restart by the reset signal when the contents of the flash memory 15 are destroyed.

  The macro 16 is another macro, for example, a RAM or a communication interface. In the example of FIG. 2, the structure which communicates with the external control apparatus 30 as a communication interface is shown. When the contents of the flash memory 15 are destroyed, the CPU 10 can download a boot program from, for example, the external control device 30 by executing a program stored in the ROM 14.

  FIG. 3 is a diagram illustrating an example of the configuration of the reset recording circuit 11. The reset recording circuit 11 in FIG. 3 includes a one-shot multivibrator 41, an inverter 42, an AND circuit 43, an AND circuit 44, an OR circuit 45, an OR circuit 46, a NOR circuit 47, a selector 48, a flash memory 49, and a decoder 50. .

  When a reset signal INITX generated from outside or inside the microcomputer is asserted, in response to this, the one-shot multivibrator 41 generates a pulse signal (negative logic) INITX_DET having a certain length. The output signal INITX_DET of the one-shot multivibrator 41 is supplied to one input of the AND circuit 43 via the inverter 42. An erase signal ERASE is supplied from the flash memory 15 of FIG. 2 to the other input of the AND circuit 43. The erase signal ERASE is a signal asserted by the flash memory 15 while the flash memory 15 is executing an erase operation in response to an erase command from the CPU 10.

  The AND circuit 43 passes the pulse signal that is the output of the one-shot multivibrator 41 when the erase signal ERASE is in the asserted state (HIGH). The output of the AND circuit 43 is supplied to one input of the OR circuit 45 as an abnormality detection pulse indicating that the reset signal INITX has occurred during the erase operation of the flash memory 15.

  The decoder 50 receives the address signal of the address bus 20 of FIG. 2 and the control signal of the control bus 22, and takes the logic of the address signal and the control signal so that the CPU 10 performs write access to the flash memory 15 of FIG. A write access signal WR indicating that the recording is in progress is output. The write access signal WR is supplied to one input of the AND circuit 44. An output signal INITX_DET of the one-shot multivibrator 41 is supplied to the other input of the AND circuit 44 via the inverter 42.

  The AND circuit 44 passes the pulse signal that is the output of the one-shot multivibrator 41 when the write access signal WR is in the asserted state (HIGH). The output of the AND circuit 44 is supplied to one input of the OR circuit 45 as an abnormality detection pulse indicating that the reset signal INITX has occurred during the write operation of the flash memory 15.

  The output of the OR circuit 45 is a HIGH pulse indicating that a reset has occurred during the erase operation or write operation of the flash memory 15. This pulse is supplied to the write enable signal input XWE of the flash memory 49 through the NOR circuit 47 as a LOW pulse.

  The access signal ACCESS output from the decoder 50 is a signal that becomes HIGH when the CPU 10 accesses the flash memory 49 of the reset recording circuit 11, and is LOW in other states. Accordingly, when a LOW pulse is supplied to the write enable signal input XWE of the flash memory 49, the A input of the selector 48 is 0 and the B input is 1. The selector 48 selects the data “0” according to the AB input of “01” and supplies it to the data signal input D_IN of the flash memory 49.

  In this way, when a reset occurs during the erase operation or write operation of the flash memory 15, data “0” is stored in the flash memory 49. The data content “0” stored in the flash memory 49 is supplied to the switching circuit 13 in FIG. 2 as the reset detection signal RDEECT. In this example, the reset detection signal RDETECT is asserted at LOW (“0”).

  In the configuration of FIG. 3, a reset occurs during the erase operation of the flash memory 15 and a reset due to a power interruption during the erase operation, and a reset occurs during a write operation of the flash memory 15 and a reset due to a power interruption during the write operation. Can be detected.

  After the program of the ROM 14 in FIG. 2 is executed and the boot program of the flash memory 15 is recovered, it is necessary to generate a reset again and start up the system by executing the boot program of the flash memory 15. At this time, the flash memory 15 cannot be booted unless the contents of the flash memory 49 of FIG. 3 are rewritten and the reset detection signal RDEECT is not negated. That is, after the boot program of the flash memory 15 is recovered, the CPU 10 needs to access the reset recording circuit 11 and store “1” in the flash memory 49.

  In FIG. 3, the access from the CPU 10 to the reset recording circuit 11 is realized when the access signal ACCESS output from the decoder 50 becomes HIGH by decoding the address signal and the control signal. This HIGH signal is supplied to the write enable signal input XWE of the flash memory 49 through the NOR circuit 47 as a LOW signal. At this time, the AB input of the selector 48 is “10”, and the data signal supplied from the CPU 10 via the data bus 21 is written into the flash memory 49 via the selector 48.

  As a result, “1” can be stored in the flash memory 49 and the reset detection signal RDEECT can be negated. Therefore, in the system of FIG. 2, the destination indicated by the reset vector is the flash memory 15, and the CPU 10 can read the boot program from the flash memory 15.

  The OR circuit 46 generates a signal for resetting other macros by ORing the reset signal INITX and the one-shot multivibrator 41. This signal is supplied to, for example, the macro 16 in FIG.

  FIG. 4 is a signal timing diagram for explaining the operation of the reset recording circuit 11 of FIG. While the flash memory 15 is executing the erase operation, the erase signal ERASE shown in (c) becomes HIGH. When the erase signal ERASE is HIGH and the reset signal INITX shown in (a) is asserted (LOW state), the one-shot multivibrator 41 has a fixed-length negative logic pulse signal in response to the falling edge. INITX_DET is generated (FIG. 4B).

  By taking the AND of the negative logic pulse signal INITX_DET (inversion by the inverter 42 in FIG. 3) and the erase signal ERASE, the abnormality detection pulse shown in (d) is generated. This abnormality detection pulse is inverted and becomes a write enable signal input of the flash memory 49 shown in FIG. At this time, data “0” is input to the data signal input D_IN of the flash memory 49. As a result, the reset detection signal RDETECT (FIGS. 2 and 3) output from the flash memory 49 is set to the asserted state (LOW state).

  FIG. 5 is a flowchart showing the operation of the microcomputer system shown in FIG. First, when the power is turned on or reset, the process starts from step S1. After the power is turned on or after resetting, as shown in step S2, the subsequent processing differs depending on whether or not there is a record in which the reset is detected during the erase operation or write operation of the flash memory 15. become. This is because the read destination of the reset vector indicated by the decoder 12 and the switching circuit 13 is switched according to the reset detection signal RDETECT output from the reset recording circuit 11.

  For example, when there is no record in which reset is detected during the erase operation or write operation of the flash memory 15, the process proceeds to step S3, and the boot program is read from the flash memory 15 that is the reset vector destination and executed. As a result, the microcomputer system is started and normal operation is started.

  FIG. 5 shows a case where an attempt is made to update the boot program of the flash memory 15 thereafter. In the example of FIG. 5, in step S4, a reset signal is generated while the boot program of the flash memory 15 is being updated, that is, during the erase or write operation of the flash memory 15. Yes.

  In response to this, a predetermined value is set in the reset recording circuit 11 in step S5. That is, the data value indicating the occurrence of reset is stored in the flash memory 49 of the reset recording circuit 11. In step S6, when the reset detection signal RDETECT output from the reset recording circuit 11 is asserted, the switching circuit 13 switches the program reading destination at the time of activation from the flash memory 15 to the ROM. Due to the reset generated in step S4, the process is executed again from step S1.

  After the reset, since there is a record in which the reset is detected during the erase operation or the write operation of the flash memory 15 in the branch in step S2, the process proceeds to step S7. In step S7, the program is read from the reset vector destination ROM 14 and executed. By executing this program, in step S8, for example, the boot program is downloaded by the download means, and the downloaded program is written in the flash memory 15. Thereby, the flash memory 15 can be recovered to a normal state.

  Thereafter, in step S9, the flash memory 49 of the reset recording circuit 11 is reset. That is, the reset detection signal RDETECT output from the reset recording circuit 11 is negated by rewriting the data value indicating the occurrence of reset stored in the flash memory 49 with another value. Thereafter, in step S10, a reset is internally generated via software. Thus, after the program in the ROM 14 is executed and the boot program in the flash memory 15 is recovered, the system can be restarted by executing the boot program in the flash memory 15.

  FIG. 6 is a diagram showing an example of a configuration for executing a ROM program and downloading a boot program according to the present invention. The configuration of FIG. 6 includes a microcomputer system 100 according to the present invention, a communication line 101, and a computer 102 such as a personal computer or workstation.

  The microcomputer system 100 is connected to the computer 102 via a communication line 101 such as RS-232. 2, the external control device 30 corresponds to the computer 102, and the macro 16 corresponds to, for example, a UART (Universal Asynchronous Receiver Transmitter).

  The microcomputer system 100 has a configuration in which the system of FIG. In FIG. 6, only the flash memory 15 is shown for convenience. The boot program in the flash memory 15 can be updated by controlling the microcomputer system 100 from the computer 102 via the communication line 101. At this time, if a reset occurs during the boot program update, the contents of the flash memory 15 are destroyed. At startup in response to the reset, the microcomputer system 100 reads and executes the program from the predetermined ROM (ROM 14 in FIG. 2) instead of the flash memory 15 by executing the above-described operation.

  The ROM 14 stores a program for downloading a boot program from the computer 102 via the communication line 101. When this program is executed, the microcomputer system 100 transmits a boot program download request to the computer 102 via the communication line 101. In response to the download request, the computer 102 sends a boot program to the microcomputer system 100 via the communication line 101.

  The CPU 10 of the microcomputer system 100 writes the boot program supplied from the computer 102 in the flash memory 15. Thereafter, based on the program stored in the ROM 14, the CPU 10 generates a reset in terms of software. As a result, the microcomputer system 100 is restarted based on the boot program downloaded and stored in the flash memory 15.

  In the above embodiment, the flash memory has been described as an example. However, other nonvolatile memories such as a ferroelectric memory may be used instead of the flash memory.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a figure which shows the memory map for demonstrating operation | movement of this invention. It is a figure which shows an example of a structure of the microcomputer system by this invention. It is a figure which shows an example of a structure of a reset recording circuit. FIG. 4 is a signal timing diagram for explaining the operation of the reset recording circuit of FIG. 3. It is a flowchart which shows operation | movement of the microcomputer system shown in FIG. It is a figure which shows an example of the structure which executes the program of ROM and downloads a boot program by this invention.

Explanation of symbols

10 CPU
11 Reset recording circuit 12 Decoder 13 Switching circuit 14 ROM
15 Flash memory 16 Macro 20 Address bus 21 Data bus 22 Control bus 41 One-shot multivibrator 42 Inverters 43 and 44 AND circuit 43
45, 46 OR circuit 47 NOR circuit 48 selector 49 flash memory 50 decoder 100 microcomputer system 101 communication line 102 computer

Claims (5)

CPU,
A first non-volatile memory;
ROM,
A reset recording circuit that records the occurrence of the reset in response to the occurrence of a reset during rewriting of the first nonvolatile memory, and outputs a reset detection signal that indicates the presence or absence of the recorded occurrence of the reset;
A signal for selecting the first nonvolatile memory as an access destination at the time of reset of the CPU is output in response to the reset detection signal coupled to the output of the reset recording circuit and indicating that the reset has not occurred, and the reset has occurred And a switching circuit for outputting a signal for selecting the ROM as an access destination at the time of resetting the CPU in response to the reset detection signal.   2. The microcomputer system according to claim 1, wherein the ROM is configured to store a program for causing the CPU to execute an operation of writing a boot program in the first nonvolatile memory.   The CPU further includes a communication circuit that communicates with the outside of the microcomputer system, and the CPU stores the boot program in the first nonvolatile memory from the outside via the communication circuit by executing a program stored in the ROM. 3. The microcomputer system according to claim 2, wherein the microcomputer system is configured to be downloaded.   The reset recording circuit includes a second non-volatile memory that records the occurrence of the reset, and the ROM stores a program that causes the CPU to execute an operation of erasing the record of the occurrence of the reset in the second non-volatile memory. The microcomputer system according to claim 2, wherein the microcomputer system is configured. The reset recording circuit is configured to record the reset occurrence in response to a reset occurrence during an erase operation of the first nonvolatile memory or a write operation of the first nonvolatile memory. The microcomputer system according to claim 1.

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