JP2004096073A - Low-power processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor integrated circuit which is compatible in both high speed and low power consumption. <P>SOLUTION: The semiconductor integrated circuit has a logic circuit 902 and a substrate-bias control circuit 903. After the logic circuit is transferred to a low-power mode in response to the execution of an instruction, the input to the logic circuit is controlled not to be changed, and after the logic circuit is transferred to a high-speed mode in response to an interrupt, the operation starts after the substrate bias voltages applied to the MOSFETs of the logic circuit are stabilized to prescribed levels. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device such as a processor, and more particularly to a microprocessor that achieves high-speed operation and low power consumption by controlling a substrate bias of a processor circuit including MOS transistors according to an operation mode of the processor.
[0002]
[Prior art]
Currently, CMOS integrated circuits are widely used to implement microprocessors. The power consumption of the CMOS circuit includes dynamic power consumption due to charging and discharging during switching and static power consumption due to leakage current. Of these, the dynamic power consumption is proportional to the square of the power supply voltage Vdd and occupies a large power consumption. Therefore, it is effective to lower the power supply voltage to reduce the power consumption. The voltage is dropping.
[0003]
Some current low power consumption type microprocessors include a power management mechanism, provide the processor with a plurality of operation modes, and stop supplying the clock to the execution unit during standby according to the operation modes. By stopping the clock supply, dynamic power consumption due to unnecessary switching in the execution unit can be reduced as much as possible. However, static power consumption due to leakage current cannot be reduced and remains.
[0004]
Since the operating speed of a CMOS circuit decreases as the power supply voltage decreases, it is necessary to lower the threshold voltage of the MOS transistor in conjunction with the lowering of the power supply voltage in order to prevent the operating speed from deteriorating. However, when the threshold voltage is lowered, the leakage current increases extremely. Therefore, as the power supply voltage decreases, the static power consumption has been remarkably increased by the leakage current which was not so large conventionally. Therefore, there is a problem in realizing a microprocessor that achieves both high speed and low power consumption.
[0005]
As a method for solving the problems relating to the operation speed and the leak current of the MOS transistor circuit, a method of controlling the threshold voltage of the MOS transistor by variably setting the substrate bias is disclosed in Japanese Patent Application Laid-Open No. Hei 6-53496.
[0006]
A device structure for variably setting the substrate bias will be described with reference to FIG. FIG. 2 is a cross-sectional view of a circuit having a CMOS structure. An n-well 205 is formed in a part of a surface layer of a p-well (p-type substrate) 201. ⁺ An nMOS transistor composed of a source / drain region 202, a gate oxide film 203, and a gate electrode 204 is formed. ⁺ A pMOS transistor including a source / drain region 206, a gate oxide film 207, and a gate electrode 208 is formed.
[0007]
Usually, the sources of the pMOS transistor and the nMOS transistor are connected to a power supply voltage (hereinafter, referred to as Vdd) and a ground potential (hereinafter, referred to as Vss), respectively, and the drains of the nMOS transistor and the pMOS transistor are connected to an output signal. As terminals for applying a substrate bias, Vbp 209 is provided in the n-well 205 of the pMOS transistor, and Vbn 210 is provided in the p-well 201 of the nMOS transistor.
[0008]
Using a device as shown in FIG. 2, Vbp 209 is normally connected to Vdd, and Vbn 210 is connected to Vss. When the circuit is not operating, these substrate biases are switched to set Vbp 209 to a higher potential and Vbn 210 to a lower potential. The connection can increase the threshold voltage of the MOS transistor and reduce the leakage current.
[Patent Document 1]
JP-A-6-53496
[0009]
[Problems to be solved by the invention]
In order to realize a microprocessor that achieves both high speed and low power consumption, the above-described variable control of the substrate bias is performed on the processor circuit, and the threshold voltage of the MOS transistor is lowered during the operation of the processor. Therefore, it is necessary to maintain the high-speed operation and increase the threshold voltage during standby to reduce the leak current. However, in order to variably control the substrate bias of the processor, it is necessary to accurately control the transition of the operation mode of the processor at the time of switching the substrate bias, particularly the timing of restarting the processor at the time of transition from the standby state to the operation state. Must be prevented from malfunctioning.
[0010]
An object of the present invention is to provide a high-speed and low-power-consumption processor by solving the above problems and realizing the substrate bias control on a processor chip and applying the substrate bias control to various operation modes of the processor.
[0011]
[Means for Solving the Problems]
In order to solve the above problems, the processor of the present invention is characterized by a processor main circuit for executing a program instruction sequence on a processor chip, a substrate bias switching device for switching a substrate bias voltage applied to the substrate, and a processor. The substrate bias switching device is controlled so as to switch the bias to the voltage for the standby mode in response to the execution of the instruction to shift to the standby mode in the main circuit. Another object of the present invention is to provide an operation mode control unit that controls the substrate bias switching device so as to switch to the voltage, and releases the standby of the processor main circuit and resumes the operation after the switched bias voltage is stabilized.
[0012]
Another feature of the processor of the present invention is that the semiconductor device of the processor chip has a triple well structure, and the processor main circuit is formed on a well region different from the substrate bias switching device and the operation mode control unit. Is Rukoto.
[0013]
Another feature of the present invention is that the operation mode control unit serves as a means for waiting for the switched bias voltage to stabilize before restarting the operation of the processor main circuit at the time of bias switching, and as a means for stabilizing the bias. An on-chip timer for measuring the passage of time or a sensor for detecting that the bias has stabilized at a predetermined voltage is provided.
[0014]
Another feature of the processor of the present invention is that the semiconductor device of the processor chip has a triple well structure, is divided into a plurality of functional modules, and these are formed on different well regions respectively. A circuit, a substrate bias switching device for switching a substrate bias applied to a substrate of each functional module, and a substrate bias of the functional module in response to execution of an instruction to set one or a plurality of the functional modules in a processor main circuit to standby. Bias switching device is controlled to switch to a voltage for a standby mode, and a substrate bias switching device is configured to switch a bias to a voltage for a normal mode when a standby release signal of the functional module is received from an external or processor main circuit. Control and switch that Bias voltage is to include a operation mode control unit for notifying that the standby function modules in the processor main circuit is released after the stable.
[0015]
Further, the processor of the present invention includes a means for dynamically switching the operation speed of the processor main circuit, and a substrate bias switching device which receives an instruction to change the operating frequency in the processor main circuit and executes the substrate bias of the processor main circuit or the functional module. And an operation mode control unit that controls the processor main circuit to notify that the switching of the operation speed has been completed after the switched bias voltage is stabilized.
[0016]
Further, a feature of the processor of the present invention is that the substrate bias switching device is constituted by a substrate bias generation circuit for internally generating a substrate bias voltage.
[0017]
The present invention also proposes a control method that contributes to low power consumption of the device. That is, although a transistor with a low threshold value operates at high speed, the leakage current between the source and the drain is large and power consumption is increased. Therefore, it is important to prevent this.
[0018]
The configuration for this is a control method for controlling the power consumption of a semiconductor integrated circuit device having a plurality of element circuit blocks having a transistor formed on a semiconductor substrate and operating based on a clock signal. All operate on the basis of the clock, the second mode in which the supply of the clock signal to at least one of the element circuit blocks is stopped, and the supply of the clock signal in all of the element circuit blocks is stopped. In addition, a third mode in which the substrate bias of at least a part of the transistor formed on the semiconductor substrate is controlled to increase the threshold value of the transistor is switched and used.
[0019]
The main circuit is, for example, a processor including a CPU and the like. The first mode is a mode in which the main circuit performs a normal operation (operation, storage, and the like).
[0020]
The second mode is a state where the clock to a part of the processor is stopped, and is called, for example, a sleep mode, a deep sleep mode, or the like. By selecting the range in which the clock is stopped, low power consumption can be achieved while maintaining only necessary functions.
[0021]
The third mode is a mode in which a substrate bias is controlled with respect to a processor circuit, a threshold value of a transistor constituting the same is increased, and power consumption due to a subthreshold leak current is reduced. This is called a standby mode. The standby mode can be returned to the normal state by interrupt control, but the hardware standby mode cannot be recovered without resetting. In the third mode, the function of the main circuit is stopped.
[0022]
As a configuration of the whole circuit, the element circuit block is included in the first circuit block, the clock signal is formed by an oscillation circuit included in the second circuit block, and the clock signal is transmitted from the second circuit block to the first circuit block. A signal and an information signal to be processed in the first circuit block are input. In addition, the second circuit block includes an input / output circuit and a control circuit for controlling the substrate bias. Normally, the second circuit block is not required to operate at a higher speed than the first circuit block including the main circuit. Therefore, it is preferable that the transistors included in the second circuit block have higher threshold voltages and higher operating voltages than the transistors included in the first circuit block. Further, the transistor forming the main circuit of the first circuit block is formed on a well separate from other circuits, so that the influence of other circuits can be reduced.
[0023]
If the operating voltages of the first and second circuit blocks are different, a level conversion circuit is required between them. For example, a level-down circuit is provided in a first circuit block, and a level-up circuit is provided in a second circuit block, to convert a signal level.
[0024]
In the present invention, since the substrate bias voltage is dynamically switched by mode switching, the operation sequence is important for ensuring reliability.
[0025]
When switching from the first or second mode to the third mode, the clock signal input from the second circuit block to the first circuit block or the first signal to be processed by the first circuit block. First, the information signal input to the circuit block is stopped, and then the substrate bias of at least a part of the transistor formed on the semiconductor substrate is controlled to increase the threshold value of the transistor. Accordingly, it is possible to prevent input to the first circuit block when the operation of the first circuit block is unstable, and to prevent malfunction of the first circuit block.
[0026]
For this operation, it is possible to adopt a configuration in which the input of signals to the first circuit block is stopped, a predetermined time (for example, about 60 microseconds) is waited by a timer or the like, and then the substrate bias is controlled. The timer for waiting is arranged outside the first circuit block, for example, inside the second circuit block or outside the device.
[0027]
When switching from the third mode (standby mode) to the first mode, the transistor bias is controlled by controlling the substrate bias of at least a part of the transistor formed on the semiconductor substrate, Then, the input of the clock signal input from the second circuit block to the first circuit block and the information signal to be processed by the first circuit block are started. That is, in order to prevent malfunction of the first circuit block, signal input is started after the substrate voltage of the first circuit block is stabilized.
[0028]
Therefore, when switching from the third mode to the first mode, the threshold value of the transistor is reduced by controlling the substrate bias of the first circuit block, and the operation is stabilized by waiting for a predetermined time by the timer. After that, the input of the clock signal and other signals input to the first circuit block is started.
[0029]
As another method, after the state of the threshold value of the transistor is confirmed by a voltage monitor or the like, signal input to the first circuit block is started. Alternatively, the input of the clock signal and other signals input to the first circuit block is started based on the state of the substrate bias generation circuit that controls the substrate voltage and in accordance with the signal output from the substrate bias generation circuit that indicates the release of standby. I do.
[0030]
As a method of stopping the information signal and the clock signal for the first block, a signal level may be fixed by an output fixing circuit (level hold circuit) provided in the second circuit block. In the first mode, the signal is input to the level down circuit via the output fixing circuit, but in the third mode, the input to the level down circuit is fixed.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0032]
FIG. 1 is a block diagram showing a configuration example of a processor chip for realizing the first embodiment of the present invention. In FIG. 1, a processor chip 101 is an LSI chip having a circuit having a CMOS structure, and includes a processor main circuit 102, an operation mode control unit 103, and a substrate bias switching device 104. The substrate bias switching device 104 receives from the signal 110 the voltages Vdd and Vss in the normal mode of the substrate bias and the voltages Vddb and Vssb in the standby mode. The substrate bias switching device 104 selects either Vdd or Vddb as the substrate bias of the pMOS transistor constituting the processor main circuit 102 according to the signal 107 output from the operation mode control unit, and outputs the selected signal to the signal Vbp111. Either Vss or Vssb is selected as a bias and output as a signal Vbn112. The voltage values for selecting the substrate bias are, for example, Vdd = 1.5 V, Vddb = 3.0 V, Vss = 0.0 V, and Vssb = −1.5 V.
[0033]
As will be described later, the well 302 in which the processor main circuit 102 is formed is formed independently of the well in which the substrate bias switching device 104 and the operation mode control unit are formed.
[0034]
FIG. 3 is a sectional view showing the device structure of the processor chip 101. FIG. 3 differs from FIG. 2 in that a p-well 302 is formed in an n-type substrate 301 and an n-well 205 is formed in a part of the surface phase, that is, the device has a triple well structure. is there. An nMOS transistor is formed on the surface of the p-well 302 and a pMOS transistor is formed on the surface of the n-well 205, thereby forming a CMOS circuit. Also, as a terminal for applying a substrate bias, Vbp 209 is provided in the n-well 205 of the pMOS transistor and Vbn 210 is provided in the p-well 302 of the nMOS transistor, as in FIG. In this embodiment, the processor main circuit 102 is formed in a p-well 302 different from the operation mode control unit 103 and the substrate bias switching device 104. As a result, the influence of the substrate bias control affects only the processor main circuit 102, and the operation mode control unit 103 and the substrate bias switching device 104 can avoid the influence.
[0035]
The operation of the processor chip 101 in this embodiment will be described with reference to FIG. The operation modes of the processor main circuit 102 include a normal mode in which normal instructions are executed and a standby mode in which no instructions are executed. FIG. 4 is a flowchart showing processing on the processor chip 101 when the operation mode of the processor main circuit 102 changes from the normal mode to the standby mode, and changes from the standby mode to the normal mode.
[0036]
First, the processor main circuit 102 operates in the normal mode. At this time, the substrate bias switching device 104 selects Vdd and Vss for the substrate biases Vbp111 and Vbn112, respectively. In this example, the voltage values of the substrate bias in the normal mode are Vbp = 1.5 V and Vbn = 0 V (step 401).
[0037]
When executing the sleep command, the processor main circuit 102 outputs a “standby request” to the signal 105 and transmits the signal to the operation mode control unit 103, and then stops the command execution operation and shifts to the standby mode (step 402).
[0038]
When receiving the signal 105 from the processor main circuit, the operation mode control unit 103 outputs a signal 107 to switch the substrate bias of the processor main circuit 102 to the voltage for the standby mode. The substrate bias switching device 104 receives the signal 107, selects Vddb and Vssb from the input voltage 110 and outputs them to the substrate biases Vbp111 and Vbn112 (steps 403 and 404). In this example, the voltage values of the substrate bias in the standby mode are Vbp = 3.0V and Vbn = -1.5V.
[0039]
When the operation mode control unit 103 detects that the “standby release interrupt” is externally asserted to the signal 108 while the processor main circuit 102 is in the standby state (step 405), the operation mode control unit 103 changes the substrate bias of the processor main circuit 102. A signal 107 is output to switch to the voltage for the normal mode, and the substrate bias switching device 104 receives the signal 107 and switches the substrate biases Vbp111 and Vbn112 to Vdd (1.5V) and Vss (0.0V), respectively. (Step 406).
[0040]
After the substrate bias is switched, some time is required until the bias voltage is stabilized. Therefore, if the operation of the processor main circuit 102 is restarted immediately, a malfunction may occur. To avoid this, before switching the operation mode of the processor main circuit 102, the operation mode control unit 103 sets and starts a sufficient time necessary for stabilizing the switched substrate bias voltage in the on-chip timer 109 (step 407). , And waits until timeout (step 408). Then, after the timeout, the operation mode control unit 103 outputs “standby release” to the signal 106 and notifies the signal to the processor main circuit 102. Upon receiving this signal 106, the processor main circuit 102 shifts to the normal mode and resumes the instruction execution operation (step 409).
[0041]
As described above, the substrate biases Vbp111 and Vbn112 of the processor main circuit 102 are controlled to lower the threshold voltage of the MOS transistors constituting the processor main circuit during operation so as to support high-speed operation, and to set the threshold during standby. Leakage current can be reduced by increasing the value voltage.
[0042]
FIG. 5 is a block diagram showing a configuration of a processor chip according to the second embodiment of the present invention. In this embodiment, the operation mode control unit 103 includes a sensor 501 for detecting a bias voltage applied to the substrate of the processor main circuit 102. When the operation mode of the processor main circuit 102 transitions from the normal mode to the standby mode, it is the same as the processing procedure in the first embodiment. When the operation mode of the processor main circuit 102 shifts from the standby mode to the normal mode, the operation mode control unit 103 controls the substrate bias switching device 104 to change the substrate bias to the voltage of the normal mode as in the first embodiment. After the switching, it waits until the signal 502 outputs that the voltage of the substrate bias switched by the sensor 501 has been stabilized to a predetermined value, that is, Vbp = 1.5 V and Vbn = 0.0 V in this embodiment. When the sensor 501 outputs the stability of the substrate bias to the signal 502, the operation mode control unit 103 outputs “standby release” to the signal 106 to restart the operation of the processor main circuit 102.
[0043]
FIG. 6 is a block diagram showing a configuration of a processor chip according to the third embodiment of the present invention. As a basic device structure of the processor chip 601, the triple well structure shown in FIG. 3 is considered. In the processor chip 601 shown in FIG. 6, the processor main circuit includes a plurality of functional modules such as a CPU 604, a module A 606, and a module B 608. Each functional module is separately provided on a different well region, and is not affected by substrate bias control of other functional modules. The function module includes a smaller unit such as a CPU, an FPU, a cache, or an arithmetic unit. The substrate bias switching devices 605, 607, and 609 are provided corresponding to the respective functional modules 604, 606, and 608, and can switch the substrate bias of the corresponding functional module in the same manner as in the above-described embodiment. The execution of the instruction is performed mainly by the CPU 604, which is one of the functional modules. When the instruction for setting the functional module unnecessary for the execution to the standby mode is executed, the standby of the functional module is transmitted to the operation mode control unit 602.
[0044]
The operation of the processor chip 601 in this embodiment will be described next. First, it is assumed that all functional modules are operating in the normal mode. When the CPU 604 executes the instruction to set the module A to standby, the CPU 604 outputs the standby request to the signal 610, and the module A 606 cannot be used until the standby of the module A 606 is released. The operation mode control unit 602 receives the signal 610 and outputs a signal 612 to the substrate bias switching device 607 to switch the substrate bias of the module A 606 to a voltage for the standby mode. When the operation mode control unit 602 receives the output signal 610 of the CPU 604 or the signal for canceling the standby of the module A 606 from the signal 613 external to the processor chip 601 when the module A 606 is in the standby state, the operation mode control unit 602 changes the signal 612 to the substrate bias switching device 607. To switch the substrate bias of the module A to the voltage for the normal mode. The operation mode control unit 602 waits for stabilization of the switched substrate bias using the on-chip timer 603 in the same manner as in the first embodiment of the present invention, and after the stabilization, the standby of the module A is released via the signal 611 to the CPU 604. Notify. Upon receiving the signal 611, the CPU 604 can execute an instruction using the module A.
[0045]
The same applies to the standby control of the module B608 and other functional modules. The CPU 604 itself is also a target of the standby control. In this case, when the CPU 604 shifts to the standby mode, the CPU 604 stops executing all instructions, and when the signal for canceling the standby of the CPU 604 is asserted to the external signal 613, the operation mode control unit 602 issues a signal after the switching of the substrate bias of the CPU 604 is completed. The control is performed in the same manner as in the case of the module A 606 except that the CPU 604 is asserted to release the standby mode to 611 and the instruction execution of the CPU 604 is resumed.
[0046]
With the standby control for each functional module in the present embodiment, it is possible to reduce unnecessary leak current of the functional module during operation of the processor.
[0047]
FIG. 7 is a block diagram showing a configuration of a processor chip according to the fourth embodiment of the present invention. The difference from the first embodiment is that the number of types of the voltage 701 supplied from the outside to the substrate bias switching device 104 is increased, and the substrate bias switching device 104 selects an appropriate one of them as the substrate bias, and That is, it can be applied to the main circuit 102. In the present embodiment, means for dynamically changing the operation speed of the processor main circuit 102, that is, the operation frequency by an instruction is provided, and the operation mode of the processor main circuit 102 is assumed to have a high-speed mode and a low-speed mode. In this embodiment, Vdd (for pMOS) and Vss (for nMOS) are used as the substrate bias corresponding to the high-speed mode, Vddb2 (for pMOS) and Vssb2 (for nMOS) are used as the substrate bias corresponding to the low-speed mode, and the standby mode is supported. Vddb1 (for pMOS) and Vssb1 (for nMOS) are selected as the substrate bias.
[0048]
Next, the operation of the processor chip 101 in this embodiment will be described. Here, consider a case where the operation mode of the processor main circuit 102 is switched from the high-speed mode to the low-speed mode. While the processor main circuit 102 is operating in the high-speed mode, the substrate bias switching device 104 selects Vdd for Vbp111 and Vss for Vbn112 as the substrate bias of the processor main circuit. When executing the instruction to shift to the low-speed mode, the processor main circuit 102 outputs the request to the signal 105 and interrupts the instruction execution operation. The clock supplied to the processor main circuit 102 is switched to a low frequency by execution of the instruction for shifting to the low-speed mode. The operation mode control unit 103 receives the signal 105 and outputs the signal 107 to switch the substrate bias of the processor main circuit 102 to the low-speed mode voltage. The substrate bias switching device 104 receives the signal 107 and switches the substrate biases Vbp111 and Vbn112 to Vddb2 and Vssb2, respectively. The operation mode control unit 103 waits for the switched substrate bias to stabilize using the on-chip timer 109 in the same manner as in the above embodiment, and notifies the processor main circuit 102 via the signal 106 that the transition to the low-speed mode has been completed. Upon receiving this signal 106, the processor main circuit 102 resumes the interrupted instruction execution operation in the low-speed mode.
[0049]
The operation at the time of switching from the low-speed mode to the high-speed mode, switching from the high-speed mode or the low-speed mode to the standby mode, or switching from the standby mode to the high-speed mode or the low-speed mode in the present embodiment is also the same as described above, so details are omitted. I do. In this embodiment, the operation speed can be further subdivided, and the substrate bias control corresponding thereto can be performed. Further, as in the third embodiment, the processor main circuit 102 is separated for each functional module by using a triple well structure of a device, and the substrate bias is controlled for each functional module in conjunction with switching of its operating frequency. It is also possible.
[0050]
By performing the substrate bias control suitable for the operating frequency of the processor as in the present embodiment, it is possible to reduce the leak current in the low-speed operation mode. Furthermore, in this low-speed mode, the range of the input voltage at which both the pMOS and nMOS transistors of the CMOS circuit conduct simultaneously becomes narrower than in the high-speed operation mode, so that the effect of reducing the through current at the time of switching can be obtained. .
[0051]
FIG. 8 is a block diagram showing a configuration of a processor chip according to the fifth embodiment of the present invention. This embodiment differs from the first embodiment in that the substrate bias switching device comprises a substrate bias generation circuit 801. The substrate bias generation circuit 801 is controlled by an output signal 802 of the operation mode control unit 103, internally generates a substrate bias voltage, and outputs it to Vbp111 and Vbn112. The voltage values of the substrate biases Vbp111 and Vbn112 generated corresponding to the operation mode of the processor main circuit 102 under the control of the operation mode control unit 103 are the same as those in the first embodiment. The operations of the processor main circuit 102 and the operation mode control unit 103 are the same as those of the first embodiment, and thus the details are omitted. By configuring the substrate bias switching device in the second, third, and fourth embodiments with the substrate bias generation circuit 801 in the same manner as in the present embodiment, a substrate bias is generated inside the processor chip, and the operation mode is changed. Can be switched according to
[0052]
As described above, according to these embodiments, the timing for restarting the processor at the time of transition from the standby state to the operating state is accurately controlled using the timer or the sensor. Substrate bias control becomes possible. As a result, it is possible to reduce the leak current in the standby mode while maintaining the high speed in the normal operation mode of the processor. Further, by performing the substrate bias control according to the operation mode of each functional module, it is possible to reduce the leak current of the functional module which is unnecessary for execution even when the processor is operating. Further, by performing the substrate bias control suitable for the operating frequency of the processor, in addition to the reduction of the leak current in the low-speed mode, the effect of reducing the through current at the time of switching can be obtained.
[0053]
As a result, power consumption can be effectively reduced, and a microprocessor having both high speed and low power can be provided.
[0054]
Hereinafter, an operation mode for controlling the substrate bias will be specifically described as an embodiment of the microcomputer. The microcomputer has two power supplies, 1.8 V and 3.3 V, and controls the substrate bias only at 1.8 V. It is desirable that the circuit for supplying 1.8 V is configured by a MOS transistor having a relatively low threshold value (for example, Vth <0.4 V).
[0055]
FIG. 9 shows an example of the operation mode of the microcomputer. The operation modes include a normal operation mode 982 that operates normally and a reset mode 981. Modes that operate with low power consumption include sleep 983, deep sleep 984, standby 985, hardware standby 986, and RTC (real-time clock) battery backup mode. The test mode includes IDDQ measurement.
[0056]
At the time of the normal operation 982, high-speed operation is required, so that control of the substrate bias is not performed. At the time of the reset 981, all the functions need to be reset, so that the control of the substrate bias is not performed. In the low power consumption mode, in the sleep 983 and the deep sleep 984 in which the return time from the low power consumption mode is short, the substrate bias is not controlled, but the standby 985 which focuses on making the power consumption smaller than the return time. In the case of hardware standby 986, substrate bias control is performed. The RTC battery backup mode is a mode in which only the power of the RTC circuit operating at 3.3 V is supplied. Since the transition to this mode is made from the low power consumption mode, substrate bias control is performed. In addition, the IDDQ measurement is a mode in which the standby current is measured and the through current due to short-circuit or failure of the transistor is measured. In this case, the substrate bias is always controlled to reduce the chip leakage power. It is necessary to make it easy to find defects.
[0057]
Before describing the low power consumption operation mode in FIG. 10, the configuration of the internal block of the processor main circuit 902 will be described. This figure is an example of the main constituent blocks of the processor main circuit. The arithmetic circuits include a CPU (central processing unit) 971 and an FPU (floating point arithmetic unit) 972. Also, a cache 973 which is a memory built in the chip, a BSC (bus control unit) 974 for interfacing with an external memory, a DMAC (DMA control unit) 975 for performing DMA (direct memory access), and an SCI (SCI) for controlling a serial port A serial control unit) 976; an INTC (interrupt control unit) 977 for controlling an interrupt input; and a CPG (clock control unit) 978 for controlling a clock.
[0058]
Referring to FIG. 11, the sleep 983, the deep sleep 984, and the standby 985 which are the low power consumption modes will be described.
[0059]
In the sleep 983, since only the clocks of the arithmetic devices such as the CPU 971, the FPU 972, and the cache 973 are stopped and the substrate bias control is not performed, the power consumption cannot be significantly reduced, but the DMA transfer by the DMAC 975 or the BSC 974 Normal refresh (1024 times / 16 ms refresh) of DRAM (dynamic RAM) or SDRAM (synchronous dynamic RAM) is possible. Since the CPG 978 is operating and the substrate bias control is not performed, the return time from the sleep 983 to the normal operation mode 982 is short.
[0060]
In the standby 985 mode, power consumption is extremely small because all operation clocks are stopped and substrate bias control is also performed. Since the clock is stopped, DMA transfer cannot be performed. Regarding the refresh of the DRAM and the SDRAM, the control signals (RAS signal and CAS signal) of each memory are set using the BSC 974 so that the memory enters a self-refresh mode in which the memory performs a refresh before entering the standby 985. It is necessary to keep. However, the return time from the standby 985 to the normal operation 982 is long because the clock is stopped, and the recovery time from the clock oscillation stabilization and the return from the substrate bias state is long.
[0061]
The deep sleep 984 mode is a low power consumption mode intermediate between sleep 983 and standby 985.
[0062]
FIG. 12 shows the difference between the operation modules of the sleep 983 and the deep sleep 983. In the sleep 983, the operating BSC 973, DMAC 974, and SCI 975 are stopped in the deep sleep 984, so that power consumption can be reduced accordingly.
[0063]
However, in the deep sleep 984 mode, the DMA transfer cannot be performed, and the memory refresh becomes a self refresh. The return time from the deep sleep 984 to the normal operation mode 982 is short as in the sleep mode.
[0064]
By providing the three types of low power consumption modes in this manner, it is possible to perform fine low power consumption control according to the application.
[0065]
A state transition diagram of the operation mode will be described with reference to FIG. The processor chip transitions to the reset state 981 by inputting the RESET # 952 (or power-on reset) pin from the state where all power supplies are off 980. When RESET # 952 is negated, the process makes a transition to normal operation 982. From this state, a transition is made to the low consumption operation mode.
[0066]
There are two transition methods. One is a transition by an instruction. This transition is made when the CPU 971 executes the sleep command. A sleep register 983, a deep sleep 984, and a standby 985 can be selected by setting a mode register when a sleep command is executed, and the mode can be transited to each mode. Returning from each mode to the normal operation mode 982 is an interrupt 958.
[0067]
Another transition method is a transition using the HARDSTB # 951 pin. When this pin is asserted, a transition is made to the hardware standby state 986. In this state, as in the case of the standby 985, all the clocks are stopped, and the substrate bias control is being performed.
[0068]
In this mode, if the input / output buffer is set to high impedance, the 3.3 V circuit does not have a transistor through which a through current flows, and the IDDQ can be measured.
[0069]
Further, if the input buffer of the RTC circuit placed in the 3.3V system is fixed, the input signal of the RTC circuit does not become floating (intermediate level) even when the power supply other than the RTC circuit is turned off. Malfunction can be prevented, and only the RTC circuit can be operated.
[0070]
Next, an application example of the hardware standby will be described.
[0071]
FIG. 14 shows a configuration of the processor chip 901 and a configuration of a power supply control circuit that make the power supply 904 (battery) of the processor chip 901 replaceable by applying hardware standby.
[0072]
The processor chip 901 includes a 1.8 V region circuit 930 operating at 1.8 V and a 3.3 V region circuit 931 operating at 3.3 V. The 1.8 V region circuit 930 includes a processor main circuit 902 and level down circuits 905 and 906 for converting the level from 3.3 V to 1.8 V. The circuit 931 in the 3.3V region includes a substrate bias generation circuit 903, a clock oscillation circuit 908, an IO circuit 909, an operation mode control unit 913, an RTC circuit 914, and level-up circuits 904 and 910 for converting the level from 1.8V to 3.3V. And output fixing circuits 907 and 911 for fixing a signal from 3.3 V to 1.8 V.
[0073]
As a power supply control circuit, there are a power supply 904, a power supply monitoring circuit 921, a display 922, and a voltage generation circuit 920 that generates a 1.8V system voltage.
[0074]
The operation will be described below. When the processor chip 901 is in the normal operation mode 982, the substrate bias generation circuit 903 holds a normal substrate level (for example, a VDD potential for a PMOS and a VSS potential for an NMOS) without subtracting a substrate bias. The clock oscillation circuit 908 is composed of a PLL (Phase Locked Loop) or the like, generates a clock for internal operation, and sends it to the processor main circuit 902 via the output fixing circuit 907 and the level down circuit 905. The IO circuit 909 takes in an external signal and sends it to the processor main circuit 902 via the output fixing circuit 907 and the level down circuit 905. Further, a signal from the processor main circuit 902 is output to the outside via the level up circuit 904. The RTC circuit 914 operates at 3.3 V, receives a control signal from the processor main circuit 902 via the level up circuit 910, and sends a control signal to the processor main circuit 902 via the level down circuit 906 and the output fixing circuit 911. Send The operation mode control unit 913 particularly controls the substrate bias generation circuit 903.
[0075]
The power supply monitoring circuit 921 monitors the voltage level of the power supply 904. When the voltage level falls below a predetermined level (detection of a dead battery state), HARDSTB # 951 is set to a low level. At the same time, an alarm indicating that the battery has run out is displayed on the display 922 to notify the user. The voltage holding circuit 923 can hold the voltage level for a predetermined period (several minutes to several hours) even when the voltage level is lowered. During this period, the user can replace the power supply 904.
[0076]
The power supply replacement sequence will be described below with reference to FIG.
(1) When HARDSTB # 951 goes low, the operation mode enters the hardware standby state 986. Here, the 1.8 V signal fixing 953 is output from the operation mode control unit 913 to fix the signal from 3.3 V to 1.8 V and stop the 1.8 V system clock. As a result, even when the substrate bias is pulled, the 1.8 V system signal does not operate. Therefore, the state in which the substrate bias is pulled (the state in which the threshold voltage of the MOS transistor is increased and the operation speed is reduced) This prevents the 1.8V circuit from malfunctioning when the substrate potential is unstable. In this state, a substrate bias control start signal 955 is output to the substrate bias generation circuit 903.
(2) Thereafter, a substrate bias control start signal 955 is output to the substrate bias generation circuit 903 based on the timing of the 1.8 V signal fixing 953. Between the signal fixing 953 and the substrate bias control start 955, a time difference is set until the signal is actually fixed and the supply of the signal to the 1.8 V region is stopped. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914.
(3) Upon receiving the substrate bias control start signal 955, the substrate bias generation circuit 903 starts pulling the substrate bias of the 1.8V substrate. While the substrate bias is being pulled, a 956 signal during the substrate bias control is returned to the operation mode control unit 913.
(4) The processor main circuit 902 does not operate while the substrate bias is being pulled. Furthermore, since the leak current is small, the current consumption is small. Accordingly, the holding time of the voltage holding circuit 923 also becomes longer.
(5) The power supply 904 is replaced in this state.
(6) After the power supply is replaced, the power supply voltage returns to the normal level, so that HARDSTB # 951 returns to the high level.
(7) Thereafter, the power-on reset circuit operates, and RESET # 952 is input. With this reset input, the substrate bias control start signal 955 output from the operation mode control unit 913 is released.
(8) In response to the cancellation of the substrate bias control start signal 955, the substrate bias generation circuit 903 changes the substrate bias of the 1.8V system substrate to the operating state potential (for example, VDD potential for PMOS and VSS potential for NMOS). Start returning. A predetermined time is required until the substrate bias is recovered, and when the substrate bias is returned, the operation mode control unit 913 is notified by canceling the substrate bias control signal 956.
(9) In response to the cancellation of the substrate bias control signal 956, the 1.8V signal fixing 953 output from the operation mode control unit 913 is canceled, and the signal is sent to the 1.8V circuit such as the processor main circuit 902. Is entered.
(10) After the reset state 981, the normal state 982 is entered, and the processor main circuit 902 starts a normal operation.
[0077]
As described above, the power supply 904 can be replaced using the low power consumption mode by the hardware standby.
[0078]
Next, a second application example of the hardware standby will be described.
[0079]
FIG. 16 shows a configuration example for realizing the RTC power supply backup mode. The RTC circuit 914 is called a real-time counter, and realizes a clock or calendar function. For this reason, the function of the clock cannot be realized unless it is constantly operating. Even when the power supply 904 is cut off, the RTC circuit 914 needs to operate.
[0080]
In the embodiment shown here, in order to realize the RTC power supply backup mode, the 3.3 V region is divided into a normal 3.3 V region 991 and a region 992 operating at 3.3 V of RTC. In the 3.3V area 992 of the RTC, an input fixed circuit 912 and an input fixed level-up circuit 960 are added to the input circuit, and other power supplies (1.8 V, a normal 3.3 V power supply) are cut off. In this state, even if the input signal becomes floating, an intermediate level signal is not transmitted to the region 992 operating at 3.3 V of the RTC, thereby preventing a malfunction.
[0081]
As a power supply control circuit, there are a backup battery 962 and diodes 963 and 964, in addition to a power supply 904, a power supply monitoring circuit 921, a display 922, and a voltage generation circuit 920 that generates 1.8V system voltage.
[0082]
The operation will be described below. In the normal operation mode 982, the substrate bias generation circuit 903 holds the normal substrate level without subtracting the substrate bias. The clock oscillation circuit 908 is composed of a PLL (Phase Locked Loop) or the like, generates a clock for internal operation, and sends it to the processor main circuit 902 via the output fixing circuit 907 and the level down circuit 905. The IO circuit 909 takes in a signal from the outside and sends it to the processor main circuit 902 via the output fixing circuit 907 and the level down circuit 905. Further, a signal from the processor main circuit 902 is output to the outside via the level up circuit 904. The RTC circuit 914 operates at 3.3V, receives a control signal from the processor main circuit 902 via the input fixed level up circuit 960, and controls the processor main circuit 902 via the level down circuit 906 and the output fixed circuit 911. Send a signal. The operation mode control unit 913 receives a control signal via the input fixing circuit 912, and controls the substrate bias generation circuit 903 in particular.
[0083]
The power supply monitoring circuit 921 monitors the voltage level of the power supply 904. When the voltage level falls below a predetermined level (detection of a dead battery), HARDSTB # 951 is set to a low level, the input of RTC 3.3V region 992 is fixed, and the malfunction of RTC circuit 914 is prevented. At the same time, an alarm indicating that the battery has run out is displayed on the display 922. Thereafter, the voltage level continues to drop, and the 3.3 V and 1.8 V system voltages are no longer supplied to the processor chip 901. At this time, the voltage (VDD-RTC, VSS-RTC) is supplied only from the backup battery 962 to the 3.3 V region of the RTC via the diode 963, and only the RTC circuit 914 (calendar counter circuit) is provided without the power supply 904. Works fine. The diode 964 prevents a current from flowing to components other than the RTC circuit 914.
[0084]
The RTC power supply backup sequence will be described in detail with reference to FIG.
(1) When HARDSTB # 951 goes low, the operation mode enters the hardware standby state 986. Here, the 1.8 V signal fixing 953 is output from the operation mode control unit 913 to fix the signal from 3.3 V to 1.8 V and stop the 1.8 V system clock. As a result, even when the substrate bias is pulled, the 1.8 V system signal does not operate, so that a malfunction of the 1.8 V system circuit while the substrate bias is pulled is prevented. At the same time, an input fixing signal 954 to the RTC circuit 914 is output to fix the input signal. This prevents an unstable intermediate level signal from entering the RTC circuit 914 when the other power supply is cut off.
(2) Thereafter, a substrate bias control start signal 955 is output to the substrate bias generation circuit 903 based on the timing of the 1.8 V signal fixing 953. Between the signal fixing 953 and the substrate bias control start 955, a time difference is set until the signal is actually fixed and the supply of the signal to the 1.8 V region is stopped. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914.
(3) Upon receiving the substrate bias control start signal 955, the substrate bias generation circuit 903 starts pulling the substrate bias of the 1.8V substrate. While the substrate bias is being pulled, a 956 signal during the substrate bias control is returned to the operation mode control unit 913.
(4) The processor main circuit 902 does not operate while the substrate bias is being pulled. Furthermore, since the leak current is small, the current consumption is small.
(5) The interruption period of the power supply 904 may be long. Further, the power supply 904 can be replaced.
(6) After the power supply 904 is recovered from the cutoff (or after the power supply 904 is replaced), the power supply voltage returns to the normal level, so that HARDSTB # 951 returns to the high level.
(7) Thereafter, the power-on reset circuit operates, and RESET # 952 is input. With this reset input, the substrate bias control start signal 955 is released.
(8) In response to the cancellation of the substrate bias control start signal 955, the substrate bias generation circuit 903 changes the substrate bias of the 1.8V system substrate to the operating state potential (for example, VDD potential for PMOS and VSS potential for NMOS). Start returning. A predetermined time is required until the substrate bias is recovered, and when the substrate bias is returned, the operation mode control unit 913 is notified by canceling the substrate bias control signal 956.
(9) In response to the cancellation of the substrate bias control signal 956, the 1.8V signal fixing 953 output from the operation mode control unit 913 is canceled, and the signal is sent to the 1.8V circuit such as the processor main circuit 902. Is entered.
(10) After the reset state 981, the normal state 982 is entered, and the processor main circuit 902 starts a normal operation.
[0085]
In the above sequence, a power switch can be provided for the power supply 904, and only the RTC circuit 914 can be operated during the power-off period.
[0086]
As described above, by using the hardware standby, only the RTC circuit 914 can be operated with battery backup.
[0087]
FIG. 18 illustrates a sequence in which the normal sleep command 959 is used to enter the standby state 985 and return to the normal state 982 by the interrupt signal 958.
(1) The sleep mode 959 causes the operation mode to enter the standby state 985. Here, the 1.8 V signal fixing 953 is output from the operation mode control unit 913 to fix the signal from 3.3 V to 1.8 V and stop the 1.8 V system clock. This prevents a malfunction of the 1.8 V system circuit when the substrate bias is pulled.
(2) Thereafter, a substrate bias control start signal 955 is output to the substrate bias generation circuit 903 based on the timing of the 1.8 V signal fixing 953. Between the signal fixing 953 and the substrate bias control start 955, a time difference is set until the signal is actually fixed and the supply of the signal to the 1.8 V region is stopped. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914.
(3) Upon receiving the substrate bias control start signal 955, the substrate bias generation circuit 903 starts pulling the substrate bias of the 1.8V substrate. While the substrate bias is being pulled, a 956 signal during the substrate bias control is returned to the operation mode control unit 913.
(4) The processor main circuit 902 does not operate while the substrate bias is being pulled. Furthermore, since the leak current is small, the current consumption is small.
(5) In this state, when an interrupt signal 958 is received from the control signal 957 (external pin) via the IO circuit 909, the operation mode control unit 913 cancels the substrate bias control start signal 955.
(6) In response to the cancellation of the substrate bias control start signal 955, the substrate bias generation circuit 903 changes the substrate bias of the 1.8V system substrate to the operating state potential (for example, VDD potential for PMOS, VSS potential for NMOS). Start returning. A predetermined time is required until the substrate bias is recovered, and when the substrate bias is returned, the operation mode control unit 913 is notified by canceling the substrate bias control signal 956.
(7) Upon receiving the cancellation of the substrate bias control signal 956, the operation mode control unit 913 cancels the 1.8V signal fixing 953. By releasing the 1.8 V signal fixing 953 after the substrate bias control signal is released, malfunction of the 1.8 V system circuit is prevented.
(5) A signal is input to a 1.8 V system circuit such as the processor main circuit 902 and enters a normal state 982, and the processor main circuit 902 starts a normal operation.
[0088]
As described above, the processor chip 901 enters the low power consumption mode and can be restored by the interruption.
[0089]
FIG. 19 illustrates a sequence in which the normal sleep command 959 is used to enter the standby state 985 and return to the normal state 982 by RESET # 952.
(1) The sleep mode 959 causes the operation mode to enter the standby state 985. Here, the 1.8 V signal fixing 953 is output from the operation mode control unit 913 to fix the signal from 3.3 V to 1.8 V and stop the 1.8 V system clock. This prevents a malfunction of the 1.8 V system circuit when the substrate bias is pulled.
[0090]
After that, the completion of signal fixing is measured by the 1.8 V signal fixing 953, and a substrate bias control start signal 955 is output to the substrate bias generation circuit 903.
(2) Upon receiving the substrate bias control start signal 955, the substrate bias generation circuit 903 starts pulling the substrate bias of the 1.8V system substrate. While the substrate bias is being pulled, a 956 signal during the substrate bias control is returned to the operation mode control unit 913.
(3) The processor main circuit 902 does not operate while the substrate bias is being pulled. Furthermore, since the leak current is small, the current consumption is small.
(4) In this state, the operation mode control unit 913 receives RESET # 952 and cancels the substrate bias control start signal 955.
(5) In response to the cancellation of the substrate bias control start signal 955, the substrate bias generation circuit 903 starts to return the substrate bias of the 1.8V system substrate to the operating state potential. When the substrate bias is returned, the operation mode control unit 913 is notified using the substrate bias controlling signal 956.
(6) Upon receiving the release signal, the 1.8V signal fixing 953 is released.
(7) After the reset state 981 is completed, a signal is input to a 1.8 V system circuit such as the processor main circuit 902, and the normal state 982 is entered, and the processor main circuit 902 starts a normal operation.
[0091]
As described above, the processor chip 901 enters the low power consumption mode and can be restored by reset.
[0092]
As described above, the processor chip 901 has a portion to which 1.8 V is supplied as a power supply voltage and a portion to which 3.3 V is supplied as a power supply voltage. A portion to which 1.8 V is supplied includes, for example, a processor main circuit 902 and the like. This part has a large circuit scale and needs to operate at a higher speed. Since the circuit scale is large and high-speed operation is required, the power consumption in this part increases. In this embodiment, the power supply voltage is reduced in order to reduce the power consumption.
[0093]
Further, when the power supply voltage is lowered (for example, 1.8 V), the operation speed is reduced. Therefore, the threshold voltage of the MOS transistor is lowered (for example, Vth <0.4 V). Further, in this embodiment, the substrate voltage control is performed to reduce the sub-threshold leakage current due to the lower threshold.
[0094]
On the other hand, a portion where 3.3 V is supplied as a power supply voltage is, for example, an RTC circuit 914. Since these circuits are small-scale and operate at low speed, power consumption is small. Therefore, such a circuit block does not need to lower the power supply voltage. For example, Vth> 0.5V can be set. Since it is not necessary to lower the threshold value of the MOS transistor, there is an advantage that there is no need to take a current measure by controlling the substrate in order to reduce the sub-threshold leakage current.
[0095]
The processor chip 901 of this embodiment uses both of these power supply voltages. That is, a portion requiring large-scale high-speed operation uses a low-voltage low-threshold MOS with substrate control, and uses a high-voltage high-threshold MOS without substrate control. The method of manufacturing MOS transistors having different thresholds is not particularly limited, but can be realized by changing the amount of channel implantation. It can also be realized by changing the thickness of the gate oxide film. In the latter case, the threshold value may be increased by increasing the thickness of the oxide film of the MOS transistor. This is because a high threshold MOS is operated at a high voltage, so that it is necessary to increase the oxide film thickness. If the threshold can be increased by increasing the thickness of the oxide film, the process can be simplified.
[0096]
Further, since the input / output circuit 909 needs to transmit and receive the external signal amplitude of 3.3 V, it is desirable to use the same MOS transistor as the high-voltage threshold MOS because the process can be shared.
[0097]
【The invention's effect】
According to the present invention, a microprocessor that achieves both high speed and low power consumption can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram of a processor chip according to a first embodiment of the present invention.
FIG. 2 is a sectional view showing a general device structure used for substrate bias control.
FIG. 3 is a sectional view showing a device structure according to the first embodiment of the present invention.
FIG. 4 is a flowchart used to explain an operation in the first embodiment of the present invention.
FIG. 5 is a block diagram of a processor chip according to a second embodiment of the present invention.
FIG. 6 is a block diagram of a processor chip according to a third embodiment of the present invention.
FIG. 7 is a block diagram of a processor chip according to a fourth embodiment of the present invention.
FIG. 8 is a block diagram of a processor chip according to a fifth embodiment of the present invention.
FIG. 9 is a diagram illustrating a relationship between an operation mode and substrate bias control according to the present invention.
FIG. 10 is a diagram illustrating a configuration of a processor main circuit of the present invention.
FIG. 11 is a diagram illustrating a low power consumption mode of the present invention.
FIG. 12 is a diagram illustrating sleep and deep sleep according to the present invention.
FIG. 13 is a transition diagram of the operation mode of the present invention.
FIG. 14 is a first configuration diagram of a configuration of a processor chip and a power supply control circuit of the present invention.
FIG. 15 is a diagram illustrating a power supply replacement sequence according to the present invention.
FIG. 16 is a second configuration diagram of a configuration of a processor chip and a power supply control circuit of the present invention.
FIG. 17 is a diagram illustrating a sequence of RTC power supply backup according to the present invention.
FIG. 18 is a diagram illustrating a sequence from the low power consumption mode of the present invention to a return from an interrupt.
FIG. 19 is a diagram illustrating a sequence from a low power consumption mode of the present invention to a return from a reset.
[Explanation of symbols]
101: Processor chip, 102: Processor main circuit, 103: Operation mode control unit, 104: Substrate bias switching device, 109: Timer, 501: Sensor, 801: Substrate bias generation circuit.

Claims (10)

A logic circuit including at least one MOS transistor and having a first mode and a second mode;
A substrate bias control circuit for controlling a substrate bias voltage applied to the at least one MOS transistor;
An operation mode control unit that operates in response to execution of an instruction to shift to the first mode or an interrupt to shift to the second mode,
The operation mode control unit controls the substrate bias voltage in response to execution of the command, controls the substrate bias voltage in the first mode to a first voltage, and responds to the interrupt in response to the interrupt. And the substrate bias voltage in the second mode is controlled to a second voltage, and the absolute value of the threshold voltage of the at least one MOS transistor to which the first voltage is applied is equal to the absolute value of the second voltage. The absolute value of the threshold voltage of the at least one MOS transistor,
The logic circuit is controlled so that an input of the logic circuit does not change in response to execution of the command, and after the interruption, the substrate bias voltage applied to the at least one MOS transistor is stabilized to a predetermined level. A semiconductor integrated circuit that starts operating later. In claim 1,
The logic circuit includes a first conductivity type first MOS transistor and a second conductivity type second MOS transistor as the MOS transistor,
A semiconductor integrated circuit in which the first MOS transistor and the second MOS transistor constitute a CMOS circuit. In claim 2,
The substrate of the semiconductor integrated circuit has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type, and a third semiconductor region of a second conductivity type,
The third semiconductor region is formed in the second semiconductor region, the second semiconductor region is formed in the first semiconductor region,
The semiconductor integrated circuit, wherein the first MOS transistor is formed in the third semiconductor region, and the second MOS transistor is formed in the second semiconductor region. In claim 3,
A semiconductor integrated circuit wherein a substrate bias voltage of the first MOS transistor is applied to the third semiconductor region, and a substrate bias voltage of the second MOS transistor is applied to the second semiconductor region. In claim 3,
The semiconductor integrated circuit, wherein the operation mode control unit is formed in a semiconductor region different from the second semiconductor region. In claim 1,
The semiconductor integrated circuit includes a timer for measuring a period defined as a stable period of the substrate bias voltage. In claim 1,
The semiconductor integrated circuit includes a sensor that monitors stability of a substrate bias voltage of the at least one MOS transistor. In claim 1,
An input control circuit connected to an input of the logic circuit,
A semiconductor integrated circuit that controls an input of the logic circuit to a predetermined level from execution of the instruction to start of operation of the logic circuit; In claim 5,
An input control circuit connected to an input of the logic circuit,
The input control circuit controls the input of the logic circuit to a predetermined level from execution of the instruction to start of operation of the logic circuit,
The input control circuit is a semiconductor integrated circuit formed in a semiconductor region where the operation mode control circuit is configured. A semiconductor integrated circuit for controlling the input of the logic circuit at the time of shifting the substrate bias control of the logic circuit.

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