JP4387122B2 - Low power processor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device such as a processor, and more particularly to a microprocessor that realizes high-speed operation and low power consumption by controlling a substrate bias of a processor circuit constituted by MOS transistors in accordance with an operation mode of the processor.
[0002]
[Prior art]
Currently, CMOS integrated circuits are widely used to realize microprocessors. The power consumption of the CMOS circuit includes dynamic power consumption due to charging / discharging during switching and static power consumption due to leakage current. Of these, dynamic power consumption is proportional to the square of the power supply voltage Vdd and occupies a large amount of power consumption. Therefore, it is effective to lower the power supply voltage in order to reduce power consumption. The voltage is decreasing.
[0003]
Some current low power consumption type microprocessors include a power management mechanism, and a plurality of operation modes are provided in the processor, and the supply of the clock to the execution unit is stopped according to the operation mode accordingly. By stopping the clock supply, dynamic power consumption due to switching in unnecessary execution units can be reduced as much as possible. However, static power consumption due to leakage current cannot be reduced and remains.
[0004]
Since the operation speed of the CMOS circuit decreases as the power supply voltage decreases, it is necessary to decrease the threshold voltage of the MOS transistor in conjunction with the decrease of the power supply voltage in order to prevent the operation speed from deteriorating. However, when the threshold voltage is lowered, the leakage current increases drastically. Therefore, as the power supply voltage decreases, static power consumption increases due to leakage current, which has not been so large in the past. For this reason, there is a problem of realizing a microprocessor that achieves both high speed and low power consumption.
[0005]
Japanese Patent Laid-Open No. 6-53496 discloses a method for controlling the threshold voltage of a MOS transistor by variably setting a substrate bias as a method for solving problems relating to the operating speed and leakage current of the MOS transistor circuit.
[0006]
A device structure for variably setting the substrate bias will be described with reference to FIG. FIG. 2 is a cross-sectional view of a circuit having a CMOS structure. An n-well 205 is formed in a part of a surface layer of a p-well (p-type substrate) 201, and an n-well 205 is formed on the surface of the p-well 201. ⁺ An nMOS transistor comprising a source / drain region 202 of type, a gate oxide film 203 and a gate electrode 204 is formed. ⁺ A pMOS transistor including a source / drain region 206 of a type, a gate oxide film 207, and a gate electrode 208 is formed.
[0007]
Normally, the sources of the pMOS transistor and the nMOS transistor are connected to a power supply voltage (hereinafter referred to as Vdd) and a ground potential (hereinafter referred to as Vss), respectively, and the drains of the nMOS transistor and the pMOS transistor are connected to an output signal. As terminals for applying a substrate bias, Vbp 209 is provided in the n well 205 of the pMOS transistor, and Vbn 210 is provided in the p well 201 of the nMOS transistor.
[0008]
Using a device such as FIG. 2, Vbp 209 is normally connected to Vdd and Vbn 210 is connected to Vss. However, when the circuit is not operating, these substrate biases are switched so that Vbp 209 is at a higher potential and Vbn 210 is at a lower potential. By connecting, the threshold voltage of the MOS transistor can be increased and the leakage current can be reduced.
[Patent Document 1]
JP-A-6-53496
[0009]
[Problems to be solved by the invention]
In order to realize a microprocessor that achieves both high speed and low power consumption, the above-mentioned variable control of the substrate bias is performed on the processor circuit, and the threshold voltage of the MOS transistor is lowered during the operation of the processor. Therefore, it is necessary to maintain high speed and to reduce the leakage current by increasing the threshold voltage during standby. However, in order to variably control the substrate bias of the processor, the processor operation mode transition at the time of switching the substrate bias, in particular, the timing for restarting the processor at the transition from the standby state to the operation state is accurately controlled. Must be prevented from malfunctioning.
[0010]
An object of the present invention is to solve such problems and to provide a high-speed and low-power consumption processor by realizing the substrate bias control on a processor chip and applying it to various operation modes of the processor.
[0011]
[Means for Solving the Problems]
In order to solve the above problems, the processor of the present invention is characterized in that a processor main circuit that executes a program instruction sequence on a processor chip, a substrate bias switching device that switches a substrate bias voltage applied to the substrate, and a processor The substrate bias switching device is controlled to switch the bias to a voltage for standby mode in response to execution of an instruction to shift to the standby mode in the main circuit, and when the standby release interrupt is received from the outside, the bias is set for the normal mode. An operation mode control unit is provided that controls the substrate bias switching device so as to switch to a voltage, releases the standby state of the processor main circuit and restarts the operation after the switched bias voltage is stabilized.
[0012]
Another feature of the processor of the present invention is that the semiconductor device of the processor chip has a triple well structure, and the processor main circuit is formed on a different well region from the substrate bias switching device and the operation mode control unit. Is Rukoto.
[0013]
Another feature of the present invention is that the operation mode control unit is necessary for stabilizing the bias as means for waiting until the switched bias voltage is stabilized before restarting the operation of the processor main circuit at the time of switching the bias. An on-chip timer for measuring the passage of time or a sensor for detecting that the bias is stabilized at a predetermined voltage is provided.
[0014]
Another feature of the processor of the present invention is that the processor chip semiconductor device has a triple well structure and is divided into a plurality of functional modules, each of which is formed on a different well region. A circuit bias, a substrate bias switching device for switching a substrate bias applied to the substrate of each functional module, and a substrate bias of the functional module upon execution of an instruction to put one or more functional modules in the processor main circuit into standby The substrate bias switching device is controlled so as to switch the voltage to the voltage for the standby mode, and the substrate bias switching device is switched so that the bias is switched to the voltage for the normal mode when the standby release signal of the functional module is received from the external or the processor main circuit. Controlled and switched Bias voltage is to include a operation mode control unit for notifying that the standby function modules in the processor main circuit is released after the stable.
[0015]
The processor according to the present invention also includes means for dynamically switching the operation speed of the processor main circuit, and the substrate bias switching device in response to execution of an instruction to change the operation frequency in the processor main circuit. And an operation mode control unit for notifying that the switching of the operation speed is completed to the processor main circuit after the switched bias voltage is stabilized.
[0016]
Further, the processor of the present invention is characterized in that the substrate bias switching device is constituted by a substrate bias generation circuit that internally generates a substrate bias voltage.
[0017]
The present invention also proposes a control method that contributes to lower power consumption of the apparatus. That is, a transistor with a low threshold is high speed, but since the leakage current between the source and drain is large and the power consumption increases, it is important to prevent this.
[0018]
A configuration for this is a control method for controlling power consumption of a semiconductor integrated circuit device having a plurality of element circuit blocks which have transistors formed on a semiconductor substrate and operate based on a clock signal. The first mode in which all of the above operate based on the clock, the second mode in which the supply of the clock signal to at least one of the element circuit blocks is stopped, and the supply of the clock signal to all of the element circuit blocks is stopped. In addition, a third mode in which the substrate bias of at least a part of the transistors formed on the semiconductor substrate is controlled to increase the threshold value of the transistors is switched and used.
[0019]
The main circuit is, for example, a processor including a CPU. The first mode is a mode in which the main circuit performs a normal operation (calculation, storage, etc.).
[0020]
The second mode is a state in which the clock to a part of the processor is stopped, and is called, for example, a sleep mode or a deep sleep mode. By selecting a range in which the clock is stopped, low power consumption can be achieved while maintaining only necessary functions.
[0021]
The third mode is a mode in which the substrate bias is controlled with respect to the processor circuit, the threshold value of the transistors constituting the processor circuit is increased, and the power consumption due to the subthreshold leakage current is reduced. This is called a standby mode. The standby mode can be restored to the normal state by interrupt control, but cannot be restored unless reset is performed in the hardware standby mode. In the third mode, the function of the main circuit is stopped.
[0022]
As a configuration of the entire circuit, the element circuit block is included in the first circuit block, the clock signal is formed by the oscillation circuit included in the second circuit block, and the clock is transferred from the second circuit block to the first circuit block. A signal and an information signal to be processed by the first circuit block are input. In addition, the second circuit block includes a control circuit for controlling the input / output circuit and the substrate bias. Normally, the second circuit block is not required to operate as fast as the first circuit block including the main circuit. Therefore, it is desirable that the transistors constituting the second circuit block have a larger threshold value and higher operating voltage than the transistors constituting the first circuit block. Further, the transistor constituting the main circuit of the first circuit block is formed on a well separate from other circuits, so that the influence of the other circuits can be reduced.
[0023]
When the operating voltages of the first and second circuit blocks are different, a level conversion circuit is required between them. For example, a level down circuit is provided in the first circuit block, and a level up circuit is provided in the second circuit block to perform signal level conversion.
[0024]
In the present invention, since the substrate bias voltage is dynamically switched by switching modes, the operation sequence is important for ensuring reliability.
[0025]
When switching from the first or second mode to the third mode, the clock signal input from the second circuit block to the first circuit block or the first circuit block is processed to be processed by the first circuit block. First, the information signal input to the circuit block is stopped, and then the substrate bias of at least part of the transistors formed on the semiconductor substrate is controlled to increase the threshold value of the transistors. As a result, input to the first circuit block when the operation of the first circuit block is unstable can be prevented, and malfunction of the first circuit block can be prevented.
[0026]
For this operation, it is possible to adopt a configuration in which the signal input to the first circuit block is stopped, the substrate bias is controlled after waiting for a predetermined time (for example, about 60 microseconds) by a timer or the like. The timer for waiting is arranged outside the first circuit block, for example, in the second circuit block or outside the apparatus.
[0027]
Also, when switching from the third mode (standby mode) to the first mode, the substrate bias of the transistor formed on the semiconductor substrate is controlled to lower the threshold value of the transistor, The input of the clock signal input to the first circuit block from the second circuit block and the information signal to be processed by the first circuit block is started. That is, in order to prevent malfunction of the first circuit block, signal input is started after the substrate voltage of the first circuit block is stabilized.
[0028]
For this reason, when switching from the third mode to the first mode, the substrate bias of the first circuit block is controlled to lower the threshold value of the transistor, and the timer waits for a predetermined time to stabilize the operation. After that, input of a clock signal and other signals input to the first circuit block is started.
[0029]
As another method, after the state of the threshold value of the transistor is confirmed by a voltage monitor or the like, signal input to the first circuit block is started. Alternatively, on the basis of the state of the substrate bias generation circuit that controls the substrate voltage, the input of the clock signal and other signals input to the first circuit block is started in accordance with the signal indicating the standby release output from the substrate bias generation circuit To do.
[0030]
As a method of stopping the information signal and the clock signal for the first block, it is conceivable to fix the signal level by an output fixing circuit (level hold circuit) provided in the second circuit block. In the first mode, the signal is input to the level down circuit via the output fixing circuit, but in the third mode, the input to the level down circuit is fixed.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0032]
FIG. 1 is a block diagram showing a configuration example of a processor chip for realizing the first embodiment of the present invention. In FIG. 1, a processor chip 101 is an LSI chip having a CMOS structure circuit, and includes a processor main circuit 102, an operation mode control unit 103, and a substrate bias switching device 104. The substrate bias switching device 104 is supplied with the voltages Vdd and Vss in the normal mode of the substrate bias and the voltages Vddb and Vssb in the standby mode from the signal 110. The substrate bias switching device 104 selects either Vdd or Vdb as the substrate bias of the pMOS transistor constituting the processor main circuit 102 in accordance with the signal 107 output from the operation mode control unit, and outputs it to the signal Vbp111, and the substrate of the nMOS transistor Either Vss or Vssb is selected as a bias and output to the signal Vbn112. The substrate bias selection voltage values are, for example, Vdd = 1.5V, Vddb = 3.0V, Vss = 0.0V, and Vssb = −1.5V.
[0033]
As will be described later, the well 302 in which the processor main circuit 102 is formed is formed independently of the well in which the substrate bias switching device 104 and the operation mode control unit are formed.
[0034]
FIG. 3 is a cross-sectional view showing the device structure of the processor chip 101. 3 is different from FIG. 2 in that a p-well 302 is formed on an n-type substrate 301 and an n-well 205 is formed in a part of the surface phase thereof, that is, a device having a triple well structure. is there. An nMOS transistor is formed on the surface of the p-well 302, and a pMOS transistor is formed on the surface of the n-well 205 to constitute a CMOS circuit. Further, as in FIG. 2, Vbp 209 is provided in the n well 205 of the pMOS transistor and Vbn 210 is provided in the p well 302 of the nMOS transistor as terminals for applying the substrate bias. In this embodiment, the processor main circuit 102 is formed in a p well 302 different from the operation mode control unit 103 and the substrate bias switching device 104. Thereby, the influence of the substrate bias control affects only the processor main circuit 102, and the operation mode control unit 103 and the substrate bias switching device 104 can avoid the influence.
[0035]
The operation of the processor chip 101 in this embodiment will be described with reference to FIG. The operation modes of the processor main circuit 102 include a normal mode for executing normal instructions and a standby mode for not executing instructions. FIG. 4 is a flowchart showing processing on the processor chip 101 when the operation mode of the processor main circuit 102 transitions from the normal mode to the standby mode and from the standby mode to the normal mode.
[0036]
First, the processor main circuit 102 operates in the normal mode. At this time, the substrate bias switching device 104 selects Vdd and Vss for the substrate biases Vbp111 and Vbn112, respectively. The voltage values of the substrate bias in the normal mode in this example are Vbp = 1.5V and Vbn = 0V (step 401).
[0037]
When executing the sleep command, the processor main circuit 102 outputs a “standby request” to the signal 105 and transmits it to the operation mode control unit 103, and then stops the command execution operation and shifts to the standby mode (step 402).
[0038]
When the operation mode control unit 103 receives the signal 105 from the processor main circuit, the operation mode control unit 103 outputs a signal 107 to switch the substrate bias of the processor main circuit 102 to the voltage for the standby mode. The substrate bias switching device 104 receives this signal 107 and selects and outputs Vddb and Vssb from the input voltage 110 to the substrate biases Vbp 111 and Vbn 112, respectively (steps 403 and 404). In this example, the substrate bias voltage values in the standby mode are Vbp = 3.0V and Vbn = −1.5V.
[0039]
When the operation mode control unit 103 detects that the “standby release interrupt” is asserted to the signal 108 from the outside when the processor main circuit 102 is in the standby state (step 405), the operation mode control unit 103 sets the substrate bias of the processor main circuit 102. The signal 107 is output to switch to the voltage for the normal mode, and the substrate bias switching device 104 receives this signal 107 and switches the substrate biases Vbp111 and Vbn112 to Vdd (1.5 V) and Vss (0.0 V), respectively. (Step 406).
[0040]
Since it takes some time for the bias voltage to stabilize after the substrate bias is switched, there is a possibility of malfunction if the operation of the processor main circuit 102 is restarted immediately. To avoid this, the operation mode control unit 103 sets and starts a sufficient time necessary for stabilizing the substrate bias voltage switched to the on-chip timer 109 before switching the operation mode of the processor main circuit 102 (step 407). The process waits until timeout (step 408). After the time-out, the operation mode control unit 103 outputs “standby release” to the signal 106 and transmits it to the processor main circuit 102. Upon receiving this signal 106, the processor main circuit 102 shifts to the normal mode and resumes the instruction execution operation (step 409).
[0041]
As described above, the substrate biases Vbp111 and Vbn112 of the processor main circuit 102 are controlled so that the threshold voltage of the MOS transistor constituting the processor main circuit is lowered during operation to cope with high-speed operation, and the threshold is set during standby. The leakage current can be reduced by increasing the value voltage.
[0042]
FIG. 5 is a block diagram showing the configuration of the processor chip in the second embodiment of the present invention. In this embodiment, the operation mode control unit 103 includes a sensor 501 that detects a bias voltage applied to the substrate of the processor main circuit 102. When the operation mode of the processor main circuit 102 transitions from the normal mode to the standby mode, the processing procedure in the first embodiment is the same. When the operation mode of the processor main circuit 102 transitions from the standby mode to the normal mode, the operation mode control unit 103 controls the substrate bias switching device 104 to change the substrate bias to the normal mode voltage as in the first embodiment. After switching, the sensor 501 waits until the substrate bias voltage switched to a predetermined value, that is, Vbp = 1.5 V and Vbn = 0.0 V in this embodiment is output to the signal 502. When the sensor 501 outputs the stability of the substrate bias to the signal 502, the operation mode control unit 103 outputs “standby release” to the signal 106 and resumes the operation of the processor main circuit 102.
[0043]
FIG. 6 is a block diagram showing the configuration of the processor chip in the third embodiment of the present invention. As a basic device structure of the processor chip 601, the triple well structure shown in FIG. 3 is considered. In the processor chip 601 of FIG. 6, the processor main circuit is composed of a plurality of functional modules such as a CPU 604, a module A 606, and a module B 608. Each function module exists separately on a different well region and is not affected by the substrate bias control of other function modules. The functional module includes a smaller unit such as a CPU, FPU, cache, or arithmetic unit. Substrate bias switching devices 605, 607, and 609 are provided corresponding to the respective functional modules 604, 606, and 608, and the substrate biases of the corresponding functional modules can be switched in the same manner as in the above embodiment. The execution of the instruction is performed mainly by the CPU 604, which is one of the functional modules. When an instruction for setting a functional module unnecessary for execution is executed, the operation mode control unit 602 is notified of the standby of the functional module.
[0044]
Next, the operation of the processor chip 601 in this embodiment will be described. First, assume that all functional modules are operating in normal mode. When the CPU 604 executes an instruction to set the module A to the standby state, the CPU 604 outputs this standby request to the signal 610, and thereafter, the module cannot be used until the standby of the module A 606 is released. The operation mode control unit 602 receives this signal 610, outputs a signal 612 to the substrate bias switching device 607, and switches the substrate bias of the module A 606 to the voltage for the standby mode. When the module A 606 is in the standby state, the operation mode control unit 602 receives the signal 612 from the output signal 610 of the CPU 604 or the signal for releasing the module A 606 from the signal 613 external to the processor chip 601, and outputs the signal 612 to the substrate bias switching device 607. And the substrate bias of the module A is switched to the voltage for the normal mode. Then, the operation mode control unit 602 waits for the stabilization of the substrate bias switched using the on-chip timer 603 as in the first embodiment of the present invention, and after the stabilization, the standby of the module A is released through the signal 611 to the CPU 604. To be notified. Upon receiving this signal 611, the CPU 604 can execute an instruction using the module A.
[0045]
The same applies to the standby control of the module B608 and other functional modules. Further, the CPU 604 itself is a target of standby control. In this case, when the CPU 604 shifts to the standby mode, execution of all instructions is stopped. When the signal for canceling the standby of the CPU 604 is asserted to the external signal 613, the operation mode control unit 602 signals after the switching of the substrate bias of the CPU 604 is completed. The control is the same as in the case of the module A606 except that the CPU 604 is de-asserted to 611 and the instruction execution of the CPU 604 is resumed.
[0046]
According to the standby control for each functional module in the present embodiment, it is possible to reduce the leakage current of the functional module that is unnecessary during the operation of the processor.
[0047]
FIG. 7 is a block diagram showing the configuration of the processor chip in the fourth embodiment of the present invention. The difference from the first embodiment is that the types of voltages 701 supplied to the substrate bias switching device 104 from the outside are increasing, and the substrate bias switching device 104 selects an appropriate one as the substrate bias from these, and the processor It can be applied to the main circuit 102. In this embodiment, it is assumed that the operation speed of the processor main circuit 102, that is, the operation frequency is provided with means for dynamically changing according to an instruction, and the operation mode of the processor main circuit 102 includes a high speed mode and a low speed mode. In this embodiment, Vdd (for pMOS) and Vss (for nMOS) as substrate biases corresponding to the high speed mode, Vddb2 (for pMOS) and Vssb2 (for nMOS) as substrate biases corresponding to the low speed mode, and standby mode are supported. Vddb1 (for pMOS) and Vssb1 (for nMOS) are selected as the substrate bias.
[0048]
Next, the operation of the processor chip 101 in this embodiment will be described. Here, consider a case where the operation mode of the processor main circuit 102 is switched from the high speed mode to the low speed mode. While the processor main circuit 102 is operating in the high-speed mode, the substrate bias switching device 104 selects Vdd for Vbp 111 and Vss for Vbn 112 as the substrate bias of the processor main circuit. When the processor main circuit 102 executes the instruction to shift to the low speed mode, it outputs the request to the signal 105 and interrupts the instruction execution operation. The clock supplied to the processor main circuit 102 is switched to a low frequency by the execution of an instruction for shifting to the low speed mode. The operation mode control unit 103 receives the signal 105 and outputs it to the signal 107 to switch the substrate bias of the processor main circuit 102 to the voltage for the low speed mode. The substrate bias switching device 104 receives this signal 107 and switches the substrate biases Vbp111 and Vbn112 to Vddb2 and Vssb2, respectively. The operation mode control unit 103 uses the on-chip timer 109 in the same manner as in the above-described embodiment, waits for the stability of the switched substrate bias, and notifies the processor main circuit 102 through the signal 106 that the transition to the low-speed mode is completed. The processor main circuit 102 receives the signal 106 and restarts the interrupted instruction execution operation in the low speed mode.
[0049]
The operation at the time of switching from the low-speed mode to the high-speed mode, switching from the high-speed mode or the low-speed mode to the standby mode, or switching from the standby mode to the high-speed mode or the low-speed mode in the present embodiment is the same as described above, and the details are omitted. To do. In this embodiment, it is possible to further subdivide the operation speed and perform substrate bias control corresponding thereto. Further, as in the third embodiment, the processor main circuit 102 is separated for each functional module using a device triple well structure, and the substrate bias is controlled in conjunction with switching of the operating frequency for each functional module. It is also possible.
[0050]
By performing the substrate bias control suitable for the operating frequency of the processor as in this embodiment, it is possible to reduce the leakage current in the low-speed operation mode. Further, in this low-speed mode, the input voltage range in which both the pMOS and nMOS transistors of the CMOS circuit are simultaneously turned on becomes narrower than in the high-speed operation mode, so that an effect of reducing the through current at the time of switching can be obtained. .
[0051]
FIG. 8 is a block diagram showing the configuration of the processor chip in the fifth embodiment of the present invention. This embodiment differs from the first embodiment in that the substrate bias switching device is constituted by a substrate bias generation circuit 801. The substrate bias generation circuit 801 is controlled by the output signal 802 of the operation mode control unit 103 to generate a substrate bias voltage and output it to Vbp 111 and Vbn 112. The voltage values of the substrate biases Vbp111 and Vbn112 generated corresponding to the operation mode of the processor main circuit 102 under the control of the operation mode control unit 103 are the same as those in the first embodiment. Since the operations of the processor main circuit 102 and the operation mode control unit 103 are the same as those in the first embodiment, the details are omitted. Similarly to the present embodiment, the substrate bias switching device in the second, third and fourth embodiments is configured by this substrate bias generation circuit 801, so that the substrate bias is generated inside the processor chip, and the operation mode Can be switched according to
[0052]
As described above, according to these embodiments, the timing at which the processor is restarted at the time of transition from the standby state to the operating state is accurately controlled using a timer or a sensor. Substrate bias control becomes possible. Thereby, the leakage current can be reduced in the standby mode while maintaining the high speed in the operation mode of the processor in the normal mode. Further, by performing the substrate bias control according to the operation mode for each functional module, it is possible to reduce the leakage current of the functional module unnecessary for execution even when the processor is operating. Furthermore, by performing substrate bias control suitable for the operating frequency of the processor, in addition to reducing the leakage current in the low-speed mode, the effect of reducing the through current during switching can be obtained.
[0053]
As a result, power consumption can be effectively reduced, and a microprocessor having both high speed and low power can be provided.
[0054]
Hereinafter, as an embodiment of the microcomputer, an operation mode for specifically controlling the substrate bias will be described. The microcomputer has two power supplies of 1.8V and 3.3V, and performs substrate bias control only for 1.8V. It is desirable that the circuit supplying 1.8V is composed of a MOS transistor having a relatively low threshold (for example, Vth <0.4V).
[0055]
FIG. 9 shows an example of the operation mode of the microcomputer. As operation modes, there are a normal operation mode 982 in which the operation is normally performed and a reset mode 981. Modes operating with low power consumption include sleep 983, deep sleep 984, standby 985, hardware standby 986, and RTC (real-time clock) battery backup mode. As a test mode, there is IDDQ measurement.
[0056]
In the normal operation 982, since a high-speed operation is necessary, the substrate bias is not controlled. At the time of reset 981, since all functions need to be reset, the substrate bias is not controlled. In the low power consumption mode, the sleep bias 983 and the deep sleep 984 that have a short recovery time from the low power consumption mode do not control the substrate bias, but the standby 985 focuses on making the power consumption smaller than the recovery time. In the case of the hardware standby 986, substrate bias control is performed. The RTC battery backup mode is a mode in which only the power supply of the RTC circuit operating at 3.3V is supplied. Since this mode is shifted from the low power consumption mode, substrate bias control is performed. The IDDQ measurement is a mode in which a standby current is measured and a through current due to a short circuit or failure of a transistor is measured. In this case, the substrate bias is always controlled to reduce the leakage power of the chip. Need to make it easier to find defects.
[0057]
Before describing the low power consumption operation mode with reference to FIG. 10, the configuration of the internal blocks of the processor main circuit 902 will be described. This figure is an example of main constituent blocks of the processor main circuit. Arithmetic circuits include a CPU (central processing unit) 971 and an FPU (floating point arithmetic unit) 972. In addition, a cache 973 that is a memory built in the chip, a BSC (bus control unit) 974 that interfaces with an external memory, a DMAC (DMA control unit) 975 that performs DMA (direct memory access), and an SCI that controls a serial port (SCI) A serial control unit) 976, an INTC (interrupt control unit) 977 for controlling an interrupt input, a CPG (clock control unit) 978 for controlling a clock, and the like.
[0058]
The sleep 983, deep sleep 984, and standby 985, which are low power consumption modes, will be described with reference to FIG.
[0059]
In the sleep 983, only the clocks of the arithmetic units such as the CPU 971, the FPU 972, the cache 973, etc. are stopped, and the substrate bias control is not performed. DRAM (dynamic RAM) and SDRAM (synchronous dynamic RAM) normal refresh (1024 times / 16 milliseconds refresh) is possible. Since the CPG 978 is operating and the substrate bias control is not performed, the return time from the sleep 983 to the normal operation mode 982 is fast.
[0060]
In the standby 985 mode, all the operation clocks are stopped and the substrate bias control is also performed, so that the power consumption is extremely small. DMA transfer is not possible because the clock is stopped. Regarding refresh of DRAM or SDRAM, before entering standby 985, control signals (RAS signal, CAS signal) of each memory are set using BSC 974 so that the memory is in a self-refresh mode in which it refreshes itself. It is necessary to keep it. However, the recovery time from the standby 985 to the normal operation 982 becomes longer due to the waiting time for stabilization of clock oscillation and the recovery time from the substrate bias state because the clock is stopped.
[0061]
The deep sleep 984 mode is a low power consumption mode between the sleep 983 and the standby 985.
[0062]
FIG. 12 shows the difference between the operation modules of the sleep 983 and the deep sleep 984. At the sleep 983, the operating BSC 973, DMAC 974, and SCI 975 are stopped in the deep sleep 984, so that power consumption can be reduced accordingly.
[0063]
However, in the deep sleep 984 mode, DMA transfer cannot be performed, and the memory refresh is also self-refreshing. The return time from the deep sleep 984 to the normal operation mode 982 is as fast as the sleep mode.
[0064]
Thus, by providing three types of low power consumption modes, fine low power consumption control according to the application can be performed.
[0065]
The operation mode state transition diagram will be described with reference to FIG. The processor chip transitions to the reset state 981 by RESET # 952 (or power-on reset) pin input from all power off states 980. When RESET # 952 is negated, the operation transits to the normal operation 982. Transition from this state to the low-consumption operation mode.
[0066]
There are two transition methods. One is a transition by an instruction. This transition is made when the CPU 971 executes a sleep command. A sleep mode 983, a deep sleep 984, and a standby 985 can be selected by setting a mode register at the time of execution of a sleep command, and each mode can be changed. The return from each mode to the normal operation mode 982 is an interrupt 958.
[0067]
Another transition method is a transition by the HARDSTB # 951 pin. When this pin is asserted, it transitions to the hardware standby state 986. This state is a state in which all the clocks are stopped and the substrate bias control is performed as in the standby 985.
[0068]
In this mode, if the input / output buffer is set to high impedance, the 3.3V circuit also has no through current flowing transistor, and IDDQ can be measured.
[0069]
If the input buffer of the RTC circuit placed in the 3.3V system is fixed, the input signal of the RTC circuit will not float (intermediate level) even when the power supply other than the RTC circuit is turned off. Malfunctions can be prevented and only the RTC circuit can be operated.
[0070]
Next, an application example of hardware standby will be described.
[0071]
FIG. 14 shows a configuration of a processor chip 901 and a configuration of a power supply control circuit that can replace the power supply 904 (battery) of the processor chip 901 by applying a hardware standby.
[0072]
The processor chip 901 includes a 1.8V area circuit 930 that operates at 1.8V and a 3.3V area circuit 931 that operates at 3.3V. The 1.8V area circuit 930 includes a processor main circuit 902 and level down circuits 905 and 906 for level conversion from 3.3V to 1.8V. The circuit 931 in the 3.3V region includes a substrate bias generation circuit 903, a clock oscillation circuit 908, an IO circuit 909, an operation mode control unit 913, an RTC circuit 914, and level-up circuits 904 and 910 for converting the level from 1.8V to 3.3V. It is composed of output fixing circuits 907 and 911 for fixing a signal from 3.3V to 1.8V.
[0073]
As a power supply system control circuit, there are a power supply 904, a power supply monitoring circuit 921, a display 922, and a voltage generation circuit 920 that generates a 1.8V system voltage.
[0074]
The operation will be described below. When the processor chip 901 is in the normal operation mode 982, the substrate bias generation circuit 903 holds a normal substrate level (for example, VDD potential for PMOS and VSS potential for NMOS) without pulling the substrate bias. The clock oscillation circuit 908 is composed of a PLL (phase locked loop) or the like, generates a clock for internal operation, and sends it to the processor main circuit 902 via the output fixing circuit 907 and the level down circuit 905. The IO circuit 909 takes in an external signal and sends it to the processor main circuit 902 via the output fixing circuit 907 and the level down circuit 905. Further, a signal from the processor main circuit 902 is output to the outside via the level-up circuit 904. The RTC circuit 914 operates at 3.3 V, receives a control signal from the processor main circuit 902 via the level-up circuit 910, and transmits a control signal to the processor main circuit 902 via the level-down circuit 906 and the output fixing circuit 911. Send. The operation mode control unit 913 particularly controls the substrate bias generation circuit 903.
[0075]
The power monitoring circuit 921 monitors the voltage level of the power source 904. When the voltage level falls below a predetermined level (detects a state where the battery is dead), HARDSTB # 951 is set to a low level. At the same time, a battery low alarm is displayed on the display 922 to inform the user. Even when the voltage level is lowered, the voltage holding circuit 923 can hold the voltage level for a predetermined period (several minutes to several hours). During this period, the user can replace the power supply 904.
[0076]
Hereinafter, the power supply replacement sequence will be described with reference to FIG.
(1) When HARDSTB # 951 goes low, the operation mode enters the hardware standby state 986. Here, a 1.8V signal fixing 953 is output from the operation mode control unit 913, a signal from 3.3V to 1.8V is fixed, and the 1.8V system clock is also stopped. As a result, even when the substrate bias is pulled, the 1.8 V system signal does not operate, so the substrate bias is pulled (the threshold voltage of the MOS transistor is high, and the operation speed is slow). Thus, a malfunction of the 1.8V system circuit in a state where the substrate potential is unstable is prevented. In this state, a substrate bias control start signal 955 is output to the substrate bias generation circuit 903.
(2) Thereafter, a substrate bias control start signal 955 is output to the substrate bias generation circuit 903 based on the timing of the 1.8V signal fixing 953. Between the signal fixing 953 and the substrate bias control start 955, a time difference is set until the signal is actually fixed and the supply of the signal to the 1.8 V region is stopped. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914.
(3) In response to the substrate bias control start signal 955, the substrate bias generation circuit 903 starts to pull the substrate bias of the 1.8V substrate. During the period when the substrate bias is being pulled, the 956 signal during substrate bias control is returned to the operation mode control unit 913.
(4) The processor main circuit 902 does not operate when the substrate bias is being pulled. Further, since the leakage current is small, the current consumption is small. As a result, the holding time of the voltage holding circuit 923 also becomes longer.
(5) Replace the power supply 904 in this state.
(6) After replacing the power supply, the power supply voltage returns to a normal level, so that HARDSTB # 951 returns to a high level.
(7) Thereafter, the power-on reset circuit operates and RESET # 952 is input. By this reset input, the substrate bias control start signal 955 output from the operation mode control unit 913 is canceled.
(8) In response to the release of the substrate bias control start signal 955, the substrate bias generation circuit 903 changes the substrate bias of the 1.8V system substrate to the operating state potential (for example, VDD potential for PMOS and VSS potential for NMOS). Start returning. A predetermined time is required until the substrate bias is recovered, and when the substrate bias is returned, the operation mode control unit 913 is notified of this by releasing the substrate bias control signal 956.
(9) Upon receiving the cancellation of the substrate bias control signal 956, the 1.8V signal fixing 953 output from the operation mode control unit 913 is canceled, and a signal is sent to a 1.8V system circuit such as the processor main circuit 902. Entered.
(10) After the reset state 981 ends, the normal state 982 is entered and the processor main circuit 902 starts normal operation.
[0077]
As described above, the power supply 904 can be replaced using the low power consumption mode by the hardware standby.
[0078]
Next, a second application example of hardware standby will be described.
[0079]
FIG. 16 shows a configuration example for realizing the RTC power backup mode. The RTC circuit 914 is called a real-time counter, and realizes a clock and calendar function. For this reason, the function of the watch cannot be realized unless it is always operating. Even when the power supply 904 is cut off, the RTC circuit 914 needs to be operating.
[0080]
In the embodiment shown here, the 3.3V region is divided into a normal 3.3V region 991 and a region 992 operating at 3.3V of the RTC in order to realize the RTC power supply backup mode. In the 3.3 V region 992 of the RTC, an input fixing circuit 912 and an input fixing level-up circuit 960 are added to the input circuit, and other power sources (1.8 V, normal 3.3 V power source) are cut off. In this state, even if the input signal becomes floating, an intermediate level signal is not transmitted to the region 992 that operates at 3.3 V of the RTC to prevent malfunction.
[0081]
As a power supply system control circuit, there are a backup battery 962 and diodes 963 and 964, in addition to a power supply 904, a power supply monitoring circuit 921, a display 922, and a voltage generation circuit 920 that generates a 1.8V system voltage.
[0082]
The operation will be described below. In the normal operation mode 982, the substrate bias generation circuit 903 maintains the normal substrate level without pulling the substrate bias. The clock oscillation circuit 908 is composed of a PLL (phase locked loop) or the like, generates a clock for internal operation, and sends it to the processor main circuit 902 via the output fixing circuit 907 and the level down circuit 905. The IO circuit 909 takes in a signal from outside and sends it to the processor main circuit 902 via the output fixing circuit 907 and the level down circuit 905. Further, a signal from the processor main circuit 902 is output to the outside via the level-up circuit 904. The RTC circuit 914 operates at 3.3 V, receives a control signal from the processor main circuit 902 via the input fixed level-up circuit 960, and controls the processor main circuit 902 via the level-down circuit 906 and the output fixing circuit 911. Send a signal. The operation mode control unit 913 receives a control signal via the input fixing circuit 912 and controls the substrate bias generation circuit 903 in particular.
[0083]
The power monitoring circuit 921 monitors the voltage level of the power source 904. When the voltage level falls below a predetermined level (detects a state where the battery is dead), HARDSTB # 951 is set to a low level, the input of the RTC 3.3V region 992 is fixed, and malfunction of the RTC circuit 914 is prevented. At the same time, a battery low alarm is displayed on the display 922. Thereafter, the voltage level continues to decrease, and 3.3V and 1.8V voltages are not supplied to the processor chip 901. At this time, the voltage (VDD-RTC, VSS-RTC) is supplied only from the backup battery 962 to the 3.3 V region of the RTC via the diode 963, and even without the power supply 904, only the RTC circuit 914 (calendar counter circuit) is provided. Works normally. The diode 964 prevents current from flowing to other than the RTC circuit 914.
[0084]
The RTC power supply backup sequence will be described in detail with reference to FIG.
(1) When HARDSTB # 951 goes low, the operation mode enters the hardware standby state 986. Here, a 1.8V signal fixing 953 is output from the operation mode control unit 913, a signal from 3.3V to 1.8V is fixed, and the 1.8V system clock is also stopped. As a result, even when the substrate bias is pulled, the 1.8V signal does not operate, so that the malfunction of the 1.8V circuit with the substrate bias being pulled is prevented. At the same time, an input fixing signal 954 to the RTC circuit 914 is output to fix the input signal. This prevents an unstable intermediate level signal from entering the RTC circuit 914 when the other power supply is shut off.
(2) Thereafter, a substrate bias control start signal 955 is output to the substrate bias generation circuit 903 based on the timing of the 1.8V signal fixing 953. Between the signal fixing 953 and the substrate bias control start 955, a time difference is set until the signal is actually fixed and the supply of the signal to the 1.8 V region is stopped. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914.
(3) In response to the substrate bias control start signal 955, the substrate bias generation circuit 903 starts to pull the substrate bias of the 1.8V substrate. During the period when the substrate bias is being pulled, the 956 signal during substrate bias control is returned to the operation mode control unit 913.
(4) The processor main circuit 902 does not operate when the substrate bias is being pulled. Further, since the leakage current is small, the current consumption is small.
(5) The interruption period of the power supply 904 may be long. Further, the power source 904 can be replaced.
(6) After the power supply 904 is shut off (or after the power supply 904 is replaced), the power supply voltage returns to the normal level, so that HARDSTB # 951 returns to the high level.
(7) Thereafter, the power-on reset circuit operates and RESET # 952 is input. The substrate bias control start signal 955 is canceled by this reset input.
(8) In response to the release of the substrate bias control start signal 955, the substrate bias generation circuit 903 changes the substrate bias of the 1.8V system substrate to the operating state potential (for example, VDD potential for PMOS and VSS potential for NMOS). Start returning. A predetermined time is required until the substrate bias is recovered, and when the substrate bias is returned, the operation mode control unit 913 is notified of this by releasing the substrate bias control signal 956.
(9) Upon receiving the cancellation of the substrate bias control signal 956, the 1.8V signal fixing 953 output from the operation mode control unit 913 is canceled, and a signal is sent to a 1.8V system circuit such as the processor main circuit 902. Entered.
(10) After the reset state 981 ends, the normal state 982 is entered and the processor main circuit 902 starts normal operation.
[0085]
In the above sequence, it is also possible to provide a power switch for the power supply 904 and operate only the RTC circuit 914 during the power-off period.
[0086]
As described above, only the RTC circuit 914 can be operated with battery backup using the hardware standby.
[0087]
FIG. 18 illustrates a sequence for entering the standby state 985 using the normal sleep instruction 959 and returning to the normal state 982 with the interrupt signal 958.
(1) The sleep mode 959 causes the operation mode to enter the standby state 985. Here, a 1.8V signal fixing 953 is output from the operation mode control unit 913, a signal from 3.3V to 1.8V is fixed, and the 1.8V system clock is also stopped. This prevents a malfunction of the 1.8V circuit when the substrate bias is pulled.
(2) Thereafter, a substrate bias control start signal 955 is output to the substrate bias generation circuit 903 based on the timing of the 1.8V signal fixing 953. Between the signal fixing 953 and the substrate bias control start 955, a time difference is set until the signal is actually fixed and the supply of the signal to the 1.8 V region is stopped. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914.
(3) In response to the substrate bias control start signal 955, the substrate bias generation circuit 903 starts to pull the substrate bias of the 1.8V substrate. During the period when the substrate bias is being pulled, the 956 signal during substrate bias control is returned to the operation mode control unit 913.
(4) The processor main circuit 902 does not operate when the substrate bias is being pulled. Further, since the leakage current is small, the current consumption is small.
(5) In this state, when the interrupt signal 958 is received from the control signal 957 (external pin) via the IO circuit 909, the operation mode control unit 913 releases the substrate bias control start signal 955.
(6) In response to the cancellation of the substrate bias control start signal 955, the substrate bias generation circuit 903 changes the substrate bias of the 1.8V system substrate to the operating state potential (for example, VDD potential for PMOS and VSS potential for NMOS). Start returning. A predetermined time is required until the substrate bias is recovered, and when the substrate bias is returned, the operation mode control unit 913 is notified of this by releasing the substrate bias control signal 956.
(7) Upon receiving the cancellation of the substrate bias controlling signal 956, the operation mode control unit 913 releases the 1.8V signal fixing 953. By canceling the 1.8V signal fixing 953 after the substrate bias control signal is canceled, the 1.8V circuit is prevented from malfunctioning.
(5) A signal is input to a 1.8V system circuit such as the processor main circuit 902 and the normal state 982 is entered, and the processor main circuit 902 starts normal operation.
[0088]
As described above, the processor chip 901 enters the low power consumption mode and can be restored by an interrupt.
[0089]
FIG. 19 illustrates a sequence in which the normal sleep instruction 959 is used to enter the standby state 985 and return to the normal state 982 by RESET # 952.
(1) The sleep mode 959 causes the operation mode to enter the standby state 985. Here, a 1.8V signal fixing 953 is output from the operation mode control unit 913, a signal from 3.3V to 1.8V is fixed, and the 1.8V system clock is also stopped. This prevents a malfunction of the 1.8V circuit when the substrate bias is pulled.
[0090]
Thereafter, the 1.8 V signal fixing 953 measures the completion of signal fixing, and outputs a substrate bias control start signal 955 to the substrate bias generating circuit 903.
(2) In response to the substrate bias control start signal 955, the substrate bias generation circuit 903 starts pulling the substrate bias of the 1.8V system substrate. During the period when the substrate bias is being pulled, the 956 signal during substrate bias control is returned to the operation mode control unit 913.
(3) The processor main circuit 902 does not operate when the substrate bias is being pulled. Further, since the leakage current is small, the current consumption is small.
(4) In this state, the operation mode control unit 913 receives RESET # 952 and cancels the substrate bias control start signal 955.
(5) In response to the cancellation of the substrate bias control start signal 955, the substrate bias generation circuit 903 starts returning the substrate bias of the 1.8V substrate to the operating potential. When the substrate bias is returned, the operation mode control unit 913 is notified using the substrate bias control signal 956.
(6) Upon receiving this release signal, the 1.8V signal fixing 953 is released.
(7) After the reset state 981 is completed, a signal is input to a 1.8V system circuit such as the processor main circuit 902, the normal state 982 is entered, and the processor main circuit 902 starts normal operation.
[0091]
As described above, the processor chip 901 enters the low power consumption mode and can be restored by reset.
[0092]
As described above, the processor chip 901 has a portion where 1.8V is supplied as the power supply voltage and a portion where 3.3V is supplied as the power supply voltage. An example of the portion to which 1.8V is supplied includes a processor main circuit 902. This part has a large circuit scale and is required to be operated at a higher speed. Since the circuit scale is large and high-speed operation is required, the power consumption of this portion increases. In this embodiment, the power supply voltage is lowered to reduce this power consumption.
[0093]
Further, when the power supply voltage is lowered (for example, 1.8 V), the operation speed is reduced, so that the threshold voltage of the MOS transistor is lowered (for example, about Vth <0.4 V). Further, in this embodiment, the substrate voltage is controlled in order to reduce the subthreshold leakage current due to the low threshold value.
[0094]
On the other hand, a portion to which 3.3V is supplied as a power supply voltage is, for example, an RTC circuit 914. Since these circuits are small and operate at low speed, power consumption is small. Therefore, such a circuit block does not need to have a low power supply voltage. For example, Vth> 0.5V can be set. Since it is not necessary to lower the threshold value of the MOS transistor, there is an advantage that there is no need for current countermeasures by substrate control in order to reduce the subthreshold leakage current.
[0095]
The processor chip 901 of this embodiment uses both power supply voltages properly. That is, a portion requiring a large-scale high-speed operation uses a low voltage low threshold MOS under substrate control, and uses a high voltage high threshold MOS without substrate control. A method for manufacturing MOS transistors having different threshold values is not particularly limited, but can be realized by changing the channel implantation amount. It can also be realized by changing the thickness of the gate oxide film. In the latter case, the threshold value may be increased by increasing the oxide film thickness in the configuration of the MOS transistor. This is because a high threshold MOS is operated at a high voltage, so that it is necessary to increase the oxide film thickness. If the threshold can be increased by increasing the thickness of the oxide film, the process can be simplified.
[0096]
Furthermore, since the input / output circuit 909 needs to transmit and receive an external signal amplitude of 3.3 V, it is preferable to use the same MOS transistor as the high voltage threshold MOS because the process can be shared.
[0097]
【The invention's effect】
According to the present invention, a microprocessor having both high speed and low power consumption can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram of a processor chip in a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a general device structure used for substrate bias control.
FIG. 3 is a sectional view showing a device structure in the first embodiment of the present invention.
FIG. 4 is a flowchart used for explaining operations in the first embodiment of the present invention;
FIG. 5 is a block diagram of a processor chip in a second embodiment of the present invention.
FIG. 6 is a block diagram of a processor chip according to a third embodiment of the present invention.
FIG. 7 is a block diagram of a processor chip according to a fourth embodiment of the present invention.
FIG. 8 is a block diagram of a processor chip according to a fifth embodiment of the present invention.
FIG. 9 is a diagram illustrating the relationship between the operation mode of the present invention and substrate bias control.
FIG. 10 is a diagram illustrating a configuration of a processor main circuit according to the present invention.
FIG. 11 is a diagram illustrating a low power consumption mode of the present invention.
FIG. 12 is a diagram illustrating sleep and deep sleep according to the present invention.
FIG. 13 is a transition diagram of the operation mode of the present invention.
FIG. 14 is a first configuration diagram of a configuration of a processor chip and a power supply control circuit according to the present invention.
FIG. 15 is a diagram illustrating a power supply replacement sequence according to the present invention.
FIG. 16 is a second configuration diagram of the configuration of the processor chip and the power supply control circuit of the present invention.
FIG. 17 is a diagram illustrating an RTC power backup sequence according to the present invention.
FIG. 18 is a diagram illustrating a sequence from the low power consumption mode of the present invention until returning by an interrupt.
FIG. 19 is a diagram illustrating a sequence from a low power consumption mode according to the present invention to return by reset.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... Processor chip, 102 ... Processor main circuit, 103 ... Operation mode control part, 104 ... Substrate bias switching device, 109 ... Timer, 501 ... Sensor, 801 ... Substrate bias generation circuit.

Claims (10)

A first logic circuit including at least one MOS transistor and having a first mode and a second mode;
A second logic circuit;
A substrate bias control circuit for controlling a substrate bias voltage applied to the at least one MOS transistor;
An operation mode control unit that operates in response to execution of an instruction to shift to the first mode or an interrupt to shift to the second mode;
The first logic circuit and the second logic circuit are formed in different well regions,
The operation mode control unit controls the substrate bias voltage of the first logic circuit in response to execution of the command, controls the substrate bias voltage in the first mode to the first voltage, and responds to the interrupt. The substrate bias voltage is controlled, the substrate bias voltage in the second mode is controlled to the second voltage, and the absolute value of the threshold voltage of the at least one MOS transistor to which the first voltage is applied is The absolute value of the threshold voltage of the at least one MOS transistor to which the second voltage is applied is made larger ,
The first logic circuit is controlled so that an input of the first logic circuit does not change in response to execution of the instruction, and after the interruption, a substrate bias voltage applied to the at least one MOS transistor is a predetermined value. A semiconductor integrated circuit that starts operation after it has stabilized to a level. In claim 1,
The first logic circuit includes a first conductivity type first MOS transistor and a second conductivity type second MOS transistor as the MOS transistors,
The first MOS transistor and the second MOS transistor are semiconductor integrated circuits constituting a CMOS circuit. In claim 2,
The substrate of the semiconductor integrated circuit has a second conductive type first semiconductor region, a first conductive type second semiconductor region, and a second conductive type third semiconductor region,
The third semiconductor region is formed in the second semiconductor region; the second semiconductor region is formed in the first semiconductor region;
The semiconductor integrated circuit, wherein the first MOS transistor is formed in the third semiconductor region, and the second MOS transistor is formed in the second semiconductor region. In claim 3,
A semiconductor integrated circuit in which a substrate bias voltage of the first MOS transistor is applied to the third semiconductor region, and a substrate bias voltage of the second MOS transistor is applied to the second semiconductor region. In claim 3,
The operation mode control unit is a semiconductor integrated circuit formed in a semiconductor region different from the second semiconductor region. In claim 1,
The operation mode control unit is a semiconductor integrated circuit including a timer for measuring a period defined as a stable period of the substrate bias voltage. In claim 1,
The operation mode control unit is a semiconductor integrated circuit including a sensor for detecting that a substrate bias voltage applied to a substrate of the at least one MOS transistor is stabilized at a predetermined value . In claim 1,
An input control circuit connected to the input of the first logic circuit;
The input control circuit, from the execution of the instruction to the start of operation of the first logic circuit, a semiconductor integrated circuit for controlling the input of the first logic circuit to a predetermined level. In claim 5,
An input control circuit connected to the input of the first logic circuit;
The input control circuit, from the execution of the instruction to the start of operation of the first logic circuit, controls the input of the first logic circuit to a predetermined level,
The input control circuit is a semiconductor integrated circuit formed in a semiconductor region in which the operation mode control circuit is configured. In claim 1,
A semiconductor integrated circuit in which the input of the first logic circuit is an information signal and a clock signal.

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