JPH04195990A - Memory device provided with battery backup - Google Patents

Abstract

PURPOSE:To attain a high density mounting as well as a reduction in cost by providing a signal switching circuit and a dynamic RAM which receives a second output signal after receiving a switched low periodic signal, switches a refresh form to a low electricity consuming mode and operates. CONSTITUTION:A power source detecting circuit (I) 4, when the voltage of a normal power source 1 starts going down, detects it, outputs a signal (b) to a power source switching circuit, and switches the power source of memory from the normal power source 1 to a battery 2. In addition, before performing the power source switching control, the detecting circuit 4 inputs to the dynamic RAM 10 with a signal (c) outputted from the power source detecting circuit (II) 6 as a trigger. A Row Address Strobe signal (h) is switched from a normal Row Address Strobe signal (f) to the low periodic signal (g) for the low electricity consuming mode which is an output from a clock generator 8. Thus, by the reduction in cost for a memory capacity which is the characteristic of the dynamic RAM 10, the memory device is constructed at low cost, and also the mounting area for an equal capacity is made small, and the high density mounting is attained.

Description

[Detailed description of the invention] [Industrial application field]

This invention provides a dynamic R with low power consumption mode.
The present invention relates to a memory device with battery backup using AM.

[Conventional technology]

Conventionally, when attempting to retain memory contents using battery power, static RAM has often been used because dynamic RAM generally consumes a large amount of power. For example, as a conventional device of this type, there is a memory device with battery backup using a static RAM as shown in FIG. In the figure, l is a normal power source for supplying power in normal conditions, 2 is an emergency battery, 3 is a normal power source 1,
Two power supply switching circuits for the battery 3; 4 is a power supply detection circuit 1 that detects the voltage of the normal power supply 1; and 5 is a static RAM.
It is. Next, the operation will be explained. In the figure, when the power supply voltage of the normal power supply 1 drops below a certain value, the power supply detection circuit (I
) 4 detects the voltage level and transmits detection information to the power supply switching circuit 3. Then, the power supply switching circuit 3 switches the power supply from the normal power supply 1 to the battery 2 and performs static RA.
I am trying to constantly supply power to M5. In addition, contrary to the above control, when the normal power supply 1 returns to a certain value or higher, the power supply detection circuit (I) 4 detects the voltage level as described above, and the power supply switching circuit 3 switches the normal power supply from the battery 2 to the normal power supply. Switch to

[Problem B that the invention attempts to solve]

Conventional memory devices with battery backup are configured as described above, so it is necessary to use static RAM that consumes less power, even though static RAM is manufactured using the same device technology as dynamic RAM. Since only about a quarter of the storage capacity can be obtained, there are problems in that the price per memory capacity becomes high and the mounting area becomes large. This invention was made to solve the above problems, and uses a dynamic RAM with a low power consumption mode to reduce the price per storage capacity, reduce the mounting area, and enable high-density packaging. The purpose of this invention is to obtain a memory device with battery backup.

[Means to solve the problem]

The memory device with battery backup in this invention is a dynamic RAM having a low power consumption mode function.
When the normal power supplied to the
5torobe) signal to a low-period signal to switch the refresh mode of the dynamic RAM.

[Effect]

The mode switching signal generation circuit according to the present invention switches the refresh mode of a dynamink RAM having a low power consumption mode function when a change in the level of the normal power supply is detected by the power supply detection means, and shifts to a storage operation in a low power consumption state. Therefore, even when the normal power supply drops or recovers, the dynamism
It is possible to perform battery recovery without damaging the memory contents of the TsukRAM.
performs a nkuanopu movement.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as in FIG. 3 are denoted by the same reference numerals. In FIG. Communicate. (Here, the power supply detection circuits 4 and 6 are collectively referred to as power supply detection means.) 7 is a mode switching signal generation circuit that generates a first output signal d and a second output signal e at appropriate timing; 8 is a clock generator that generates a fixed period signal, 9 is a Row Address 5trobe
A signal switching circuit 10 switches between the signal f and the low-period signal g, and 10 is a dynamic RAM equipped with a low power consumption mode. In addition, signal a is the signal line display of the voltage of the normal power supply 1,
Signal S is a signal outputted from the power supply detection circuit (■) 4 and conveys power supply voltage information to the power supply switching circuit 3. Signal C is output from the power supply detection circuit (■) 6 and generates a mode switching signal with power supply voltage information as described above. The signal transmitted to circuit 7, signal d, is signal f
, g, a signal e is a signal for switching the dynamic RAM 10 between a low power consumption state and a normal state, and a signal f is a Row Address Str input to the dynamic RAM 10 in the normal state.
The obe signal and the signal g are low-period signals output from the clock generator 8, and the signal is a signal selected as either the signal [or g], and is input into the dynamic RAM 10. Next, the operation will be explained. First, in the normal state, the power supply detection circuit (■) 4 detects when the voltage of the normal power supply 1 starts to drop, and outputs a signal to the power supply switching circuit 3 to switch the memory power supply from the normal power supply 1 to the battery 2. Switch. Furthermore, before the power supply switching control is performed, the signal C output from the power supply detection circuit (■) 6 is used as a trigger to input the Roiv Address to the dynamic RAM 10.
s 5trobe signal, normal Row Addr
The ess 5trobe signal r is switched to the low cycle signal g for the low power consumption mode, which is the output of the clock generator 8. Further, in order to switch the dynamic RAM 10 to the low power consumption mode, two operations are performed to input the signal e to the dynamic RAM 10. Conversely, when the normal power supply 1 recovers to a certain value or more, a switching operation opposite to the switching operation described above is performed. In other words, dynamic RAM
The signal input to 0 is returned from signal g to signal f, and signal e for low power consumption operation is invalidated. Subsequently, the power supplied to the Dynamink RAM 10 is returned from the battery 2 to the normal power supply 1. FIG. 2 is a time chart showing the timing of the above operation. The symbols in the figure match the symbols attached to the signal lines in FIG. The transition of the operation of each signal line will be explained below. When the normal power supply l drops below a certain value, the power supply detection circuit (■) 6 detects the voltage and outputs a signal C. When switching dynamic RAMl0 to low power consumption mode,
The mode switching signal generation circuit 7 causes its output to transition in the order of the signal d to the signal e. Then, when the signal e becomes significant, the dynamic RAM 10 switches to the low power consumption mode. Conversely, when the normal power supply 1 recovers to a certain value or higher, the power supply detection circuit (■) 6 detects the voltage level and disables the signal C, and then disables the signals e and d in that order. go. Here, when the signal d becomes valid, the dynamic RAM 10↓ is input to the Row Add
Ress 5Trobe signal is switched to low-cycle clock signal g as shown in the figure, and RowAddress
There is no need to control the 5-trobe elsewhere. In the above embodiment, two sets of power supply detection circuits 4゜6 are used for switching the power supply of the dynamic RAM 10 and for generating a low power consumption mode switching signal. As long as timing control is performed, one may be used instead, and the same effect as in the above embodiment can be obtained.

【Effect of the invention】

As described above, according to the present invention, the memory operation when switching to the battery to retain data in the memory during normal voltage drop can be performed using the dynamic R
By using AM, the refresh operation when the voltage drops is performed by switching control signals in a predetermined order, so it can be constructed at a low cost due to the low cost per memory capacity, which is the advantage of dynamic RAM compared to static RAM. At the same time, there is an effect that the mounting area per the same capacity becomes smaller and high-density mounting becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a memory device with a battery hack amplifier according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation transition of the device shown in FIG. 1, and FIG.
The figure is a block diagram showing the configuration of a conventional memory device with battery bank up. In the figure, 1 is a normal power supply, 2 is a battery, 4 is a power supply detection circuit (1), 6 is a power supply detection circuit (II), (4 and 6 are power supply detection means), 7 is a mode switching signal generation circuit, and 9 is a The signal switching circuit 10 is a dynamic RAM. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] Detects when the voltage of the normal power supply drops below a predetermined value,
In the memory device with battery backup that backs up the memory by switching from the normal power source to the battery,
a mode switching signal generation circuit that generates first and second output signals with different timings based on the voltage drop detection signal; and a signal that switches from a normal operation low address strobe signal to a low cycle signal based on the first output signal. A memory device with a battery backup, comprising: a switching circuit; and a dynamic RAM that operates by receiving the second output signal after receiving the switched low-period signal and switching the refresh mode to a low power consumption mode.