JPH1116351A - Dynamic semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable optimization of substrate voltage setting and reduction of junction leak to realize lower power consumption by providing a plurality of substrate potential detecting circuit and generating a substrate potential which is different in the self-refresh cycle and in the other cycle. SOLUTION: In the regular mode, an SR activating signal ϕ is in the GND level, a substrate potential detecting circuit 11 is in the enable condition, a ring oscillator 13 operates by receiving an output signal ϕN of the substrate potential detecting circuit 11 and a pump circuit 14 is operated by an output CLK of the ring oscillator 13 to drop the substrate potential. During the self- refresh mode, the substrate potential detecting circuit 12 is in the enable condition and a transfer gate TG2 is in the continuity. Using such signal ϕ for activation during the SR, the substrate potential detecting circuit 11 for regular mode or substrate potential detecting circuit 12 for self-refresh mode are used depending on the purposes to improve the charge holding time of memory cell in the SR cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device, and more particularly, to a substrate potential detecting circuit.

[0002]

2. Description of the Related Art In recent years, there has been a demand for a dynamic semiconductor memory device that can back up a battery (retain a battery) and has low power consumption.

A dynamic semiconductor memory device utilizes the principle of storing information charges in a MOS capacitor. However, the accumulated charge is gradually lost due to a junction leak or the like, so it is necessary to rewrite the accumulated charge every certain time.

This rewriting operation is called refresh.
This refresh operation needs to be performed at regular intervals even during battery backup. Typical dynamic semiconductor memory devices include RAS only refresh (hereinafter referred to as “ROR”), CAS before RAS refresh (hereinafter referred to as “CBR”), and self refresh (hereinafter referred to as “SR”). ,
Since CBR requires complicated control, it is not very preferable at the time of battery backup.

The set cycle of SR is the same as that of CBR, but after setting, both RAS (row address strobe) and CAS (column address strobe) may be at the "GND" level, so that very complicated control is required. And not.

Since low power consumption is required in battery backup, the refresh interval is controlled by a built-in timer for optimization.

[0007] The charge accumulation time (hereinafter referred to as "hold time") in a dynamic semiconductor memory device is governed by junction leakage. In FIG.
1 shows a configuration of a conventional substrate potential generating circuit and a conventional substrate potential detecting circuit.

The substrate potential detecting circuit 31 constantly monitors the substrate potential, detects a rise in the substrate potential, activates the ring oscillator 32, and lowers the substrate potential by a pump circuit (charge pump circuit) 33. Let it.

The substrate potential detection level is set so as to correspond to a cycle in which the substrate potential is increased most.

[0010]

A substrate potential generating circuit and a detecting circuit of a conventional dynamic semiconductor memory device are:
Since it is configured as described above, the normal mode and S
In any of the R (self-refresh) mode operations, the substrate potential set for the normal mode is detected. Therefore, in self-refresh requiring a hold time, the substrate potential becomes too low, and the junction leak increases. There is a problem that.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to separate a substrate potential detecting circuit in an SR mode from a circuit in a normal mode so as to form a junction. An object of the present invention is to provide a dynamic semiconductor memory device that reduces leakage.

[0012]

In order to achieve the above object, the present invention relates to a dynamic semiconductor memory device having a self-refresh function, comprising a plurality of substrate potential detection circuits, a self-refresh cycle and another cycle. And different substrate potentials are generated.

[0013]

Embodiments of the present invention will be described below. In a preferred embodiment, the dynamic semiconductor memory device of the present invention has a self-refresh function, and the substrate potential detection circuit is provided with a detection circuit which operates by inputting a self-refresh signal and a detection circuit which operates in a normal mode. It is characterized by having a circuit.

More specifically, the embodiment of the present invention preferably includes a first substrate potential detection circuit (11 in FIG. 1) selected in the normal mode and a second substrate potential detection circuit activated in the self-refresh operation. Reference potential detection circuit (12 in FIG. 1)
And means for selectively outputting the outputs of the first and second reference potential detecting circuits in accordance with the normal mode and the self-refresh mode, respectively (SR in FIG. 1).
An activation signal φ, an inverter INV, transfer gates TG1 and TG2), a ring oscillator (13 in FIG. 1) to which the output of the first or second reference potential detection circuit selected and output is input, and a ring oscillator of this ring oscillator. A pump circuit (14 in FIG. 1) for varying the substrate potential according to the output;
And generates different substrate potentials between the self-refresh cycle and other cycles.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a diagram showing a configuration of a substrate potential detection circuit of a dynamic semiconductor memory device according to one embodiment of the present invention.

Referring to FIG. 1, a substrate potential detecting circuit 11
Denotes a substrate potential detection circuit for the normal mode (also referred to as “normal mode substrate potential detection circuit”), and the substrate potential detection circuit 12 is a self-refresh (SR) substrate detection circuit (SR substrate potential). Detection circuit), 13
Is a ring oscillator, and 14 is a pump circuit. Also,
The outputs of substrate potential detection circuits 11 and 12 are supplied to ring oscillator 13 via N-type transfer gates TG1 and TG2.
, An inverted signal of the SR activation signal φ by the inverter INV is input to the gate terminal of the transfer gate TG1, and the SR activation signal is input to the gate terminal of the transfer gate TG2. The SR activation signal φ and its inverted signal by the inverter INV are input to the substrate potential detection circuits 12 and 11, respectively.
Control activation.

In the normal mode, the SR activation signal φ is at the 'GND' (Low) level, the substrate potential detection circuit 11 is enabled, and the transfer gate TG1 is turned on (at this time, the substrate potential detection circuit 12 Disabled state, transfer gate TG2 is non-conductive state), ring oscillator 13 includes substrate potential detecting circuit 11
Operates in response to the output signal φ _N of
, The pump circuit 14 operates to lower the substrate potential.

At the time of SR (self refresh), SR
Since activation signal φ attains the power supply level (High level), substrate potential detection circuit 12 is enabled and transfer gate TG2 is turned on (at this time, substrate potential detection circuit 11 is disabled and transfer gate TG1 is turned off). Is non-conductive).

Ring oscillator 13 operates in response to output signal φ _S of substrate potential detection circuit 12.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention.

When SR activation signal φ is at the 'GND' level, the substrate potential is at the level of V1.

In this state, when the substrate potential rises due to a read cycle, a write cycle or the like and exceeds the normal mode detection level S1, the normal mode detection signal φ _N is activated and the pump circuit 14 lowers the substrate potential. Then, the original level V1 is maintained.

When the SR mode is entered and the SR activation signal φ attains the power supply potential 'Vcc' level, the detection level becomes S2.

When the substrate level rises, SR
Use detection signal phi _S is activated, lowering the substrate potential by a pump circuit 14, the level V2 is maintained.

As described above, in one embodiment of the present invention,
Using the signal φ activated during SR, the substrate potential detecting circuit 11 for normal mode and the substrate potential detecting circuit 12 for self-refresh are selectively used in each cycle, and the substrate potential in each cycle is changed. , The charge retention time of the memory cell can be improved.

[0026]

As described above, according to the present invention,
Since the substrate potential detection circuit for both the normal mode and the SR mode is included, it is possible to optimize the substrate potential setting at the time of SR (self-refresh) and reduce junction leakage, thereby reducing the power consumption of the dynamic semiconductor. A storage device can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing waveform chart for explaining the operation of one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional technique.

[Explanation of symbols]

11, 12, 31 Substrate potential detection circuit 13, 32 Ring oscillator 14, 33 Pump circuit φ SR activation signal φ _N Substrate potential detection circuit 11 output signal φ _S substrate potential detection circuit 12 output signal

Claims (3)

[Claims] 1. A dynamic semiconductor memory device having a self-refresh function, comprising a plurality of substrate potential detection circuits, wherein different substrate potentials are generated between a self-refresh cycle and another cycle. Dynamic type semiconductor memory device. 2. A dynamic semiconductor memory device having a self-refresh function, comprising: at least a first substrate potential detection circuit selected in a normal mode; and a second reference potential detection circuit selected in a self-refresh operation. Means for selectively outputting the outputs of the first and second reference potential detection circuits according to a normal mode and a self-refresh mode, respectively, and detecting the first or second reference potential output selectively output A ring oscillator having an output of a circuit as an input; and a pump circuit for varying a substrate potential according to the output of the ring oscillator, wherein different substrate potentials are generated in a self-refresh cycle and another cycle. A dynamic semiconductor memory device characterized by the above-mentioned. 3. The first and second reference potential detection circuits are activated based on a self-refresh activation signal. In a self-refresh mode, the second reference potential detection circuit is activated, and the first and second reference potential detection circuits are activated. The potential detection circuit is deactivated,
3. The dynamic semiconductor memory according to claim 2, wherein in a normal mode, the first reference potential detection circuit is activated and the second reference potential detection circuit is deactivated. apparatus.