JP2001250377A - Electronic equipment with energy saving function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic equipment in which transition to a energy saving mode can be performed independently of stored contents of a DRAM such as whether significant stored contents exists or not, and the like, by backing up a DRAM by a power source which is never turned off even in a energy saving mode. SOLUTION: This device is provided with a main control section to which electric power is supplied from a main power source 112 through a switch means 13 which is turned off in a energy saving mode, and a DRAM 21 to which a power source is supplied from the main power source independently of power source supply to the main control section. In a energy saving mode, the switch means 13 is turned off and power source supply to the main control section 14 is stopped, while a power source is supplied from the main power source 12, a power source of the DRAM 21 is backed up, and refreshing is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backup of a DRAM in an electronic device having an energy saving function such as a facsimile device, which can reduce power consumption in a standby state.

[0002]

2. Description of the Related Art In a device that handles image information such as a facsimile machine, a DRAM (Dynami
c Random Access Memory) is commonly used.
DRAMs are volatile in nature, but there is a demand for providing some degree of non-volatility to such devices as a provision for unexpected power failure.

For this purpose, a battery backup is performed in the DRAM. However, unlike an SRAM which is frequently used as a battery backup target, the DRAM is basically a capacitor memory. It is necessary to perform a refresh operation to recover the power, and power consumption accompanying the refresh operation is inevitable.

A self-refresh mode, which consumes less power, including peripheral circuits, is often used. However, if a backup is made using a primary battery such as an SRAM (Static RAM), the battery is completely discharged in a short time. It is common to use a secondary battery. The backup time in one discharge cycle of the secondary battery is usually at most one hour or more from the capacity of the secondary battery that can be actually used.

[0005] On the other hand, there has been a growing demand for electronic devices to reduce power consumption in recent years. In order to respond to this, a large number of devices provided with a so-called energy saving mode in which the power consumption in the standby state is made smaller than that in the normal operation have been provided.

For example, in a facsimile apparatus with an energy saving function for reducing power consumption in a standby state as disclosed in Japanese Patent Application Laid-Open No. Hei 8-214069, all units in the apparatus are controlled by a main control unit in a normal state by energy saving control. While sending a control instruction signal to the means, the energy saving control means cuts off the main power supply of the main control means and other means in the standby state to shift to the energy saving state, and in the energy saving state, the user presses the energy saving key, There is known a method of releasing from an energy saving state by an event signal such as a document set, a ringing signal at the time of reception, and an off-hook signal at the time of transmission. As in this example, the power supply to the main control unit is stopped in the energy saving mode, and only the minimum circuit power supply for monitoring events such as operation input by the operator or incoming calls from the line in communication equipment Is supplied.

[0007] In a device having an energy-saving mode and a DRAM, the DRAM is generally connected to a power supply of the same system as the power supply of the main control unit (for example, see Japanese Patent Application Laid-Open No. 7-1995).
334432).

[0008]

In this case, when the power of the main control unit is turned off, the DRAM is backed up from the battery. However, in this case, the secondary battery is discharged in a frequently-used energy saving mode. The backup operation cannot be guaranteed when backup is truly required, such as in the event of a critical power failure. Therefore, if there is significant storage content to be backed up in the DRAM, control is performed so as not to enter the energy saving mode.

[0009] However, this reduces the chances of entering the energy saving mode, so that it is not possible to sufficiently meet the demand for reducing power consumption.

The present invention solves such a problem, and in the energy saving mode, by backing up the DRAM with a power supply that does not turn off even in the energy saving mode, the DRAM is controlled by the memory content such as whether or not there is significant memory content. It is an object of the present invention to provide an electronic device capable of shifting to an energy saving mode.

[0011]

According to a first aspect of the present invention, there is provided an electronic device having an energy-saving function, wherein power is supplied from a main power source.
An energy-saving control unit for controlling to an energy-saving mode; a main control unit for supplying power from the main power supply via switch means turned off in the energy-saving mode to control the whole; and a power supply for supplying power from the main power supply and having a refresh mode. DRAM
With

When the power supply to the main control unit is stopped, power is supplied from the main power supply to back up and refresh the DRAM.

According to this configuration, even in the energy saving mode, the power is supplied from the main power supply to back up and refresh the DRAM, so that the energy saving can be performed regardless of the stored contents of the DRAM such as whether or not there is significant stored contents. Mode. As a result, in the energy saving mode,
The main control unit is turned off, so that power consumption of the electronic device can be reduced.

According to a second aspect of the present invention, in the electronic device with the energy saving function according to the first aspect, the refresh mode of the DRAM is set to a self-refresh mode, and power is supplied to the main control unit. Monitoring is performed, and a self-refresh mode control signal is generated based on the monitoring result, and the DRAM is placed in a self-refresh mode.

According to this configuration, in the energy saving mode,
Since the DRAM is in the self-refresh mode, power consumption is further reduced. Since the control signal of the self-refresh mode is formed separately from the main control unit by using the output of the reset circuit for monitoring the power supply line which is turned off in the energy saving mode, the configuration is simplified and the cost is reduced. be able to.

According to a third aspect of the present invention, there is provided the electronic device with the energy saving function according to the first and second aspects, wherein the voltage of the backup battery and the voltage of the main power supply are changed according to the relationship between the voltage of the backup battery and the voltage of the main power supply. A backup circuit for switching between the backup battery and the main power supply and supplying power to the DRAM is provided.

According to this configuration, since the power is supplied to the DRAM by switching between the backup battery and the main power supply, the DRAM can be backed up even when the main power supply fails. Also, the backup battery need only be supplied with power when the main power supply fails, and the DRAM is placed in a self-refresh mode to reduce power consumption as in the case of energy saving. Therefore, backup is performed for a long time with a small-capacity backup battery. be able to.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration diagram of an electronic device with an energy saving function to which the present invention is applied.
Is a timing chart at the time of the energy saving operation.

In FIG. 1, a DC power supply 12 as a main power supply is provided.
Receives the voltage of the AC power supply 11 and outputs a predetermined DC voltage Vs. The switch 13 is turned on during a normal operation and turned off during an energy saving mode. The voltage Vm passed through the switch 13 is supplied to the main control unit 14 and the main reset circuit 15.

The main control unit 14 controls the SD during normal operation.
It controls the operation of the entire electronic device including access to a RAM (synchronous DRAM). Main reset circuit 15
Receives the voltage Vm, generates a reset signal or a power-on reset signal, and outputs this signal Rm to the main control unit 14.
To supply.

The energy-saving control unit 16 is issued after a command input from the main control unit 14 (for example, when an input event has not occurred for a certain period of time, etc., and termination processing of each unit in progress is completed. Control in energy saving mode. At the beginning of the energy saving mode, the switch 13 is turned off to turn off the power of the main control unit 14. When a predetermined event signal such as an operation input is received during the energy saving mode, the switch 13 is turned off.
Is turned on, and the main control unit 14 is activated to release the energy saving mode and report the cause of the release (not shown). Further, the energy saving reset circuit 17 receives the voltage Vs of the DC power supply 12, creates a reset signal or a power-on reset signal, and supplies this signal Rs to the energy saving control unit 16.

The backup circuit 19 selects and outputs the higher one of the voltage Vs of the DC power supply 12 and the voltage of the floating-charged secondary battery 18. This voltage selection may be performed using a diode matching circuit as shown in the figure, or may be performed using a changeover switch.
In any case, it is only necessary to select the higher voltage.

SDRAM (Synchronous DRAM) 2
Reference numeral 1 denotes a DRAM which performs input / output in synchronization with an external clock to increase the data transfer rate, and has a DRAM of, for example, 100 MHz.
It operates in synchronization with an external clock CLK that is as fast as possible, and takes in an external signal at the rising edge of the clock. SD
The RAM is provided with a self-refresh mode as a refresh mode, in which a refresh operation is automatically performed at regular intervals by an internal timer. According to the present invention, the self-refresh is performed in the energy-saving mode, thereby achieving a more energy-saving effect. Is what you get. Also, S
A backup power supply from a backup circuit 19 is supplied to a power supply terminal of the DRAM 21, and a voltage Vs of the DC power supply 12 is supplied from the secondary battery 18 when the DC power supply 12 is out of power and during other normal operation and the energy saving mode. .

The driver circuit 20 receives a control signal from the main control unit 14 and reads, writes,
It supplies various drive signals such as refresh. The power from the backup circuit 19 is also supplied to the driver circuit 20.

A clock enable signal generation circuit (CKE)
The generation circuit 22 is for putting the SDRAM 21 into the self-refresh mode in the energy saving mode, and receives the reset signal or the power-on reset signal Rm of the main reset circuit 15 and the clock signal CLK from the main control unit 14. , The high level (H level) of the clock enable signal CKE synchronized with the clock signal CLK
From the low level (L level) to the low level (L level),
At the same time, a refresh command issuance instruction signal REF is generated. Further, the CKE generation circuit 22 generates an L → H transition of the clock enable signal CKE asynchronous with the clock signal CLK for releasing the self-refresh mode.

The ground resistance R connected to the input terminal of the clock enable signal CKE of the SDRAM 21 is CK
This is to maintain the L level even when the power of the E generation circuit 22 is off.

The operation of the thus configured electronic device with an energy saving function will be described. First, an operation for entering the energy saving mode during the normal operation will be described. The state of each signal at this time is shown as a timing chart in FIG.

During normal operation, the voltage V
s is output, and the voltage Vs is supplied to the energy saving control unit 16 and the energy saving reset circuit 17.
3 is on, the voltage Vm is supplied to the main control unit 14 and the main reset circuit 15. Also, SDRA
M21 and the driver circuit 20 include a backup circuit 1
9, the voltage Vs is supplied.

In this state, as shown in FIG.
The signal Rs which is a reset signal or a power-on reset signal from the energy saving reset circuit 17 is at the H level,
A reset signal from the main reset circuit 15 or a signal Rm which is a power-on reset signal is also at the H level,
The energy saving control unit 16 and the main control unit 14 receiving these signals Rs and Rm operate in the normal state. During normal operation, the main control unit 14 monitors, for example, an input event and controls the SDRAM 21 for a driver circuit 20.
Energy saving control unit 16, SDRAM 2 such as controlling memory operations such as writing, reading, and refreshing via
And 1 controls the entire operation of the electronic device.

The clock signal C from the main control unit 14
CKE generating circuit 22 receiving LK and signal Rm outputs signal R
While m is at the H level, the clock enable signal CK
E is set to the H level, and the refresh command issuance instruction signal REF is not generated. Therefore, SDRAM 21 does not enter the self-refresh mode.

In the normal operation state as described above, the main control unit 14 sets the energy saving mode so that the electronic device is set to the energy saving mode when the standby state continues for a certain period of time, such as when no input event occurs for a certain period of time. An energy saving command signal is supplied to the control unit 16. When the energy saving command signal is supplied to the energy saving control unit 16, the main control unit 14 has finished terminating the running job and accessing the SDRAM 21.

The energy saving control section 16 receives the energy saving command signal from the main control section 14 and turns off the switch 13.
Even in this energy saving mode, the voltage V
Since s is at a steady voltage, the voltage Vs
Is supplied.

When the switch 13 is turned off, the main control unit 14
Further, the voltage Vm of the main reset circuit 15 decreases as shown in FIG. When the voltage Vm decreases from the steady voltage to a certain value, the main reset circuit 15 outputs an L-level reset signal Rm as shown by a signal Rm in FIG.

This L-level reset signal Rm is sent to the main control unit 14 and the CKE generation circuit 22, and the main control unit 14 is reset. At this time, since the CKE generation circuit 22 receives the L-level reset signal Rm, the clock enable signal CKE from the main control unit 14 makes an H → L transition in synchronization with the clock signal CLK, and simultaneously issues a refresh command. The instruction signal REF is supplied to the driver circuit 2
Supply 0.

Refresh command issuance instruction signal REF
The driver circuit 20 having received the refresh command S
Issued to DRAM 21, SDRAM 21 is placed in a self-refresh state. These series of operations are performed by the voltage V
m is executed in the transition period during descent.

SDR in self-refresh state
The AM 21 sequentially selects word lines necessary for refreshing while sequentially incrementing the address by a clock signal generated therein. When all the word lines are selected, one round of refresh is completed. This operation is repeated unless is canceled.

As described above, in the self-refresh mode, an internally generated clock signal is used.
Unlike refreshing in a normal operation in which a refresh cycle is performed by giving a command from the outside of the SDRAM 21, the power supply of the refresh trigger circuit outside the SDRAM can be turned off, and power consumption can be reduced.

The self refresh is performed in the SDRAM 2
1 is used to hold data when it is not necessary to access 1. Therefore, the internal clock cycle can be lengthened and current consumption can be reduced. It can be as small as an order of magnitude.

During this energy saving operation, the energy saving control unit 16 monitors a predetermined event signal such as an operation input, and turns on the switch 13 when any event signal is received. When the voltage Vm rises and exceeds a predetermined level when the switch 13 is turned on, the signal Rm as the power-on reset signal of the main reset circuit 15 changes to the H level.

The power-on reset signal R
In response to the transition of m to the H level, the main control unit 14 performs an initial setting process, and the CKE generation circuit 22 causes the clock enable signal CKE to transition from the L level to the H level. This may be asynchronous with the clock CLK of the SDRAM 21. Thereby, the SDRAM 21 releases the self-refresh mode and returns to the normal operation state.

As described above, even in the energy saving mode, the voltage Vs of the DC power supply 12 is supplied to the SDRAM 21 to back up the power supply and refresh the SDRAM 21. Therefore, when shifting from the normal operation state to the energy saving operation state, significant storage contents are obtained. It is possible to shift to the energy saving mode irrespective of the stored contents of the DRAM, such as whether or not there is a memory. Thus, in the energy saving mode, the main control unit 14 is turned off, and the power consumption of the electronic device can be reduced.

In the energy saving mode, the SDRAM 2
Setting 1 to the self-refresh mode further reduces power consumption. Then, the control signals REF and CKE in the self-refresh mode are changed to the output R of the main reset circuit 15 for monitoring the power supply line which is turned off in the energy saving mode.
Since m is used to form the CKE generation circuit 22 provided separately from the main control unit 14, the configuration is simplified and the cost can be reduced.

As described above, when the normal operation state and the energy saving operation state are taken into consideration, the secondary battery 18 and the backup circuit 19 are deleted from the configuration of FIG.
May be connected to the voltage Vs.
Even in this case, the effect in the energy saving mode is exhibited.

Next, the operation when the input of the DC power supply 12 is stopped due to a power failure or the like during the normal operation will be described. The state of each signal at this time is shown as a timing chart in FIG.

The operation during the normal operation is the same as that described with reference to FIG. If a power failure occurs during normal operation, the voltage Vs of the DC power supply 12 decreases. In this case, since the switch 13 is on because the mode is not the energy saving mode, the voltage Vm also decreases. When the voltage Vm and the voltage Vs decrease from the steady voltage to a certain value, the main reset circuit 15 and the energy-saving reset circuit 17 output L-level reset signals as shown by the signals Rm and Rs in FIG.

The L-level reset signal Rs is sent to the energy-saving control unit 16, and the energy-saving control unit 16 is reset after performing the termination processing of the job being executed.

On the other hand, the L-level reset signal Rm is sent to the main control unit 14 and the CKE generation circuit 22,
Is reset after terminating the running job. At this time, since the CKE generation circuit 22 receives the L-level reset signal Rm, the clock enable signal CKE from the main control unit 14 makes an H → L transition in synchronization with the clock signal CLK, and simultaneously issues a refresh command. The instruction signal REF is supplied to the driver circuit 20.

Refresh command issuance instruction signal REF
The driver circuit 20 having received the refresh command S
It is issued to the DRAM 21. These series of operations are executed in a transition period in which the voltage Vm and the voltage Vs are falling.

On the other hand, the power supply of the SDRAM 21 is automatically supplied from the secondary battery 18 when the voltage Vs falls to a certain value by the backup circuit 19. Thus, SDRAM 21 is placed in the self-refresh mode.

The self refresh of the SDRAM 21
This is the same as in the energy saving mode described with reference to FIG. 2, and since the internally generated clock signal is used, the power supply of the refresh trigger circuit outside the SDRAM can also be turned off, and the power consumption can be reduced. Further, by increasing the internal clock cycle, the current consumption can be reduced by about two digits, for example, compared to the current consumption during refresh in normal operation.

In the power failure state, power is supplied from the secondary battery 18 to the SDRAM 21 placed in the self-refresh mode. However, since the power consumption is reduced, a long-term backup is possible, and the current consumption is significantly reduced. Therefore, a battery having a small current capacity can be used.

When the power failure is restored, first, the voltage Vs of the DC power supply 12 rises. Since the switch 13 is turned on, the voltage Vm rises together with the voltage Vs, and the rise is detected by the main reset circuit 15 and the energy-saving reset circuit 17, and the signal Rm, which is an H level power-on reset signal, is output from the main control unit 14. Then, the signal Rs is sent to the energy saving control unit 16 respectively. When the switch 13 has been turned off, the switch 13 is turned on after the energy saving control unit 16 starts up, and power is supplied to the main control unit 14.

On the other hand, the SDRAM 21 has a DC power supply 12
When the voltage Vs exceeds the voltage of the secondary battery 18,
Instead of the secondary battery 18 by the backup circuit 19,
Supplied.

In response to the transition of the signal Rm, which is the power-on reset signal, to the H level, the main control unit 14 performs an initialization process, and the CKE generation circuit 22 transitions the clock enable signal CKE from the L level to the H level. Let it.
This may be asynchronous with the clock CLK of the SDRAM 21. Thereby, the SDRAM 21 releases the self-refresh mode and returns to the normal operation state before the power failure.

According to the embodiment of the present invention, even in the energy saving mode, the voltage Vs of the DC power supply 12 is supplied to the SDRAM 21 to back up the power, and the SDRAM 21 is refreshed. It is possible to shift to the energy saving mode irrespective of the storage contents of the DRAM, such as whether or not significant storage contents exist. Thus, in the energy saving mode, the main control unit 14 is turned off, and the power consumption of the electronic device can be reduced.

In the power saving mode and the power failure state, the power consumption can be further reduced by setting the SDRAM 21 in the self refresh mode.

In both the energy saving mode and the power failure state, the state detection is detected by the main reset circuit 15 which monitors the power supply line which is turned off in the energy saving mode, and based on the detection signal Rm, the main controller 14 A control signal REF, C for setting the SDRAM 21 in the self-refresh mode is provided by a CKE generation circuit 22 separately provided.
KE is formed. Therefore, the configuration for detecting the state and forming the control signal is simplified, and the cost can be reduced.

In a power failure state, power is supplied from the secondary battery 18 to the SDRAM 21 placed in the self-refresh mode. However, since power consumption is reduced, long-term backup is possible and current consumption is reduced. Since the amount is significantly reduced, a battery having a small current capacity can be used.

[0059]

According to the first aspect of the present invention, even in the energy saving mode, the power is supplied from the main power source to back up and refresh the DRAM, so that the storage of the DRAM, such as whether or not there is significant storage content, is performed. Regardless of the content, the mode can be shifted to the energy saving mode. Thus, in the energy saving mode, the main control unit is turned off, and the power consumption of the electronic device can be reduced.

According to the second aspect of the present invention, in the energy saving mode, the DRAM is in the self refresh mode, so that the power consumption is further reduced. Since the control signal of the self-refresh mode is formed separately from the main control unit by using the output of the reset circuit for monitoring the power supply line which is turned off in the energy saving mode, the configuration is simplified and the cost is reduced. be able to.

According to the third aspect of the present invention, since the power is supplied to the DRAM by switching between the backup battery and the main power supply, the DRAM can be backed up even when the main power supply fails. Also, the backup battery only needs to be supplied when the main power supply is interrupted.
Since the AM is in the self-refresh mode and consumes less power, a long-time backup can be performed with a small-capacity backup battery.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an electronic device with an energy saving function according to an embodiment of the present invention.

FIG. 2 is a timing chart during an energy saving operation according to the embodiment of the present invention.

FIG. 3 is a timing chart during a power failure operation according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 AC power supply 12 DC power supply 13 Switch 14 Main control part 15 Main reset circuit 16 Energy saving control part 17 Energy saving reset circuit 18 Secondary battery 19 Backup circuit 20 Driver circuit 21 SDRAM 22 CKE generation circuit

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5B011 DA02 DA13 DB21 EA10 EB01 GG03 HH02 JB02 KK02 KK03 MA07 5B024 AA01 BA29 CA27 DA01 DA20 5C062 AB43 AB50 AB51 BA00 5K037 AA13 AB07 5K101 KK01 NN21 NN45

Claims (3)

[Claims] An electric power is supplied from a main power supply through an energy saving control unit that is supplied with power from a main power supply and controls an energy saving mode, and a switch that is turned off in the energy saving mode.
A DRAM which is supplied with power from the main power supply and has a refresh mode, and which is supplied with power from the main power supply when the supply of power to the main control unit is stopped. An electronic device with an energy-saving function that backs up and refreshes. 2. The electronic device with an energy saving function according to claim 1, wherein a refresh mode of said DRAM is a self-refresh mode, a power supply to said main control unit is monitored, and a self-refresh mode control signal is generated based on a result of the monitoring. An electronic device with an energy saving function, wherein the electronic device is created and the DRAM is placed in a self-refresh mode. 3. The electronic device with an energy saving function according to claim 1, wherein the backup battery and the main power are switched according to a relationship between a voltage of a backup battery and a voltage of the main power. An electronic device with an energy saving function, comprising a backup circuit for supplying power to a DRAM.