JP4158569B2 - Information processing apparatus and information processing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing apparatus and an information processing method, and in particular, even when an interrupt request is generated when a storage unit storing data necessary for interrupt processing is in a power saving mode, the storage unit can be smoothly operated. The present invention relates to an information processing apparatus and an information processing method that can perform interrupt processing by returning to a non-power saving mode.
[0002]
[Prior art]
Currently, information processing apparatuses having a power saving function are widely used. This power saving function is installed not only in the CPU but also in each component of the information processing apparatus, and can be switched to a power saving mode and a non-power saving mode.
[0003]
As a DRAM widely used as a main memory of an information processing apparatus, a DRAM having a power saving function has become widespread. For example, there is a product having a function (self-refresh function) for automatically refreshing a DRAM chip alone. In this DRAM, during the power saving mode (self-refresh mode), the portions other than the circuit executing the self-refresh function in the DRAM chip sleep, so that power consumption can be suppressed. Even when the memory controller that gives the DRAM a refresh cycle is in the power saving mode, the DRAM itself can be automatically refreshed by the self-refresh function, so the stored data is not lost. Note that when the DRAM is in the self-refresh mode, data cannot be read / written.
[0004]
The transition from the normal operation mode (non-power saving mode) of the DRAM to the self-refresh mode or the return from the self-refresh mode to the normal operation mode is usually performed by a command from the CPU.
[0005]
An interrupt request may occur during the period in which the CPU enters the power saving mode after the DRAM is shifted to the self refresh mode by the CPU self refresh transition command. In this case, the CPU returns from the power saving mode to the non-power saving mode in response to the generated interrupt request, and performs an interrupt process.
[0006]
However, when data necessary for interrupt processing is stored in the DRAM, it is necessary to restore the DRAM from the self-refresh mode to the normal operation mode before the CPU accesses the DRAM.
[0007]
For this reason, conventionally, all data necessary for interrupt processing is stored in a dedicated SRAM or a boot ROM for storing boot code executed after power-on, and an interrupt request is made during the power saving mode. When this occurs, data necessary for interrupt processing is obtained from a dedicated SRAM or boot ROM. However, when SRAM is used, since the SRAM itself is expensive, there is a problem that the cost of the apparatus increases by mounting the SRAM. When the boot ROM is used, the boot ROM itself is conventional. Since it is hardware that is generally installed in information processing devices, it does not cost anything, but because the access speed is slower than RAM, not only interrupt processing in power saving mode but also in non power saving mode. There is a problem that the processing is slow.
[0008]
As an apparatus for solving such a problem, an information processing apparatus provided with a WAITI instruction fetch detection circuit for returning an SDRAM to a normal operation mode by an external interrupt signal is known (for example, see Patent Document 1). reference.).
[0009]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-140138
[Problems to be solved by the invention]
However, since such a WAITI instruction fetch detection circuit is not provided in a general information processing apparatus, the information processing apparatus in which the WAITI instruction fetch detection circuit is not provided can return the DRAM to the normal operation mode. There is a problem that it is not possible.
[0011]
The present invention has been made to solve the above-described problems, and can perform interrupt processing smoothly with a conventional hardware configuration without providing an additional circuit, and the processing speed can be reduced. It is an object to provide an information processing apparatus and an information processing method that can be minimized.
[0012]
[Means for Solving the Problems]
The information processing apparatus according to the present invention is necessary for data necessary for processing to switch from the power saving mode to the non power saving mode and for processing that can be executed in the interrupt processing before switching from the power saving mode to the non power saving mode. storing a first storage means for storing initial data necessary for the initialization of interrupt processing, interrupt processing data required for the interrupt processing, or processing data except for the initial data from the interrupt processing data including data And a second storage means capable of switching between a power saving mode and a non-power saving mode, and when an interrupt request is generated when the second storage means is in the power saving mode, the first storage means switching the second storage means in the processing and interrupt processing switching the second storage means to obtain the initial data from the power saving mode to the non-power saving mode from the power saving mode to the non-power saving mode from the Perform executable processing until the second after the storage means is switched to the non-power saving mode, interrupt processing data stored in said second storage means, or excluding the initial data processing Interrupt processing means for acquiring data and continuing interrupt processing.
[0013]
In the information processing apparatus of the present invention, first storage means, performed during the data and interrupt processing required for the processing of switching from the power saving mode to the non-power saving mode from the power saving mode to the non-power saving mode to the switched Store initial data required at the beginning of an interrupt process including data required for possible processing . The second storage means stores interrupt processing data necessary for the interrupt processing or processing data obtained by removing initial data from the interrupt processing data, and enables switching between the power saving mode and the non-power saving mode. When an interrupt request is generated when the second storage means is in the power saving mode, the interrupt processing means acquires initial data from the first storage means and removes the second storage means from the power saving mode. In the process of switching to the power mode and the interrupt process, the second storage means performs a process that can be executed until the power saving mode is switched to the non-power saving mode, and the second storage means is switched to the non-power saving mode. After that, the interrupt processing data stored in the second storage means or the processing data excluding the initial data is acquired and the interrupt processing is performed.
[0014]
According to the information processing method of the present invention, the data acquisition destination for the interrupt processing is the data required for the processing for switching from the power saving mode to the non power saving mode, and the interrupt processing from the power saving mode to the non power saving mode. Interrupt processing data required for interrupt processing, or first storage means for storing initial data required at the beginning of interrupt processing including data required for processing that can be executed before switching , or A setting step of setting the second storage means storing the processing data excluding the initial data from the interrupt processing data before switching to the power saving mode; and an interrupt when the second storage means is in the power saving mode. If the request is generated in the processing and interrupt processing switching the second storage means to obtain the initial data from the first storage unit based on the setting from the power saving mode to the non-power saving mode A first interrupt process whose serial second storage means performs a process executable until switched from the power saving mode to the non-power saving mode, after the first interrupt processing step, the second storage means The interrupt processing data stored in the memory or the processing data excluding the initial data is acquired and the interrupt processing is continued, and the acquisition destination of the data for performing the interrupt processing is the first storage means And a second interrupt processing step for performing processing for switching to the second storage means.
[0015]
In the information processing method of the present invention, in the setting step, the acquisition destination of data for performing the interrupt process is the data required for the process of switching from the power saving mode to the non power saving mode, and the interrupt process is not performed from the power saving mode. Interrupts required for interrupt processing are the first storage means for storing initial data necessary for the initial stage of interrupt processing including data necessary for processing that can be executed before switching to the power saving mode. The second storage means storing the processing data or the processing data obtained by removing the initial data from the interrupt processing data is set before switching to the power saving mode. In the first interrupt processing step, when an interrupt request is generated when the second storage means is in the power saving mode, the initial data is acquired from the first storage means based on the setting and the second storage means is omitted. In the process of switching from the power mode to the non-power saving mode and the interrupt process, the second storage means performs a process that can be executed until the power saving mode is switched to the non power saving mode . In the second interrupt processing step, after the first interrupt processing step, the interrupt processing data stored in the second storage means or the processing data excluding the initial data is acquired and the interrupt processing is continued. At the same time, a process of switching the acquisition destination of data for performing the interrupt process from the first storage means to the second storage means is performed.
[0016]
According to the information processing apparatus and the information processing method of the present invention, even when the second storage unit is in the power saving mode, the data stored in the first storage unit is acquired and the second storage unit is omitted. In order to switch to the power mode, the second storage means can be switched to the non-power saving mode without providing an additional circuit similar to the WAITI instruction fetch detection circuit in the information processing apparatus. Further, after the switching, the data in the second storage means is acquired and the interrupt process is performed, so that the interrupt process can be performed smoothly and continuously.
[0018]
Also, until the second storage means switched from the power saving mode not the power saving mode, the second storage means from the power saving mode in the interrupt processing to obtain the data in the first storage means to the non-power saving mode Executable processing can be performed before switching, and the time until the second storage unit switches from the power saving mode to the non-power saving mode can be used effectively.
[0019]
As the first storage means, a non-volatile memory such as a boot ROM for storing a boot code or a backup memory backed up by a power source can be used.
[0020]
Since the boot ROM is a storage device that can be accessed at all times and is generally mounted in a conventional information processing apparatus, it is not necessary to add new storage means by using the boot ROM as the first storage means. Also, initial data is stored in the boot ROM, and interrupt processing data or processing data obtained by removing the initial data from the interrupt processing data is stored in the DRAM having a higher access speed than the boot ROM, and the interrupt processing is performed. As a result, compared with the case where the interrupt processing is performed by storing all the interrupt processing data in the boot ROM, the speed reduction at the time of executing the interrupt processing can be minimized.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0022]
FIG. 1 is a block diagram showing a configuration of an information processing apparatus 10 according to an embodiment of the present invention.
[0023]
As illustrated, the information processing apparatus 10 includes a CPU 12, a DRAM controller 14, a DRAM 16, an interrupt controller 18, a boot ROM 22, and an input / output interface (I / O) 24. Connected through.
[0024]
The CPU 12 can switch between the power saving mode and the non-power saving mode, and can return to the non-power saving mode when an interrupt signal is input from the interrupt controller 18 during the power saving mode. In addition, data stored in the DRAM 16 and the boot ROM 22 (this data includes a program code) is acquired, and processing at the time of shifting to the power saving mode, interrupt processing, and the like are executed.
[0025]
The DRAM 16 is used as a main memory. The DRAM 16 includes various data performed by the CPU 12 including data necessary for interrupt processing (hereinafter referred to as interrupt data) and data necessary for shifting each component of the information processing apparatus 10 to the power saving mode. Data necessary for processing is stored. The DRAM 16 can be switched between a self-refresh mode (power saving mode) and a normal operation mode (non-power saving mode) under the control of the CPU 12.
[0026]
The DRAM controller 14 controls the DRAM 16 to control data transfer with the CPU 12 and the I / O 24, and saves the DRAM 16 from the power saving mode to the non-power saving mode or from the non-power saving mode according to a command from the CPU 12. Issue a command to switch to power mode. When the DRAM 16 is in the non-power saving mode, the DRAM controller 14 causes the DRAM 16 to periodically refresh.
[0027]
The interrupt controller 18 outputs an interrupt signal to the CPU 12 when an interrupt request is generated.
[0028]
The boot ROM 22 stores a boot code to be executed after power-on, and the DRAM 16 is not saved from the power saving mode as data necessary for the initial stage of interrupt processing (hereinafter referred to as initial data) among interrupt data. Data necessary for processing to switch to the power mode is stored.
[0029]
The I / O 24 is connected to various input / output devices and controls data transfer.
[0030]
Details of the operation of the information processing apparatus 10 according to the present embodiment will be described below.
[0031]
When the CPU 12 and the DRAM 16 are in the non-power saving mode, the CPU 12 operates by acquiring data necessary for various processes including the interrupt process from the DRAM 16. At this time, the DRAM controller 14 periodically refreshes the DRAM 16.
[0032]
Next, the processing of the CPU 12 performed when the CPU 12 and the DRAM 16 are shifted to the power saving mode will be described with reference to the flowchart of FIG. Note that the processing in this flowchart is executed after data stored in the DRAM 16 is acquired.
[0033]
In step 100, processing is performed to set the interrupt data acquisition destination (hereinafter referred to as interrupt data address) to be the boot ROM 22. More specifically, the interrupt data address is set by changing the value of the interrupt data address register (not shown) of the CPU 12 so that the initial data of the boot ROM 22 is stored.
[0034]
In step 102, an instruction (self-refresh transition instruction) for setting the DRAM 16 to the self-refresh mode is issued to the DRAM controller 14. Upon receiving this instruction, the DRAM controller 14 issues a command for causing the DRAM 16 to shift to the self-refresh mode. Here, the issuance of a command is delayed on the DRAM controller 14 side so that the CPU 12 itself can acquire data for shifting to the power saving mode after issuing the self-refresh transition instruction. When the command is issued, the DRAM 16 shifts to the power saving mode.
[0035]
In step 104, the CPU 12 itself shifts to the power saving mode.
[0036]
Next, the processing of the CPU 12 performed when an interrupt request is generated during the power saving mode will be described using the flowchart of FIG.
[0037]
Generation of an interrupt request, for example, a job request from an external device (not shown) connected to the network, a signal from a timer (not shown) in the information processing device 10, or an I / O 24 of the information processing device 10 When a trigger is input to the interrupt controller 18 by an operation of a connected input device (not shown) (for example, key input or switch pressing), an interrupt signal is input from the interrupt controller 18 to the CPU 12.
[0038]
In step 200, the CPU 12 returns from the power saving mode to the non-power saving mode by the input of the interrupt signal.
[0039]
In step 202, interrupt data (initial data) is acquired from the boot ROM 22 based on the setting of the interrupt data address.
[0040]
In step 204, the DRAM 16 is switched from the self-refresh mode to the normal operation mode using the acquired initial data. Specifically, a self-refresh mode release command is issued to the DRAM controller 14. As a result, a command is issued from the DRAM controller 14 and the DRAM 16 is switched to the normal operation mode.
[0041]
In step 206, interrupt data is acquired from the DRAM 16 and interrupt processing is continued, and the setting of the interrupt data address is switched from the boot ROM 22 to the DRAM 16. This switching is performed by changing the value of the register for specifying the interrupt data address so that the interrupt data address becomes the address of the area where the interrupt data of the DRAM 16 is stored, as in the process of step 100 described above. Is called.
[0042]
As described above, among the interrupt process data necessary for the interrupt process, the initial data necessary for the initial stage of the interrupt process including the data necessary for the process of switching the DRAM 16 from the power saving mode to the non-power saving mode is booted. When an interrupt request is generated when the DRAM 16 stored in the ROM 22 and storing the interrupt processing data is in the power saving mode, the initial data is acquired from the boot ROM 22 and the DRAM 16 is set in the non-power saving mode. Therefore, the DRAM 16 can be switched to the non-power saving mode without providing an additional circuit. In addition, after the DRAM 16 is switched to the non-power-saving mode, the interrupt processing data is acquired from the DRAM 16 and the interrupt processing is continued. Therefore, when the interrupt processing is performed by storing all the interrupt data in the boot ROM 22. In comparison, the reduction in processing speed can be minimized.
[0043]
In the above-described embodiment, the example in which data necessary for the process of switching the DRAM 16 from the power saving mode to the non-power saving mode is stored in the boot ROM 22 as the initial data has been described. In addition, in the interrupt processing, data necessary for processing that can be executed before the DRAM 16 is switched from the power saving mode to the non-power saving mode can be stored in the initial data. In this case, in step 204 of FIG. 3, not only the release of the self-refresh mode of the DRAM 16 but also the acquisition of the data in the boot ROM 22 until the DRAM 16 is switched from the power saving mode to the non-power saving mode. Continue processing. Thereby, the time until the DRAM 16 is switched from the power saving mode to the non-power saving mode can be used effectively.
[0044]
Further, in the above-described embodiment, the CPU 12 has explained an example in which all data necessary for the process for shifting to the power saving mode is acquired from the DRAM 16 and processed. However, this data is stored in the boot ROM 22 in advance. You may make it leave. With such a configuration, a command for shifting to the self-refresh mode can be immediately issued from the DRAM controller 14 to the DRAM 16.
[0045]
In the above-described embodiment, description of switching between the power saving mode and the non-power saving mode of the DRAM controller 14 is omitted, but the DRAM controller 14 also shifts to the power saving mode and the non-power saving mode together with the CPU 12. It may be.
[0046]
In the above-described embodiment, the example in which all the interrupt data is stored in the DRAM 16 has been described. However, the processing data excluding the initial data necessary for the initial stage of the interrupt processing from the interrupt data is stored. It may be.
[0047]
Furthermore, the information processing apparatus according to the present invention is not limited to the above-described configuration of the information processing apparatus as long as it has a configuration for realizing the present invention.
[0048]
【The invention's effect】
The power saving control apparatus and the power saving control method according to the present invention store initial data necessary for an initial stage of an interrupt process including data necessary for a process of switching from a power saving mode to a non-power saving mode in a first storage unit. If an interrupt request is generated when the second storage means is in the power saving mode, the initial data is acquired from the first storage means and the second storage means is changed from the power saving mode to the non-power saving mode. After the second storage means is switched to the non-power-saving mode, the data stored in the second storage means is acquired and the interrupt process is continuously performed. Even if a special circuit is not provided, the interrupt processing can be performed smoothly by switching the first storage means to the non-power saving mode with the conventional hardware configuration, and the decrease in processing speed can be minimized. , Has the effect.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an information processing apparatus according to an embodiment of the present invention.
FIG. 2 is a flowchart showing processing performed by a CPU when a CPU and a DRAM are shifted to a power saving mode.
FIG. 3 is a flowchart illustrating a process performed by a CPU when an interrupt request is generated in the power saving mode.
[Explanation of symbols]
10 Information processing device 12 CPU
14 DRAM controller 16 DRAM
18 Interrupt controller 22 Boot ROM

Claims (6)

Initial stage of interrupt processing including data required for processing to switch from power saving mode to non-power saving mode and data required for processing that can be executed before switching from power saving mode to non power saving mode in interrupt processing First storage means for storing initial data required for
Second processing means capable of storing interrupt processing data required for interrupt processing or processing data obtained by removing the initial data from the interrupt processing data, and capable of switching between a power saving mode and a non-power saving mode;
When said interrupt request occurs when in the second storage means the power saving mode, the first from the storage means to acquire the initial data the second non-power saving mode storage means from the power saving mode In the process of switching to and the interrupt process, the second storage means performs a process that can be executed before switching from the power saving mode to the non power saving mode, and the second storage means is switched to the non power saving mode. After that, interrupt processing data stored in the second storage means, or interrupt processing means for obtaining the processing data excluding the initial data and continuing the interrupt processing;
An information processing apparatus including: It said first storage means according to claim 1 Symbol placement of the information processing apparatus is a backup memory backed up by non-volatile memory or power. It said first storage means according to claim 1 Symbol placement of the information processing apparatus is a boot ROM for storing boot code. The data acquisition destination for interrupt processing can be executed before the data required for processing to switch from the power saving mode to the non power saving mode and before switching from the power saving mode to the non power saving mode in the interrupt processing. The first storage means for storing the initial data necessary for the initial stage of the interrupt process including the data necessary for the correct process, the interrupt process data necessary for the interrupt process or the initial value from the interrupt process data A setting step for setting the second storage means storing the processing data excluding the data before switching to the power saving mode;
When said second storage means interrupt request when it is in the power saving mode is generated, the second storage means to obtain the initial data from the first storage unit based on the setting from the power saving mode A first interrupt processing step for performing a process that can be executed until the second storage unit switches from the power saving mode to the non power saving mode in the process of switching to the non power saving mode and the interrupt process;
After the first interrupt processing step, the interrupt processing data stored in the second storage means or the processing data excluding the initial data is acquired to continue the interrupt processing, and the interrupt A second interrupt processing step for performing processing for switching the acquisition destination of data for processing from the first storage means to the second storage means;
Information processing method including: The first storage means, information processing method according to claim 4 Symbol mounting a backup memory which is backed up by non-volatile memory or power. The first storage means, information processing method according to claim 4 Symbol mounting a boot ROM for storing boot code.

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