JPH06119257A - Large scale integrated circuit incorporating internal state saving structure - Google Patents

Large scale integrated circuit incorporating internal state saving structure

Info

Publication number
JPH06119257A
JPH06119257A JP4268373A JP26837392A JPH06119257A JP H06119257 A JPH06119257 A JP H06119257A JP 4268373 A JP4268373 A JP 4268373A JP 26837392 A JP26837392 A JP 26837392A JP H06119257 A JPH06119257 A JP H06119257A
Authority
JP
Japan
Prior art keywords
internal state
lsi
power source
turned
external memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4268373A
Other languages
Japanese (ja)
Inventor
Yukihiro Yoshida
幸弘 吉田
Kenji Kawahara
健児 川原
Noboru Kubo
登 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4268373A priority Critical patent/JPH06119257A/en
Publication of JPH06119257A publication Critical patent/JPH06119257A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

PURPOSE:To dispense with an external memory and an external memory power source, and to decrease a delay time at the time of start and stop of the whole system by incorporating an internal state saving structure for resetting an internal state from a storage means when reset of the internal state is instructed. CONSTITUTION:The large scale integrated circuit(LSI) 10 is provided with a flash memory 12 being a storage means for saving an internal state 11 of the LSI 10, a data copying circuit 13 being a data moving means for reading and writing the internal state 11 to the flash memory 12, and a circuit 14 which does not contain the internal state. In such a state, when the system for restarting an operation from a state at the time when a power source is turned on when the power source is turned on by using the LSI 10 is constructed, since the LSI 10 incorporates a saving structure of the internal state 11, an external memory and an external memory power source except the power source of the LSI 10 main body become unnecessary. Also, when the power source is disconnected, and the power source is turned on, the internal state of the LSI 10 is not transferred to the outside of a chip, therefore, a delay time at the time of rise and fall of the whole system becomes small.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、内部状態退避構造を内
蔵した大規模集積回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large scale integrated circuit containing an internal state saving structure.

【0002】[0002]

【従来の技術】従来の大規模集積回路(以下、LSIと
称する)では、電源切断時にレジスタやランダム・アク
セス・メモリ(RAM)などに格納されていた内部状態
が失われてしまう。従って、LSIを用いて電源投入時
に電源切断時の状態から動作を再開するシステムを構築
するには、電源切断時にLSI40の内部状態41をチップ
外部に読み出して外部メモリ42に格納し、電源投入時に
LSI40の内部状態41を外部メモリ42から取り出してチ
ップ内部に再び書き込むという操作が必要であった。そ
こで従来のLSIを用いて電源投入時に電源切断時の状
態から動作を再開するシステムを構築するには、図7に
示すように、LSI40の電源43以外に、LSI40の内部
状態41を格納するための外部メモリ42及び外部メモリ42
がデータを保持するための外部メモリ用電源44を設ける
必要がある。
2. Description of the Related Art In a conventional large-scale integrated circuit (hereinafter referred to as an LSI), the internal state stored in a register, a random access memory (RAM) or the like is lost when the power is turned off. Therefore, in order to construct a system that uses LSI to restart the operation from the state when the power is turned off when the power is turned on, the internal state 41 of the LSI 40 is read outside the chip when the power is turned off and stored in the external memory 42, and when the power is turned on. It was necessary to take out the internal state 41 of the LSI 40 from the external memory 42 and write it again in the chip. Therefore, in order to construct a system that resumes the operation from the state when the power is turned off when the power is turned on by using the conventional LSI, as shown in FIG. 7, the internal state 41 of the LSI 40 is stored in addition to the power source 43 of the LSI 40. External memory 42 and external memory 42
Need to provide an external memory power supply 44 for holding data.

【0003】[0003]

【発明が解決しようとする課題】上述した従来のLSI
を用いた電源投入時に電源切断時の状態から動作を再開
するシステムでは、LSIの内部状態を格納するための
外部メモリ及び外部メモリがデータを保持するための外
部メモリ用電源を設ける必要があり、システム構成が複
雑になるという問題点があった。また、電源切断、電源
投入時にLSIの内部状態をチップ外部に転送する操作
に長い時間がかかり、システム全体の立ち上げ、立ち下
げ時の遅延時間が大きくなるという問題点があった。
DISCLOSURE OF THE INVENTION The conventional LSI described above
In a system that restarts the operation from the state when the power is turned off when the power is turned on, it is necessary to provide an external memory for storing the internal state of the LSI and an external memory power source for the external memory to hold data. There is a problem that the system configuration becomes complicated. In addition, there is a problem in that it takes a long time to transfer the internal state of the LSI to the outside of the chip when the power is turned off and turned on, and the delay time at the time of starting and shutting down the entire system increases.

【0004】本発明は、上述した従来のLSIを用いた
システムにおける問題点に鑑み、システム構成が簡単
で、電源切断時及び電源投入時のLSIの操作時間を短
縮でき、システム全体の立ち上げ及び立ち下げをスム−
ズに行うことができるLSIを提供する。
In view of the above-mentioned problems in the system using the conventional LSI, the present invention has a simple system configuration and can reduce the operation time of the LSI at the time of turning off the power and turning on the power, thereby starting up the entire system. Shut down
To provide an LSI that can be performed.

【0005】[0005]

【課題を解決するための手段】本発明は、内部状態を退
避するための記憶手段と、内部状態を記憶手段へ読み書
きするためのデータ移動手段とを備えており、データ移
動手段により内部状態の退避が指示されたときに内部状
態を記憶手段に退避し、内部状態の復帰が指示されたと
きに記憶手段から内部状態を復帰する内部状態退避構造
を内蔵した大規模集積回路によって達成される。
The present invention comprises storage means for saving the internal state and data moving means for reading / writing the internal state from / to the storage means. This is achieved by a large-scale integrated circuit having an internal state saving structure that saves the internal state in the storage unit when the saving is instructed and restores the internal state from the storage unit when the internal state is instructed.

【0006】[0006]

【作用】本発明の大規模集積回路では、記憶手段は内部
状態を退避し、データ移動手段は内部状態を記憶手段へ
読み書きして、データ移動手段により内部状態の退避が
指示されたときに内部状態を記憶手段に退避し、内部状
態の復帰が指示されたときに記憶手段から内部状態を復
帰する。
In the large scale integrated circuit of the present invention, the storage means saves the internal state, the data moving means reads / writes the internal state from / to the storage means, and when the data moving means instructs the saving of the internal state, the internal state is saved. The state is saved in the storage means, and the internal state is restored from the storage means when the restoration of the internal state is instructed.

【0007】[0007]

【実施例】以下、図面を参照して、本発明の大規模集積
回路(以下、LSIと称する)の実施例を詳細に説明す
る。
Embodiments of the large-scale integrated circuit (hereinafter referred to as LSI) of the present invention will be described in detail below with reference to the drawings.

【0008】図1は、本発明のLSIの一実施例の構成
を示すブロック図である。
FIG. 1 is a block diagram showing the configuration of an embodiment of the LSI of the present invention.

【0009】図1のLSI10は、LSI10の内部状態11
を退避するための記憶手段であるフラッシュメモリ12、
内部状態11をフラッシュメモリ12に読み書きするための
デ−タ移動手段であるデータコピー回路13、及び内部状
態を含まない回路14を備えている。
The LSI 10 shown in FIG. 1 is an internal state 11 of the LSI 10.
Flash memory 12, which is a storage means for saving
A data copy circuit 13, which is a data moving means for reading / writing the internal state 11 from / into the flash memory 12, and a circuit 14 not including the internal state are provided.

【0010】次に、図2を参照して、図1のLSI10の
動作を説明する。
Next, the operation of the LSI 10 shown in FIG. 1 will be described with reference to FIG.

【0011】図1のLSI10では、データコピー回路13
は、内部状態退避が指示されたとき内部状態11をフラッ
シュメモリ12に退避し(図2(a)参照)、内部状態復
帰が指示されたとき内部状態11をフラッシュメモリ12か
ら復帰する(図2(b)参照)。
In the LSI 10 of FIG. 1, the data copy circuit 13
Saves the internal state 11 to the flash memory 12 when the internal state save is instructed (see FIG. 2A), and restores the internal state 11 from the flash memory 12 when the internal state restore is instructed (see FIG. 2). (See (b)).

【0012】図3は、図1のLSIを適用した電卓用1
チップマイクロコンピュ−タ(以下、マイコンと称す
る)の一構成例を示すブロック図である。
FIG. 3 shows a calculator 1 to which the LSI of FIG. 1 is applied.
It is a block diagram showing an example of 1 composition of a chip microcomputer (henceforth a microcomputer).

【0013】図3のマイコンは、レジスタ群15、演算器
(ALU)16、データ用ランダム・アクセス・メモリ
(RAM)17、フレームメモリ18、各部分回路用のデー
タコピー回路19〜22、各部分回路の内部状態を格納する
ためのフラッシュメモリ23〜26、命令デコ−ダ27、リ−
ド・オンリ−・メモリ(ROM)28、キ−入力制御回路
29、及び液晶ドライバ30によって構成されている。
The microcomputer of FIG. 3 includes a register group 15, an arithmetic unit (ALU) 16, a data random access memory (RAM) 17, a frame memory 18, data copy circuits 19 to 22 for each partial circuit, and each part. Flash memories 23 to 26 for storing the internal state of the circuit, instruction decoder 27, reader
Dedicated memory (ROM) 28, key input control circuit
29 and a liquid crystal driver 30.

【0014】上記レジスタ群15には、プログラムカウン
タ、制御レジスタ、演算レジスタ、汎用レジスタが含ま
れる(図示省略)。
The register group 15 includes a program counter, a control register, an arithmetic register, and a general-purpose register (not shown).

【0015】マイコンを構成する部分回路のうち、レジ
スタ群15、ALU16、データ用RAM17、フレームメモ
リ18については、図に示すように、それぞれの部分回路
の内部状態を格納するためのデータコピー回路19〜22及
びフラッシュメモリ23〜26を設ける。
Of the partial circuits constituting the microcomputer, the register group 15, the ALU 16, the data RAM 17, and the frame memory 18 are, as shown in the figure, a data copy circuit 19 for storing the internal state of each partial circuit. 22 and flash memories 23 to 26 are provided.

【0016】図4を参照して、図3のマイコンの内部状
態の退避動作を説明する。
The saving operation of the internal state of the microcomputer shown in FIG. 3 will be described with reference to FIG.

【0017】まず、マイコンの命令セットに内部状態の
退避、復帰を指示する命令を用意する。
First, an instruction for saving and restoring the internal state is prepared in the instruction set of the microcomputer.

【0018】これらの命令は、命令デコーダ27でデコー
ドされると、図4に示す制御信号31を変化させる。
When these instructions are decoded by the instruction decoder 27, they change the control signal 31 shown in FIG.

【0019】データコピー回路19〜22は、制御信号31を
入力して、図2の動作原理に基づいて動作する。即ち、
制御信号31が内部状態退避のとき各部分回路の内部状態
を各部分回路用のフラッシュメモリ23〜26に退避し、制
御信号31が内部状態復帰のとき各部分回路用の内部状態
を各部分回路用のフラッシュメモリ23〜26から復帰す
る。
The data copy circuits 19 to 22 receive the control signal 31 and operate based on the operation principle of FIG. That is,
When the control signal 31 saves the internal state, the internal states of each partial circuit are saved in the flash memories 23 to 26 for each partial circuit, and when the control signal 31 returns the internal state, the internal state of each partial circuit is changed to each partial circuit. Restore from flash memory 23-26 for.

【0020】次に、図5のフロ−チャ−トを参照して、
図3のマイコンにおける内部状態の退避、復帰の動作タ
イミングを説明する。
Next, referring to the flow chart of FIG.
The operation timing of saving and restoring the internal state in the microcomputer of FIG. 3 will be described.

【0021】まず、表示ル−チンを実行し(ステップS
1)、電卓の特定キーが押されたか否かを判定し(ステ
ップS2)、上記ステップS2で特定キーが押された
(YES)と判定されたときは、内部状態の退避、復帰
を実行し(ステップS3)、後述するステップS4へ進
む。他方、上記ステップS2で特定キーが押されていな
い(NO)と判定されたときは、演算ル−チンを実行し
(ステップS4)、電卓の特定キーが押されたか否かを
判定し(ステップS5)、上記ステップS5で特定キー
が押された(YES)と判定されたときは、内部状態の
退避、復帰を実行し(ステップS6)、後述するステッ
プS7へ進む。他方、上記ステップS5で特定キーが押
されていない(NO)と判定されたときは、演算ル−チ
ンが終了したか否かを判定し(ステップS7)、上記ス
テップS7で演算ル−チンが終了している(YES)と
判定されたときは上記ステップS1に戻り、上記ステッ
プS7で演算ル−チンが終了していない(NO)と判定
されたときは上記ステップS4に戻る。
First, the display routine is executed (step S
1) It is determined whether or not a specific key of the calculator is pressed (step S2). When it is determined that the specific key is pressed (YES) in step S2, the internal state is saved and restored. (Step S3), the process proceeds to step S4 described later. On the other hand, when it is determined in step S2 that the specific key is not pressed (NO), a calculation routine is executed (step S4), and it is determined whether the specific key of the calculator is pressed (step S4). S5) If it is determined in step S5 that the specific key is pressed (YES), the internal state is saved and restored (step S6), and the process proceeds to step S7 described later. On the other hand, when it is determined in step S5 that the specific key is not pressed (NO), it is determined whether or not the calculation routine is finished (step S7), and the calculation routine is determined in step S7. When it is determined that the calculation routine is completed (YES), the process returns to step S1. When it is determined that the calculation routine is not completed (NO) in step S7, the process returns to step S4.

【0022】上記ステップをまとめると、電源切断前の
終了処理時に内部状態を退避し、電源投入後の初期化時
に内部状態を待避する。そして、電卓の特定のキーが押
されたときに内部状態の退避、復帰を行う。
To summarize the above steps, the internal state is saved during the termination process before the power is turned off, and the internal state is saved during the initialization after the power is turned on. Then, when a specific key of the calculator is pressed, the internal state is saved and restored.

【0023】図6に示すように、本発明のLSI10を用
いて電源投入時に電源切断時の状態から動作を再開する
システムを構築すると、本発明のLSI10が内部状態11
の退避構造を内蔵しているのでLSI10本体の電源32以
外の、外部メモリと外部メモリ用電源が不要になる。ま
た、電源切断、電源投入時にLSI10の内部状態をチッ
プ外部に転送しないので、システム全体の立ちあげ、立
ち下げ時の遅延時間が小さくなる。
As shown in FIG. 6, if a system is constructed using the LSI 10 of the present invention to restart the operation from the state when the power is turned off when the power is turned on, the LSI 10 of the present invention will have an internal state 11
Since the evacuation structure is built in, an external memory and an external memory power supply other than the power supply 32 of the LSI 10 main body are unnecessary. In addition, since the internal state of the LSI 10 is not transferred to the outside of the chip when the power is turned off or turned on, the delay time at the time of starting and shutting down the entire system is reduced.

【0024】これらの特徴は、本発明のLSIが電源制
御をきめ細かく行い省消費電力を図る携帯型機器の構成
要素をとして使用されたときに特に有効となる。
These characteristics are particularly effective when the LSI of the present invention is used as a constituent element of a portable device for finely controlling power supply and saving power consumption.

【0025】[0025]

【発明の効果】本発明の大規模集積回路は、内部状態を
退避するための記憶手段と、内部状態を記憶手段へ読み
書きするためのデータ移動手段とを備えており、データ
移動手段により内部状態の退避が指示されたときに内部
状態を記憶手段に退避し、内部状態の復帰が指示された
ときに記憶手段から内部状態を復帰する内部状態退避構
造を内蔵しているので、外部メモリと外部メモリ用電源
が不要になる。また、電源切断、電源投入時にLSIの
内部状態をチップ外部に転送しないので、システム全体
の立ちあげ、立ち下げ時の遅延時間が小さくなる。
The large-scale integrated circuit of the present invention is provided with the storage means for saving the internal state and the data moving means for reading / writing the internal state from / to the storage means. The internal state saving structure that saves the internal state to the storage means when the saving of the internal state is instructed and restores the internal state from the storage means when the internal state is instructed is built-in. No power supply for memory is needed. In addition, since the internal state of the LSI is not transferred to the outside of the chip when the power is turned off or turned on, the delay time at the time of starting and shutting down the entire system is reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の大規模集積回路の一実施例の構成を示
すブロック図である。
FIG. 1 is a block diagram showing a configuration of an embodiment of a large scale integrated circuit of the present invention.

【図2】図1のデータコピー回路の動作説明図である。FIG. 2 is an operation explanatory diagram of the data copy circuit of FIG.

【図3】図1の大規模集積回路を適用した電卓用1チッ
プマイコンの一構成例を示すブロック図である。
3 is a block diagram showing a configuration example of a one-chip microcomputer for a calculator to which the large scale integrated circuit of FIG. 1 is applied.

【図4】図3のデータコピー回路の制御方法の説明図で
ある。
FIG. 4 is an explanatory diagram of a control method of the data copy circuit of FIG.

【図5】図3の電卓用1チップマイコンの動作を説明す
るためのフローチャートである。
5 is a flowchart for explaining the operation of the calculator 1-chip microcomputer in FIG. 3. FIG.

【図6】図1のLSIを用いたシステムの一構成例を示
すブロック図である。
6 is a block diagram showing a configuration example of a system using the LSI of FIG.

【図7】従来のLSIを用いたシステムの一構成例を示
すブロック図である。
FIG. 7 is a block diagram showing a configuration example of a system using a conventional LSI.

【符号の説明】[Explanation of symbols]

10 大規模集積回路(LSI) 11 内部状態 12 フラッシュメモリ 13 デ−タコピ−回路 14 内部状態を含まない回路 10 Large scale integrated circuit (LSI) 11 Internal state 12 Flash memory 13 Data copy circuit 14 Circuit not including internal state

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 内部状態を退避するための記憶手段と、
前記内部状態を前記記憶手段へ読み書きするためのデー
タ移動手段とを備えており、前記データ移動手段により
前記内部状態の退避が指示されたときに該内部状態を前
記記憶手段に退避し、前記内部状態の復帰が指示された
ときに前記記憶手段から該内部状態を復帰することを特
徴とする内部状態退避構造を内蔵した大規模集積回路。
1. A storage unit for saving an internal state,
A data moving unit for reading / writing the internal state from / to the storage unit, and saving the internal state to the storage unit when the data moving unit gives an instruction to save the internal state, A large-scale integrated circuit having an internal state saving structure, wherein the internal state is restored from the storage means when an instruction to restore the state is given.
JP4268373A 1992-10-07 1992-10-07 Large scale integrated circuit incorporating internal state saving structure Pending JPH06119257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4268373A JPH06119257A (en) 1992-10-07 1992-10-07 Large scale integrated circuit incorporating internal state saving structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4268373A JPH06119257A (en) 1992-10-07 1992-10-07 Large scale integrated circuit incorporating internal state saving structure

Publications (1)

Publication Number Publication Date
JPH06119257A true JPH06119257A (en) 1994-04-28

Family

ID=17457599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4268373A Pending JPH06119257A (en) 1992-10-07 1992-10-07 Large scale integrated circuit incorporating internal state saving structure

Country Status (1)

Country Link
JP (1) JPH06119257A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010217941A (en) * 2009-03-13 2010-09-30 Rohm Co Ltd Data processor
JP2010267136A (en) * 2009-05-15 2010-11-25 Rohm Co Ltd Data processor
JP2012256404A (en) * 2011-03-08 2012-12-27 Semiconductor Energy Lab Co Ltd Memory element and signal processing circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010217941A (en) * 2009-03-13 2010-09-30 Rohm Co Ltd Data processor
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JP2012256404A (en) * 2011-03-08 2012-12-27 Semiconductor Energy Lab Co Ltd Memory element and signal processing circuit
US9508448B2 (en) 2011-03-08 2016-11-29 Semiconductor Energy Laboratory Co., Ltd. Memory element and signal processing circuit
US9767862B2 (en) 2011-03-08 2017-09-19 Semiconductor Energy Laboratory Co., Ltd. Memory element and signal processing circuit

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