JP2007108402A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing power consumed during a regular operation and reset of a power source and capable of shortening a starting time. <P>SOLUTION: In a regular mode, a control section 12 exerts control such that data stored in a SRAM 19 provided in association with a functional block 17 is retracted into a context holder section 13 and thereafter the supply of power to the corresponding block 17 is stopped. When the regular mode is reset from a power-saving mode, the control section 12 exerts control such that the supply of power to the block 17 is resumed, the data retracted in the context holder section 13 is restored into the SRAM 19, and the supply of power to the context holder section 13 is stopped. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, for example, an application specific semiconductor integrated circuit (ASIC) for controlling an image forming apparatus.

  In recent image forming apparatuses, in order to save power, a power saving mode is adopted in which not only a fixing unit that consumes a large amount of power during standby but also all or most of the power supply of the system is shut off. On the other hand, if the return time when returning from the standby state becomes long, the convenience is deteriorated. When the power is restored, it is necessary to initialize the control unit centered on the CPU. Since the conventional fixing unit took several minutes to restore, there was no problem even if it took several seconds to initialize the control unit. However, recently, the restoration time of the fixing unit has become several seconds, and the time required for initialization of the control unit greatly depends on the restoration time of the entire system.

  As an example for shifting to the power saving mode, there is a method of stopping the supply of the clock signal to the control unit. The method of stopping the supply of the clock signal to the control unit is in the energized state, and thus there is an advantage that various information in the control unit is retained, but the leak current continues to flow. In particular, recently, since a fine pattern of 90 nm or 65 nm is used in the semiconductor manufacturing process by the deep submicron design method, the ratio of the leakage current to the total consumption current increases. For this reason, the power saving effect as expected in the power saving mode by stopping the clock cannot be expected.

Japanese Patent Laid-Open No. 2004-78043 (Patent Document 1) discloses a device in which the value of a register group is copied to a non-volatile memory when the power of the image forming apparatus is shut down, so that the apparatus is kept in a state where the power is turned off at the next power-on. The image forming apparatus is described in which the recovery time is shortened so that the recovery time is increased.
Japanese Unexamined Patent Publication No. 2004-78043 (paragraph numbers 0040 and 0041, FIG. 1)

  In the power saving mode, it is necessary to cut off the power supply as much as possible, except for circuits that need to receive an interrupt signal from the outside of each function. Even in the normal operation mode, it is preferable that the circuit that operates only in the power saving mode cuts off the power supply. The image forming apparatus described in Patent Document 1 describes saving of data when the power is shut off. However, regarding saving of data in the power saving mode and restoring of data when the power is restored. Not listed.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of reducing power consumption during normal operation and power recovery and shortening the startup time.

  The present invention relates to a semiconductor integrated circuit including a functional block circuit in which power is cut off in a power saving mode and power is supplied in a normal mode. The semiconductor integrated circuit is provided in association with the functional block circuit. Stored in the first storage means in response to the power saving mode being entered. After the stored data is saved in the second storage means, the power supply to the functional block is cut off, and the power supply to the functional block is resumed when the normal mode is restored from the power saving mode. Control means for storing the saved data in the first storage means.

  Preferably, the control means supplies power to the second storage means in the power saving mode to save the data in the first storage means, and saves the data saved in the second storage means in the normal operation to the first storage means. Then, the power supply to the second storage means is cut off.

  Preferably, the first storage means and the second storage means store data according to the clock signal, and the clock signal supplied to the second storage means is compared with the clock signal supplied to the first storage means. And a low-speed clock signal.

  Preferably, the first storage unit and the control unit are built in the application-specific semiconductor integrated circuit, and the second storage unit is externally attached to the application-specific semiconductor integrated circuit.

  Preferably, the externally attached second storage means can read data stored from the outside.

  According to the present invention, in the normal mode, after the data stored in the first storage means provided in association with the functional block is saved in the second storage means, power is supplied to the functional block. When the normal mode is restored from the power saving mode, the power supply to the functional block is resumed, and the data saved in the second storage means is stored in the first storage means. It is possible to reduce the power consumption when the power is restored, save the data in the power saving mode, and restore the data when the power is restored to shorten the startup time.

  FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, an application specific semiconductor integrated circuit (hereinafter referred to as ASIC) 1 is a controller that processes an image in an image forming apparatus, for example, and includes a clock generation unit 10, a CPU core 11, a control unit 12, A context holding unit 13, power supply stop correspondence blocks 14 and 15, and a constant power supply block 16 are included.

  The clock generation unit 10 generates a clock signal and supplies it to the CPU core 11, the context holding unit 13, and the power supply stop corresponding blocks 14 and 15. The context holding unit 13 is configured by using, for example, an SRAM as a second storage unit, and a clock signal supplied to the SRAM is a clock signal that is slower than clock signals supplied to other functional blocks. is there. By using such a low-speed clock signal, power consumption in the context holding unit 13 in the power saving mode can be reduced. The CPU core 11 is loaded with a program from the external ROM 2. Note that initial data can be set from the CPU core 11 to the SRAMs 19 and 20.

  The control unit 12 performs switching control of operation modes of the power supply stop corresponding blocks 14 and 15. In the normal operation, the context holding unit 13 is cut off from the power supply. In the power saving mode, the context holding unit 13 is supplied with power and stores various data (context) immediately before the power supply stop corresponding blocks 14 and 15. Transfer data to and from. The power supply stop corresponding blocks 14 and 15 are functional blocks in which power supply is stopped in response to an instruction to shift to the power saving mode by the power saving mode control signal from the control unit 12.

  The power supply stop corresponding blocks 14 and 15 include functional blocks 17 and 18 and SRAMs 19 and 20 as first storage means, respectively. The functional blocks 17 and 18 have, for example, compression and expansion functions. The SRAMs 19 and 20 hold the data of the corresponding functional blocks 17 and 18 and output the held data to the control unit 12 according to the power saving mode control signal. This data is held by the context holding unit 13.

  The constant power supply block 16 is always supplied with power even in the power saving mode, and a print request signal is input irregularly from a host computer (not shown). The constant power supply block 16 includes a functional block 21 that provides an interrupt signal to the CPU core 11 in order to notify the presence of received data in response to a print request signal even when the ASIC 1 is set to the power saving mode.

  FIG. 2 is a diagram showing a data flow at the time of transition to the power saving mode of the semiconductor integrated circuit in one embodiment of the present invention, and FIG. 3 is a flowchart showing an operation of the control unit at the time of transition to the power saving mode, FIG. 4 is a flowchart showing the operation of the control unit when returning from the power saving mode.

  Next, the operation of the ASIC in one embodiment of the present invention will be described with reference to FIGS. The control unit 12 determines various information such as an operation status of the image forming apparatus, an input status of print data, or an instruction from a user, and determines whether to shift the ASIC 1 to the power saving mode. If it is determined that the mode is the transition to the power saving mode, power supply from the power supply unit (not shown) to the context holding unit 13 is started in step (abbreviated as SP in the drawing) SP1 shown in FIG. In step SP2, a power saving mode control signal is given from the control unit 12 to the CPU core 11 and the power supply stop corresponding blocks 14 and 15 to instruct transition to the power saving mode.

  In response to the power saving mode control signal being given, the CPU core 11 monitors the current job in step SP3 and determines whether or not it is possible to immediately shift to the power saving mode. If the job is being executed, it waits until the job is completed. If the job is completed, the SRAM 19 of the power supply stop corresponding block 14 is actively accessed in step SP4, and the information stored in the SRAM 19 is stored. Suck up. In step SP5, the information is transferred to the context holding unit 13. In step SP6, the power supply to the power supply stop corresponding block 14 is stopped, and the power saving mode is entered.

  FIG. 2 shows the flow of this series of data. In the above description, the operation for setting the power supply stop corresponding block 14 to the power saving mode has been described. However, the operation for setting the power supply stop corresponding block 15 to the power saving mode is also performed in parallel, and data stored in the corresponding SRAM 20 is stored. Is saved in the context holding unit 13.

  When shifting to the return mode during the power saving mode operation, the process shown in FIG. 4 is performed. When a print request signal is given from the host computer or when there is a request for returning to the normal operation mode from the user, the control unit 12 determines in step SP11 that there is a request to return to the normal mode, In SP12, the power supply to the power supply stop corresponding block 14 is resumed. In step SP13, the control unit 12 restores the data from the context holding unit 13 to the SRAM 19, and in step SP14, sets the built-in data restore completion flag. Thereafter, in step SP15, the power supply to the context holding unit 13 is stopped to reduce power consumption.

  On the other hand, if it is determined in step SP11 that there is a request to return to the normal mode, the control unit 12 instructs the CPU core 11 to shift to the normal mode in step SP16. When the CPU core 11 returns to the normal mode, the data restoration completion flag in the control unit 12 is monitored in step SP17, and when it is confirmed that the flag is set, the return to the normal mode is completed. Similarly, when the power supply stop corresponding block 15 is set to the power saving mode, the data held in the context holding unit 13 can be restored to the SRAM 20 to return to the normal mode.

  As described above, according to this embodiment, when shifting to the power saving mode, the data of the SRAMs 19 and 20 of the power supply stop corresponding blocks 14 and 15 are saved in the context holding unit 13 and when returning to the normal mode, the context holding is performed. Since the data saved in the unit 13 is restored to the SRAMs 19 and 20, there is no need to reset the data in the SRAMs 19 and 20 by the CPU core 11, and the time required for shifting the image forming apparatus from the power saving mode to the normal mode. Can be shortened.

  Further, immediately after the data in the SRAMs 19 and 20 is saved in the context holding unit 13, the power supply to the power supply stop corresponding blocks 14 and 15 is cut off, and the power supply is resumed immediately after the data is restored in the SRAMs 19 and 20. As a result, it is possible to reduce power consumption while shortening the time for shifting from the power saving mode to the normal mode.

  Furthermore, power consumption can be reduced by using an SRAM that operates with a low-speed clock signal as the context holding unit 13.

  The context holding unit 13 may be configured by an external memory connected to the ASIC 1 without being built in the ASIC 1, and external reading may be possible. In this case, when a problem occurs in the image forming apparatus, Since the last set value after setting the power saving mode is left in the external memory, it can be used for investigating the cause of the failure.

  As mentioned above, although embodiment of this invention was described with reference to drawings, this invention is not limited to the thing of embodiment shown in figure. Various modifications and variations can be made to the illustrated embodiment within the same range or equivalent range as the present invention.

1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention. It is a figure which shows the data flow at the time of transfer to the power saving mode of the semiconductor integrated circuit in one Embodiment of this invention. It is a flowchart which shows operation | movement of the control part at the time of transfer to power saving mode. It is a flowchart which shows operation | movement of the control part at the time of the return from power saving mode.

Explanation of symbols

  1 ASIC, 2 ROM, 10 clock generation unit, 11 CPU core, 12 control unit, 13 context holding unit, 14, 15 power supply stop support block, 16 always power supply block, 17, 18, 21 function block, 19, 20 SRAM.

Claims (5)

A semiconductor integrated circuit with a built-in functional block circuit that is powered off in power saving mode and powered in normal mode,
First storage means provided in association with the functional block and storing data related to the functional block circuit in the normal mode;
Second storage means capable of holding data in the power saving mode;
In response to the power saving mode, after the data stored in the first storage means is saved in the second storage means, the power supply to the functional block is shut off, and the power saving mode A semiconductor integrated circuit comprising: control means for storing data saved in the second storage means in the second storage means after resuming power supply to the functional block at the time of return from the normal mode.   The control means supplies power to the second storage means in the power saving mode to save the data in the first storage means, and saves the data saved in the second storage means in the normal operation. 2. The semiconductor integrated circuit according to claim 1, wherein power supply to said second storage means is cut off after transfer to the first storage means. The first storage means and the second storage means store data according to a clock signal,
3. The semiconductor integrated circuit according to claim 1, wherein the clock signal applied to the second storage unit is a clock signal that is slower than the clock signal applied to the first storage unit. The first storage means and the control means are built in a semiconductor integrated circuit for specific applications,
4. The semiconductor integrated circuit according to claim 1, wherein the second storage unit is externally attached to the application-specific semiconductor integrated circuit. 5. 5. The semiconductor integrated circuit according to claim 4, wherein said externally attached second storage means is capable of reading data stored from outside.

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