JP2004070854A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor easily realizing low power consumption as a whole by reducing power consumption of an on-chip nonvolatile memory itself. <P>SOLUTION: The data processor (1) has a central processing unit (2), a RAM (8) and the rewritable nonvolatile memory (7) on a semiconductor chip. A predetermined program is transferred to the RAM from the nonvolatile memory during a power-on reset. After resetting, transition is allowed to a low power consumption mode of executing the program of the RAM by the central processing unit in a state of stopping operation of the nonvolatile memory. Since the program is transferred during resetting, the power consumption by the on-chip nonvolatile memory as an inherent function of a microcomputer is reduced, and the low power consumption of the microcomputer as a whole can be realized without relying on a user program. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to reducing the power consumption of a data processor having a central processing unit, a RAM, and a rewritable nonvolatile memory in a semiconductor chip. Related to effective technology applied to computers.
[0002]
[Prior art]
Japanese Patent Laying-Open No. 11-288409 describes a microcomputer in which a program stored in a flash memory is transferred to a RAM, a clock is switched from a high frequency to a low frequency, and the flash memory is stopped.
[0003]
Japanese Patent Laying-Open No. 2001-232431 discloses a microcomputer in which a program in a nonvolatile memory is transferred to a RAM when power is turned on.
[0004]
Japanese Patent Laying-Open No. 4-239349 discloses a microcomputer in which a system program in a ROM is transferred to a RAM when power is turned on.
[0005]
[Problems to be solved by the invention]
The present inventors have studied low power consumption of a microcomputer in which an electrically rewritable flash memory is on-chip. According to this, the flash memory not only requires a high voltage for erasing and writing, but also requires a relatively high level word line voltage for a read operation and a verify operation. Therefore, since the power consumption by the timing generator, the charge pump circuit for internal boosting, and the like is relatively large, the flash memory consumes a relatively large amount of power only by keeping it operable. Under such circumstances, even if the microcomputer is operated at a low clock frequency such as 32 kHz of the clock timer circuit in the low power consumption mode of the microcomputer, the comparison is performed as long as the flash memory is operable. Enormous power is consumed. The inventor of the present invention, when operating a microcomputer at a low-speed clock frequency such as 32 KHz of a clock timer circuit, transfers a program from a flash memory to a RAM, causes the CPU to execute the program in the RAM, and executes the operation of the flash memory. Was considered to be able to stop. As a result of further study, the present inventor has determined that in order to maximize the effect of low power consumption, transfer of the program and flash memory as functions unique to the microcomputer without depending on the user program. It has been found that it is advantageous to realize the operation stoppage.
[0006]
An object of the present invention is to provide a data processor which can easily reduce power consumption by an on-chip nonvolatile memory itself and realize low power consumption as a whole.
[0007]
Another object of the present invention is to provide, as a function unique to a microcomputer, data that can reduce power consumption by an on-chip nonvolatile memory and realize low power consumption as a whole without depending on a user program. It is to provide a processor.
[0008]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0010]
[1] A data processor according to the present invention has a central processing unit, a RAM, and a rewritable nonvolatile memory on a semiconductor chip, and stores a predetermined program from the nonvolatile memory to the RAM during a power-on reset. After the transfer is performed and the reset is released, a transition to the low power consumption mode in which the central processing unit executes the program of the RAM while the operation of the nonvolatile memory is stopped is enabled. Since the program is transferred during the reset, the power consumption by the on-chip nonvolatile memory is reduced as a function unique to the microcomputer without depending on the user program, thereby realizing low power consumption of the entire microcomputer. be able to.
[0011]
The power-on reset is instructed by, for example, assertion of an external reset signal. The reset release is performed, for example, by releasing the internal reset instruction after the reset signal is negated.
[0012]
As a specific mode, the transition to the low power consumption mode is enabled after executing reset exception processing after reset release. This transition is performed in accordance with a user program or an instruction from the outside, but the microcomputer itself is prepared to be able to immediately transition to the low power consumption mode when instructed.
[0013]
As another specific mode, the reset exception processing itself after reset release is set to the low power consumption mode. The low power consumption mode is set from the beginning, and the effect of low power consumption can be maximized. In this case, the RAM program executed after the reset release includes the exception handling and interrupt handling vector and the reset exception handling program.
[0014]
To facilitate the program transfer, it is desirable to have a transfer control circuit for controlling transfer of a predetermined program from the nonvolatile memory to the RAM.
[0015]
The microcomputer is allowed to transition to a normal operation mode in which the central processing unit executes the program of the nonvolatile memory. At this time, in the low power consumption mode, the central processing unit is operated in synchronization with a clock signal of a first frequency, and in the normal operation mode, the central processing unit operates as a lock signal of a second frequency higher than the first frequency. Operates synchronously.
[0016]
[2] A data processor according to another aspect of the present invention includes a central processing unit, a RAM, and a rewritable nonvolatile memory on a semiconductor chip, and stores a predetermined amount of data from the nonvolatile memory to the RAM during a power-on reset. The central processing unit executes the program of the RAM to perform a reset exception process in a state where the operation of the nonvolatile memory is stopped after the reset is released, and thereafter, the central processing unit executes the transfer of the RAM. And a normal operation mode in which the central processing unit executes the program in the nonvolatile memory. Since the program is transferred during reset, the power consumption of the on-chip nonvolatile memory is reduced as a function unique to the microcomputer without depending on the user program, thereby realizing low power consumption of the entire microcomputer. Can be. Since the RAM program is executed from the reset exception processing after reset release, the low power consumption mode is set from the beginning, and the effect of low power consumption can be maximized.
[0017]
In the reset exception processing and the low power consumption mode, the central processing unit is operated in synchronization with a clock signal of a first frequency, and in the normal operation mode, the central processing unit is synchronized with a clock signal of a second frequency higher than the first frequency. It is operated synchronously. Low power consumption is also achieved in terms of the clock frequency of the central processing unit.
[0018]
[3] A data processor according to still another aspect of the present invention has a central processing unit, a RAM, and a rewritable nonvolatile memory on a semiconductor chip, and transfers the data from the nonvolatile memory to the RAM during a power-on reset. A predetermined program is transferred, and after the reset is released, the central processing unit executes the program of the RAM and performs a reset exception process in a state where the operation of the nonvolatile memory is stopped. Since the program is transferred during reset, the power consumption of the on-chip nonvolatile memory is reduced as a function unique to the microcomputer without depending on the user program, thereby realizing low power consumption of the entire microcomputer. Can be. Since the RAM program is executed from the reset exception processing after reset release, the low power consumption mode is set from the beginning, and the effect of low power consumption can be maximized.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a microcomputer which is an example of a data processor according to the present invention. Although not particularly limited, the microcomputer 1 shown in FIG. 1 has a central processing unit (CPU) 2 that controls the entire control, a bus controller 3, a data transfer control circuit 4, an interrupt controller 5, a system controller 6, a rewritable nonvolatile memory. A flash memory 7, a RAM 8, a clock timer 9, and other peripheral circuits 10, an oscillation control circuit 11, a main oscillator 12, a sub oscillator 13, a selector 14, a module stop control register 16, and an internal bus 15 It is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon by a known CMOS integrated circuit manufacturing technique. The system controller 6 has a power supply voltage monitoring circuit 20, an oscillation stabilization counter 21, and an AND gate 22.
[0020]
The CPU 2 fetches an instruction from the RAM 8 or the flash memory 7 via the bus controller 3, decodes the fetched instruction, executes data fetch and operation control in accordance with the decoded result, and executes the instruction. The RAM 8 is used as a work area and a program area for the CPU 2. The flash memory 7 is used as a data area and a program area of the CPU 2.
[0021]
The flash memory 7 has a stack structure in which a floating gate and a control gate are stacked via a gate insulating film on a channel region between the source and the drain, respectively, although the details thereof are not shown. There is a select gate separate structure in which a select gate and a memory gate are separately arranged on the left and right on a channel region between them. For example, in the latter flash memory cell having a separate structure, writing is performed by hot electron injection from the source side to the memory gate, erasing is performed by electron tunneling from the memory gate to the channel, and the threshold voltage seen from the memory gate is reduced. Configurable. In the figure, a large number of flash memory cells are arranged in a matrix in a memory array MARY. A read circuit RDC and an erase / write circuit EPC for a flash memory cell are provided, and an oscillation circuit TCNT for generating a timing signal for read, erase, and write operations and a boosting operation for generating a high voltage is provided. When the flash memory 7 is enabled in accordance with the setting state of a module stop control register 16 described later, the oscillation circuit TCNT operates even if an actual memory access operation is not performed. A frequency division operation or the like for signal generation is performed, and this operation consumes relatively large power. The boosted voltage obtained by the charge pump operation is used as an erase voltage, a write voltage, a read word line selection voltage, and the like. In order to completely cut off such power consumption, it is necessary to set the module stop control register 16 and control the flash memory 7 to stop the operation (inoperable state).
[0022]
The bus controller 3 controls a bus to be accessed via the bus 15 in response to an access request from the CPU 2 or the like. The bus controller 3 has a bus control register 30 and stores an address (mapping address) at which a circuit module such as the flash memory 7 or the RAM 8 is arranged in the address space of the CPU 2, an access data size, the number of access cycles, and the like in an address area or a circuit. Holds access control information for each module. This access control information is made programmable by the CPU 2 and is initialized to a predetermined value by a reset operation. The bus 15 includes, in addition to an address bus and a data bus, a control bus to which a read command, a write signal, a bus command which encodes a bus size signal and the like are transmitted.
[0023]
The interrupt controller 5 inputs an exception signal such as an interrupt signal (not shown) or a bus error signal from the clock timer 9 or other peripheral circuits 10 and the like, and sends an exception request signal IRQ and a cause code of the interruption or exception processing to the CPU 2. (Vector number). As a result, the CPU 2 interrupts the process being executed, saves the state, reads the branch destination address from the vector indicated by the vector number, branches to a predetermined processing routine, and performs a desired process. At the end of a predetermined processing routine, a return instruction is usually placed. By executing this instruction, the interrupted processing is restarted.
[0024]
Although not particularly limited, the main oscillator 12 has an oscillation frequency of 10 MHz, and the sub oscillator 13 has an oscillation frequency of 32 KHz. The outputs of the oscillators 12 and 13 are selected by the selector 14 and used as an operation reference clock signal φs for the microcomputer. The selection operation of the selector 14 and the oscillation operation of the oscillators 12 and 13 are controlled by the oscillation control circuit 11 based on the 2-bit control signal S1. When the control signal S1 is 00, the sub-oscillator 13 is oscillated and its oscillation output is selected by the selector 14, and when the control signal S1 is 01, the sub-oscillator 13 and the main oscillator are oscillated and the oscillation output of the main oscillator 12 is selected by the selector 14. Then, the oscillating operations of both the oscillators 12 and 13 are stopped by the control signal S10. In the reset process, the control signal S1 is initialized to 00, the oscillation operation of the sub-oscillator 13 is designated, the selector 14 is designated to select the output of the sub-oscillator 13, and the operation reference clock signal after the reset is released. φs is a low frequency of 32 KHz. A clock signal of 32 KHz from the sub-oscillator 13 is constantly supplied to the clock timer 9 as a synchronous clock signal for timer operation.
[0025]
In the module stop control register 16, control data for controlling the operation stop (inoperable state) of the flash memory 7, the RAM 8, the clock timer 9, other peripheral circuits 10, and the oscillation control circuit 11 and the release of the stop are set. The control data can be set by the CPU 2 via the bus 15 in a programmable manner. When the standby mode STB is asserted to indicate the standby mode, the control data is forced to stop the operation of all circuit modules. When the standby signal STB is negated and the release of the standby mode is instructed, the control data is set to the same low power consumption state as after reset release described later.
[0026]
The system controller 6 performs microcomputer reset control and the like. That is, the internal reset signal res / (symbol / means a low enable signal) of the microcomputer 1 is output from the AND gate 22. The internal reset signal res / is supplied to an internal circuit of the microcomputer 1 and resets (initializes) a register value and a predetermined circuit node according to the low level. The reset is released by the high level of the internal reset signal res /. An external reset signal RES / from a reset terminal and a transfer end signal S3 from the data transfer control circuit 4 are input to the AND gate 22. When the reset operation is instructed by the low level of the external reset signal RES /, the internal reset signal res / is set to the low level to start the reset operation, and the reset operation is instructed by the high level of the external reset signal RES /. At this time, the internal reset operation is canceled after the completion of the data transfer by the data transfer control circuit 4 is notified by the transfer end signal S3. When the internal reset operation is released, the CPU 2 fetches the reset vector from the address 0 of the program address and starts executing the reset exception processing. The processing content of the reset exception processing is defined by, for example, a user program.
[0027]
The power supply voltage monitoring circuit 20 activates the signal S4 when the supply voltage reaches the operable voltage when the power supply voltage VCC is applied to the power supply terminal. The oscillation stabilization counter 21 starts the counting operation of the clock signal φs input to the clock terminal CK when the external reset signal RES / is set to the low level, and the counting operation is performed by the control signal S4 from the power supply voltage monitoring circuit 20. , And when the count value reaches a predetermined value, the control signal S5 is activated. In short, the control signal S5 is such that the power supply voltage VCC is stabilized at the time of power-on and the oscillation frequency of the clock signal φs is stabilized, and then the time necessary for completing the internal reset operation elapses by the counting operation of the counter 21. It is activated after waiting. After the control signal S5 is activated, the microcomputer 1 can normally perform internal operations in synchronization with the clock signal φs using the power supply voltage VCC as an operation power supply.
[0028]
The data transfer control circuit 4 performs data transfer control after the activation of the control signal S5. That is, after the microcomputer 1 can normally perform internal operations in synchronism with the clock signal φs using the power supply voltage VCC as an operation power supply, a predetermined amount of data is stored in the flash memory 7 and the RAM 8 during the power-on reset. Transfer of the program. Although the transfer method is not particularly limited, the transfer control is the same as that of the direct memory access transfer. The transfer source address, the transfer destination address, the number of words to be transferred, and the like are determined by the reset operation of the data transfer control circuit 4. Is determined uniquely. As shown in FIG. 2, the address mapping between the flash memory 7 and the RAM 8 by the reset is as follows. This address mapping is set by hardware when the space control register 30 of the bus controller 3 is reset. The transfer source set during the reset in the data transfer control circuit 4 is the address H'0000-H'00FFF assigned to the area FE1 of the flash memory 7, and the transfer destination is the address H'FD000- assigned to the area RE1 of the RAM 8. H′FDFFF is set. The area FE1 stores the exception processing and interrupt processing vector VEC and a part of the program PGM1, which are transferred to the area RE1 of the RAM 8. Some of the programs PGM1 include a reset exception handling program. After completing the transfer from the area FE1 to the area RE1, the data transfer control circuit 4 assigns addresses H'0000 to H'00FFF as a program area to a part of the area RE1 of the RAM 8 and a part of the area of the flash memory. Addresses H'01000 to H'3FFFF are assigned to FE2 as a subsequent program area. The area FE1 of the flash memory 7 is not address-mapped and is a non-access area, and the area RE2 of the RAM 8 is assigned to addresses H'FE000 to H'FFFFF and is used as a work area of the CPU 2. This address mapping is performed by the data transfer control circuit 4 setting control data in the space control register 30 of the bus controller 3. The address mapping between the flash memory 7 and the RAM 8 is as shown in FIG. Further, the data transfer control circuit 4 changes the data setting for the module stop control register 16 to change the flash memory 7 to the operation stop module, and makes the power consumption of the flash memory 7 zero. After completing the processing up to this point, the data transfer control circuit 4 asserts the signal S3.
[0029]
The reset release is instructed by the external reset signal RES /, and the reset operation is released by the internal reset signal res / by asserting the signal S3, whereby the CPU 2 resets the reset vector at address 0 (address H'00000). Fetch is performed to execute reset exception processing. At this time, the address 0 is allocated to a partial area RE1 of the RAM 8 as described above, and the reset vector is fetched from the RAM 8 and the reset exception processing program is fetched from the RAM 8 and executed. Thereafter, the CPU 2 can fetch the program from the RAM 8 and execute it. When it is desired to execute a program in the flash memory 7, the flash memory 7 is made operable. At this time, if the entire RAM 8 is to be used as a work area for the CPU 2, the address mapping may be changed as shown in FIG. If it is desired to further speed up the instruction execution, the main oscillator 12 is caused to oscillate, and its output is selected by the selector 14 to increase the frequency of the clock signal φs.
[0030]
The operation mode of the microcomputer 1 is not particularly limited, but is a low power consumption mode, a normal operation mode, and a standby mode.
[0031]
In the low power consumption mode, the operation reference clock signal φs is used as the oscillation output of the sub oscillator 13, the oscillation operation of the main oscillator 12 is stopped, the flash memory 7 is made inoperable, and the area RE1 of the RAM 8 is used as the program area of the CPU 2. Mode. As is clear from the above description, the microcomputer 1 is in the low power consumption mode when the reset operation is released. In the low power consumption mode, when the CPU 2 accesses the program from H'00000, the RAM is accessed as illustrated in FIG.
[0032]
The normal operation mode is an operation mode in which the operation reference clock signal φs is used as the oscillation output of the main oscillator 12, the flash memory 7 is operable, and the program area of the CPU 2 is the flash memory 7. The transition from the low power consumption mode to the normal operation mode is performed as a part of interrupt processing in response to a predetermined interrupt request (high-speed operation request) for performing high-speed arithmetic processing from the peripheral circuit 10 or externally. And by changing the setting of the module stop control register 16. When the interrupt processing in response to the high-speed operation request ends, the microcomputer returns to the state before the interrupt and returns to the low power consumption mode. In the normal operation mode, when the CPU 2 accesses the program from H'00000, the flash memory 7 is accessed as illustrated in FIG.
[0033]
The standby mode instruction is given to the module stop control register 16 by the standby signal STB, and the control data is forced to stop the operation of all circuit modules. As a result, the oscillation operations of the oscillators 12 and 13 are stopped, and the operations of the CPU 2, the flash memory 7, and the like are stopped. When the standby signal STB is negated and the release of the standby mode is instructed, the control data of the module stop control register 16 is set to the same state as in the low power consumption mode. The standby mode may be set by changing the control data of the module stop control register 16 so that the CPU 2 executes a sleep command and stops the operation of all circuit modules.
[0034]
FIG. 6 illustrates a timing chart of the power-on reset start of the microcomputer 1. 7 and 8 show operation flowcharts at that time.
[0035]
In FIG. 6, (1), (2), and (3) show operations during reset. In (1), an internal reset process started by the assertion of the external reset signal RES / is performed. The oscillation stabilization wait period is set. That is, in FIG. 7, it is determined that the power supply voltage has become an operable voltage (S1), and thereafter, an elapse of the oscillation stabilization time is waited (S2). FIG. 9 illustrates an outline of an internal state of the microcomputer 1 in the internal reset processing. A circuit module indicated by a thick rectangle is an operable circuit module. The main clock is a clock signal output from the main oscillator 12, and the sub clock is a clock signal output from the sub oscillator 13.
[0036]
Steps (2) and (3) in FIG. 6 are periods during which the data transfer control circuit 4 transfers vectors and programs from the flash memory 7 to the RAM 8, and the like. In FIG. 7, the data transfer process of step S3 is performed. In particular, (3) means a period during which the transfer of the program has not yet been completed even if an external reset release instruction has been issued. After the transfer of the program or the like, the flash memory 7 is disabled by the module stop control. FIG. 10 illustrates an outline of the internal state of the microcomputer 1 in the transfer processing of the program and the like.
[0037]
Thereafter, the microcomputer 1 is operated in the low power consumption mode indicated by the period (4) in FIG. First, a reset vector is fetched from the RAM 8 to execute reset exception processing, and thereafter, in a low power consumption mode, the presence or absence of an external high-speed operation request is monitored. For example, input monitoring of button operation or waiting for data reception is performed. In FIG. 7, reset exception processing and the like are performed in step S6, and monitoring for the presence or absence of a high-speed operation request is performed in step S7. An outline of the internal state of the microcomputer 1 in the low power consumption mode is illustrated in FIG.
[0038]
In (5) of FIG. 6, for example, an input of a button operation is detected, and transition control to the normal operation mode is performed. That is, the main oscillator 12 is oscillated to release the module stop of the flash memory 7 to enable the operation. Waiting for stabilization of the oscillation clock signal φs and stabilization of the operation of the oscillation circuit TCNT of the flash memory 7, switching of the clock signal and switching of the address mapping by the bus control register 30 are performed, and the microcomputer 1 Operate in normal operation mode as indicated by the period. In FIG. 8, the process of transition to the normal operation mode is the process of steps S8 to S11, and the process of the normal operation mode is steps S12 to S13. FIG. 12 illustrates an outline of the internal state of the microcomputer 1 when transitioning to the normal operation mode. FIG. 13 schematically illustrates the internal state of the microcomputer 1 in the normal operation mode.
[0039]
After the necessary operation in the normal operation mode is completed, the operation mode is again shifted to the low power consumption mode as indicated by (7). In FIG. 8, the transition process is shown in steps S14 to S16.
[0040]
In FIG. 6, in the low power consumption mode, for example, when there is no operation request for a certain period, the standby mode is instructed from outside as shown by (8). When the release of the standby mode is instructed, the subclock oscillator 13 resumes the oscillating operation as shown in (9), and is set to the low power consumption mode. FIG. 14 schematically shows the internal state of the microcomputer 1 in the standby mode.
[0041]
In the above description, the microcomputer 1 is set to the low power consumption mode after the reset is released, and performs the reset exception processing in the operation mode as it is. That is, immediately after reset release, a low power consumption mode is set in which the CPU 2 executes the program of the RAM 8 in a state where the operation of the flash memory 7 is stopped. Since the program is transferred during the reset, the power consumption by the on-chip flash memory 7 is reduced as a function unique to the microcomputer 1 without depending on the user program, thereby realizing low power consumption of the microcomputer 1 as a whole. can do. Since the microcomputer 1 operates in the low power consumption mode as the main operation mode, excellent low power consumption performance can be realized.
[0042]
Contrary to the above, the microcomputer 1 of the present invention is configured to be in the normal operation mode after reset release, perform reset exception processing in this operation mode, and operate in the low power consumption mode as necessary. Is also possible. Hereinafter, a case where such a configuration is adopted for the microcomputer 1 will be described. That is, when the processing of transferring the program and the vector from the flash memory 7 to the RAM 8 is completed, the operation of the flash memory 7 is kept enabled, and the address mapping between the RAM 8 and the flash memory 7 with respect to the address space of the CPU 2 is performed as shown in FIG. Keep it as it is. After the reset is released, the CPU 2 executes the program of the flash memory 7 in the manner illustrated in FIG. The operation mode is changed to the low power consumption mode as necessary due to an interrupt or the like, and after the operation in the low power consumption mode is completed, the process returns from the interrupt processing and the instruction can be executed in the normal operation mode.
[0043]
FIG. 15 illustrates a timing chart of a power-on reset start of the microcomputer which is brought into the normal operation mode immediately after the reset. 16 and 17 show operation flowcharts at that time.
[0044]
In FIG. 15, (1), (2) and (3) show operations during reset. In (1), an internal reset process started by the assertion of the external reset signal RES / is performed. The oscillation stabilization wait period is set. That is, in FIG. 16, it is determined that the power supply voltage has become an operable voltage (S11), and thereafter, an elapse of the oscillation stabilization time is waited (S12).
[0045]
(2) and (3) in FIG. 15 are periods during which the data transfer control circuit 4 transfers vectors and programs from the flash memory 7 to the RAM 8 and the like. In FIG. 16, the data transfer process of step S13 is performed. In particular, (3) means a period during which the transfer of the program has not yet been completed even if an external reset release instruction has been issued.
[0046]
Thereafter, the microcomputer 1 is operated in the normal operation mode indicated by the period (4) in FIG. First, a reset vector is fetched from the flash memory 7 to execute reset exception processing, and thereafter, completion of the high-speed operation in the normal operation mode is monitored. In FIG. 16, reset exception processing and the like are performed in step S15, and monitoring of completion of high-speed operation is performed in step S16.
[0047]
In (5) of FIG. 15, for example, transition control to the low power consumption mode is performed. That is, as illustrated in FIG. 17, the address mapping is switched by the bus control register 30 (S17), the operation of the flash memory 7 is stopped (S18), the oscillation of the main oscillator 12 is stopped, and the operation reference clock is output. The signal φs is switched to the oscillation output of the sub oscillator 13 (S19). Thus, the CPU 2 fetches an instruction from the address-mapped RAM 8 in FIG. 4 and executes the program (S20). After completing the necessary operation in the low power consumption mode, it is monitored whether a request for a high speed operation in the normal operation mode is made (S21).
[0048]
When the request for the high-speed operation is detected, the transition control to the normal operation mode is performed in (6) of FIG. That is, the main oscillator 12 is oscillated to release the module stop of the flash memory 7 to enable the operation. Waiting for stabilization of the oscillation clock signal φs and stabilization of the operation of the oscillation circuit TCNT of the flash memory 7, switching of the clock signal and switching of the address mapping by the bus control register 30 are performed, and the microcomputer 1 Operate in normal operation mode as indicated by the period. In FIG. 17, the transition processing to the normal operation mode is the processing of steps S22 to S25.
[0049]
In the example of FIG. 15, after the necessary operation in the normal operation mode is completed, the standby mode as indicated by {circle around (8)} is set, and thereafter, the mode transits to the normal operation power mode again.
[0050]
In the configuration in which the transition to the low power consumption mode is enabled after executing the reset exception processing after reset release as illustrated in FIG. 15, the transition to the low power consumption mode is performed by a user program or an external device. The microcomputer itself can be prepared so as to be able to immediately transit to the low power consumption mode upon receiving the instruction.
[0051]
Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it goes without saying that the invention can be variously modified without departing from the gist thereof.
[0052]
For example, the operation mode of the microcomputer is not limited to the low power consumption mode, the normal operation mode, and the standby mode. A sleep mode in which the operation of the CPU and the flash memory is stopped to enable predetermined peripheral circuits to operate; a module standby mode in which the CPU and the flash memory are enabled and operation of the peripheral circuits are stopped; Sub-active mode to operate synchronously with the clock for clock, sub-sleep mode to suspend operation of the CPU and flash memory and enable peripheral circuits to operate synchronously with the clock for clock, and to suspend operation of the CPU and flash memory and operate only the clock timer A watch mode may be provided. Also, the oscillator is not limited to a configuration having two main oscillators and a sub-oscillator separately, but does not require high precision used for a clock or the like and has a low-frequency oscillator separately from a high-precision and high-frequency oscillator. It is preferable for low power consumption to operate only the former oscillator at the time of clock synchronization operation with priority on low power consumption. The circuit module possessed by the microcomputer is not limited to the example of FIG. 1 and can be changed as appropriate. The electrically rewritable nonvolatile memory is not limited to a flash memory, but may be an EEPROM, a high-dielectric memory, or the like. The data transfer control circuit 4 may be configured as a dedicated circuit for program transfer processing performed as part of the reset processing. However, when a general-purpose transfer control circuit such as a direct memory access controller is provided as an on-chip circuit module, Such a transfer control circuit may be used for transfer control of a program in the reset processing.
[0053]
The data processor of the present invention can be widely applied to various data processing apparatuses called a microprocessor, a single-chip data processor, and the like, in addition to the microcomputer.
[0054]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
[0055]
That is, according to the data processor of the present invention, since the program is transferred from the nonvolatile memory to the RAM during the reset, it is possible to prepare to be able to immediately transition to the low power consumption mode when instructed. In addition, the power consumption of the on-chip nonvolatile memory can be reduced as a function unique to the microcomputer without depending on the user program, and low power consumption of the entire microcomputer can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram of a microcomputer according to an example of the present invention.
FIG. 2 is an explanatory diagram exemplifying address mapping between a flash memory and a RAM by reset;
FIG. 3 is an explanatory diagram exemplifying address mapping between a flash memory and a RAM in a low power consumption mode;
FIG. 4 is an explanatory diagram illustrating a program space accessible by a CPU in a low power consumption mode;
FIG. 5 is an explanatory diagram illustrating a program space accessible by a CPU 2 in a normal operation mode.
FIG. 6 is a timing chart illustrating a power-on reset start state of the microcomputer;
FIG. 7 is an operation flowchart showing a part of the operation control procedure in the power-on reset start of FIG. 6;
FIG. 8 is an operation flowchart showing a continuation of FIG. 6;
FIG. 9 is an explanatory diagram schematically illustrating an internal state of a microcomputer in an internal reset process.
FIG. 10 is an explanatory diagram schematically illustrating an internal state of a microcomputer in transfer processing of a program or the like.
FIG. 11 is an explanatory diagram schematically illustrating an internal state of the microcomputer in a low power consumption mode.
FIG. 12 is an explanatory diagram schematically illustrating an internal state of the microcomputer when transitioning to a normal operation mode.
FIG. 13 is an explanatory diagram schematically illustrating an internal state of the microcomputer in a normal operation mode.
FIG. 14 is an explanatory diagram schematically illustrating an internal state of the microcomputer in a standby mode.
FIG. 15 is a timing chart illustrating a power-on reset start state of a microcomputer which is set to a normal operation mode immediately after reset.
FIG. 16 is an operation flowchart showing a part of the operation control procedure in the power-on reset start of FIG. 15;
FIG. 17 is a flowchart showing a continuation of FIG. 16;
[Explanation of symbols]
1 Microcomputer
2 Central processing unit (CPU)
3 Bus controller
4 Data transfer control circuit
5 Interrupt controller
6 System controller
7 Flash memory
8 RAM
RES / External reset signal
res / Internal reset signal

Claims (12)

A central processing unit, a RAM, and a rewritable nonvolatile memory are provided on a semiconductor chip, and a predetermined program is transferred from the nonvolatile memory to the RAM during a power-on reset. A data processor wherein a transition to a low power consumption mode in which the central processing unit executes a program of the RAM is enabled while the operation of the memory is stopped. 2. The data processor according to claim 1, wherein the power-on reset is instructed by assertion of an external reset signal. 3. The data processor according to claim 2, wherein the reset release is performed by releasing an internal reset instruction after the reset signal is negated. 2. The data processor according to claim 1, wherein a transition to the low power consumption mode is enabled after executing reset exception processing after reset release. 2. The data processor according to claim 1, wherein reset exception processing itself after reset release is set to the low power consumption mode. 6. The data processor according to claim 5, wherein the RAM program executed after the reset release includes a vector for exception processing and interrupt processing and a reset exception processing program. 6. The data processor according to claim 4, further comprising a transfer control circuit for controlling transfer of a predetermined program from said nonvolatile memory to said RAM. 6. The data processor according to claim 4, wherein a transition to a normal operation mode in which the central processing unit executes a program of the nonvolatile memory is enabled. In the low power consumption mode, the central processing unit is operated in synchronization with a clock signal having a first frequency, and in the normal operation mode, the central processing unit is operated in synchronization with a lock signal having a second frequency higher than the first frequency. The data processor according to claim 8, wherein A central processing unit, a RAM, and a rewritable nonvolatile memory on a semiconductor chip, performing a predetermined program transfer from the nonvolatile memory to the RAM during a power-on reset, and releasing the nonvolatile memory after reset release In a state where the operation of the CPU is stopped, the central processing unit executes the program of the RAM to perform a reset exception process, and thereafter, the low power consumption mode in which the central processing unit executes the program of the RAM and the central processing unit. Wherein a normal operation mode for executing a program of the nonvolatile memory can be selected. In the reset exception processing and the low power consumption mode, the central processing unit is operated in synchronization with a clock signal of a first frequency, and in the normal operation mode, the central processing unit is synchronized with a clock signal of a second frequency higher than the first frequency. The data processor according to claim 10, wherein the data processor is operated synchronously. A central processing unit, a RAM, and a rewritable nonvolatile memory on a semiconductor chip, performing a predetermined program transfer from the nonvolatile memory to the RAM during a power-on reset, and releasing the nonvolatile memory after reset release Wherein the central processing unit executes a program of the RAM to perform a reset exception process in a state in which the operation of the data processor is stopped.

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