JP2010191650A - Information processor and control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor for suppressing power consumption even when a rewritable memory is arranged outside an IC chip. <P>SOLUTION: The information processor is provided with: an IC chip having a CPU, an internal memory and internal wiring connecting the CPU with the internal memory; an external memory arranged outside the IC chip, and connected through an interface to the internal wiring; an execution address transition means for making the CPU execute a standby program in the internal memory in a standby mode, and for making the CPU execute a processing program in the external memory when a processing request is made from the outside; and an external memory control means for stopping the external memory when in the standby mode, and for making the external memory operate when the processing request is made. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus including an IC chip on which a CPU is mounted and a memory outside the IC chip, and a control method therefor.

  In general, an information processing apparatus mounted on an electronic device incorporates firmware in order to perform basic hardware control, and the firmware is often updated to improve the function and operational stability of the device. In order to cope with firmware upgrades, a rewritable ROM (Read-Only Memory) type memory element, such as a flash ROM, is often mounted, and firmware is often written into the memory element.

  On the other hand, in small sensor terminals, portable terminals, watches, calculators, and the like that require low power consumption by reducing current at the microampere level, SOI (Silicon) is more efficient than general-purpose CMOS (Complementary Metal-Oxide Semiconductor) in terms of power consumption. on Insulator) -CMOS. However, it is difficult to physically mix SOI-CMOS and rewritable ROM due to the manufacturing process. For this reason, in the information processing apparatus, a rewritable ROM is arranged outside an IC chip on which a central processing unit (CPU) is mounted, and both are connected through an external interface (I / F) (for example, non-patent). See reference 1.)

Oki Electric Industry Co., Ltd., “Oki System LSI Design Platform” “http://www.okisemi.com/jp/dbps_data/_material_/topics/html/_res/images_uplat/OKI_uPLAT — 01.pdf, January 20, 2009.

  In such a configuration, the stray capacitance is larger in the wiring outside the chip than in the wiring in the chip, so that a drive capability is required for the protection circuit of the IC, and there is a leakage current due to a pull-up resistor of the bus. For this reason, even if SOI-CMOS was low power, the subject that the power consumption of information processing apparatus became large occurred.

  In order to solve the above-described problems, an object of the present invention is to provide an information processing apparatus and a control method capable of suppressing power consumption even when a rewritable memory is arranged outside an IC chip.

  In order to achieve the above object, the information control apparatus according to the present invention transfers a program required when the CPU waits in advance from an external memory arranged outside the IC chip to the internal memory in the IC chip, Data transmission / reception between the IC chip and the external memory is eliminated, and the power supply of the external memory is shut off.

  Specifically, an information control device according to the present invention includes a CPU, an internal memory, an IC chip on which the CPU and the internal wiring for connecting the CPU and the internal memory are mounted, and an external part of the IC chip. External memory connected to the internal wiring, and execution address transition means for causing the CPU to execute the standby program in the internal memory when waiting for processing and causing the CPU to execute the processing program in the external memory when requesting processing from the outside And external memory control means for stopping the external memory when waiting for the processing and operating the external memory when requesting the processing.

  Further, the control method of the information control apparatus according to the present invention includes a CPU, an internal memory, an IC chip on which the CPU and the internal wiring for connecting the CPU and the internal memory are mounted, and the outside of the IC chip. An information processing apparatus control method comprising: an external memory connected to an internal wiring; a standby program read step for reading a standby program in the internal memory during processing standby; and executing the standby program; A standby processing step for stopping the operation, an operation processing step for ending the standby program at the time of an external processing request and operating the external memory, a processing program reading step for reading the requested processing program in the external memory, It is characterized by performing.

  Since there is no data transmission / reception via the standby interface, the power consumed by the interface can be reduced. In addition, since the external memory is stopped, the power consumed by the external memory can be reduced. Therefore, the present invention can provide an information processing apparatus and a control method capable of suppressing power consumption even when a rewritable memory is arranged outside the IC chip.

  Addresses are allocated to the memory spaces of the internal memory and the external memory, and the execution address transition means of the information control device according to the present invention provides a program counter in which the address of the memory space to be read by the CPU is written. Can be changed. Further, in the control method of the information control device, in the standby program reading step, a program counter in which the address of the memory space that is read by the CPU is written to the address of the memory space in which the standby program of the internal memory is held. In the processing program reading step, the program counter can be changed to an address of a memory space in which the processing program in the external memory is held. By changing the program counter, the reading destination of the CPU program can be changed.

  The interface includes a protection circuit that adjusts electrical characteristics between the external wiring formed outside the IC chip and the internal wiring, and the information control apparatus according to the present invention further includes the protection circuit during the processing standby. It is preferable to further include protection circuit control means for stopping the circuit and operating the protection circuit when the processing is requested. Furthermore, power consumption can be reduced.

  The protection circuit control means of the information control device according to the present invention cuts off the data signal line of the protection circuit that connects the internal wiring and the external memory during the processing standby, and connects the data signal line when the processing is requested. It is preferable to reconnect. The power consumed by the internal resistances of the input protection circuit and the output protection circuit, the current flowing from the external circuit to the internal circuit, and the current flowing from the internal circuit to the external circuit can be reduced.

  Preferably, the information control apparatus according to the present invention further includes an operation clock changing unit that lowers an operation clock for the CPU to operate when waiting for the process and increases the operation clock when the process is requested. Furthermore, power consumption can be reduced.

  The internal memory has a program area for holding the standby program and a data area for holding calculation data in the CPU, and the information control apparatus according to the present invention can store the internal memory at the time of the processing request. It is preferable to further comprise internal memory control means for stopping the program area and operating the program area of the internal memory during the processing standby. Furthermore, power consumption can be reduced.

  The information control apparatus according to the present invention preferably further comprises transfer means for copying the standby program recorded in the external memory to the internal memory. The information control apparatus control method according to the present invention preferably performs a transfer step of copying the standby program recorded in the external memory to the internal memory before the standby program reading step. The standby program can be transferred from the external memory to the internal memory when the information processing apparatus is activated or after the program area of the internal memory is stopped.

  The present invention can provide an information processing apparatus and a control method capable of suppressing power consumption even when a rewritable memory is arranged outside an IC chip.

It is a block diagram explaining the structure of the information processing apparatus which concerns on this invention. It is a block diagram explaining the structure of the information processing apparatus which concerns on this invention. It is a figure explaining the structure of the external memory of the information processing apparatus which concerns on this invention. It is a figure explaining the structure of the internal memory of the information processing apparatus which concerns on this invention. It is a figure explaining the structure of the input protection circuit of the information processing apparatus which concerns on this invention. It is a figure explaining the structure of the output protection circuit of the information processing apparatus which concerns on this invention. It is a conceptual diagram of the memory space of the information processing apparatus which concerns on this invention. It is a conceptual diagram of the memory space of the information processing apparatus which concerns on this invention. It is a flowchart explaining the control method of the information processing apparatus which concerns on this invention.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

  1 and 2 are block diagrams illustrating the configuration of the information processing apparatus 301 and the information processing apparatus 302 according to the present embodiment. The information processing apparatus 301 and the information processing apparatus 302 are external to the IC chip 101 on which the CPU 11, the internal memory 12, and the internal wiring 13 that connects the CPU 11 and the internal memory 12 are mounted. And an external memory 22 connected to the wiring 13.

  The CPU 11 is a central processing unit that processes programs stored in the internal memory 12 and the external memory 22. The CPU 11 is connected to the sensor unit 401 outside the information processing apparatus 301 and the information processing apparatus 302, and can control the sensor unit 401. Further, the CPU 11 receives a processing request. The processing request is, for example, an interrupt such as a sensor unit 401 or a timer interrupt.

  The internal memory 12 has a program area for holding a program and a data area for holding calculation data in the CPU 11. The internal memory 12 is a RAM, for example. Since the RAM consumes more power than the ROM, the program area has only a minimum capacity.

  The internal wiring 13 is a bus that connects circuits in the IC chip 101. The internal wiring 13 is connected to the CPU 11, the internal memory 12, and the interface 18.

  The external memory 22 holds programs and firmware executed by the CPU 11. The external memory 22 is, for example, a flash ROM.

  The information processing apparatus 301 includes an external wiring 23. The external wiring 23 is a bus that connects the IC chip 101 and peripheral components such as the external memory 22. In the information processing apparatus 301, the interface 18 is connected to the external wiring 23. In this case, the interface 18 can be a parallel bus capable of propagating a plurality of bits. 2 does not include the external wiring 23, and directly connects the external memory 22 and the internal wiring 13 through the interface 18. In this case, the interface 18 can be a serial bus.

  The interface 18 may have a protection circuit 15. The protection circuit 15 is a circuit in an IC chip that adjusts electrical characteristics of the internal wiring 13 and the external wiring 23 or the internal wiring 13 and the external memory 22. The protection circuit 15 has a function as a driver for flowing a specified current, a function of preventing overcurrent, and a function of preventing current from flowing from the external bus to the internal bus when the ROM is disconnected. The protection circuit 15 needs to be arranged for each bit. The protection circuit 15 includes an input protection circuit in which a signal flows from the outside of the IC chip 101 to the internal wiring 13 and an output protection circuit in which a signal flows from the internal wiring 13 to the outside of the IC chip 101.

  The control signal line 14 connects the CPU 11, the internal memory 12, the external memory 22, and the protection circuit 15. The CPU 11 can transmit a control signal to each circuit via the control signal line 14 to stop and operate each circuit.

  FIG. 3 is a diagram for explaining the configuration of the external memory 22. The external memory 22 has a switch 31 and a ROM circuit 32. The ROM circuit 32 is a general ROM circuit, and exchanges signals via the external wiring 23 or the interface 18. The switch 31 connects the power supply Vcc and the ROM circuit 32 and is turned on and off by a control signal from the control signal line 14. That is, the external memory 22 is stopped and activated by the control signal from the control signal line 14.

  FIG. 4 is a diagram for explaining the configuration of the internal memory 12. The internal memory 12 has a switch 41 and a RAM circuit 42. The RAM circuit 42 is a general RAM circuit, and sends and receives signals via the internal wiring 13. The switch 41 connects the power supply Vcc and the RAM circuit 42 and is turned on and off by a control signal from the control signal line 14. That is, the internal memory 12 is stopped and operated by the control signal from the control signal line 14.

  FIG. 5 is a diagram for explaining the configuration of the input protection circuit in the protection circuit 15. The protection circuit 15 includes an input protection circuit 58, a switch 51, and a switch 54. The input protection circuit 58 is a general input protection circuit, and includes an internal resistor 53, a diode 52-1, and a diode 52-2. The switch 51 and the switch 54 are, for example, CMOS switches. The input protection circuit 58 is driven by the power supply Vcc, and the data signal flows from the external wiring 23 or the external memory 22 to the internal wiring 13 via the data signal line including the internal resistance 53. The switch 51 is disposed between the power supply Vcc and the diode 52-1 and is turned on and off by a control signal from the control signal line 14. That is, the protection circuit 15 is stopped and activated by the control signal from the control signal line 14. The switch 54 is disposed in a path of a signal flowing from the external wiring 23 or the external memory 22 to the internal wiring 13 and is turned on and off by a control signal from the control signal line 14. That is, the protection circuit 15 connects and disconnects the external wiring 23 or the external memory 22 and the internal wiring 13 with a control signal from the control signal line 14.

  FIG. 6 is a diagram illustrating the configuration of the output protection circuit in the protection circuit 15. The protection circuit 15 includes an output protection circuit 68, a switch 61, and a switch 64. The output protection circuit 68 is a general output protection circuit, and includes an internal resistor 63, a pull-up resistor 65, a diode 62-1 and a diode 62-2. The switches 61 and 64 are, for example, CMOS switches. The output protection circuit 68 is driven by the power supply Vcc, and the data signal flows from the internal wiring 13 to the external wiring 23 or the external memory 22 via the data signal line including the internal resistor 63. The switch 61 is disposed between the power supply Vcc and the diode 62-1 and is turned on and off by a control signal from the control signal line 14. That is, the protection circuit 15 is stopped and activated by the control signal from the control signal line 14. The switch 64 is disposed in a path of a signal flowing from the internal wiring 13 to the external wiring 23 or the external memory 22 and is turned on and off by a control signal from the control signal line 14. That is, the protection circuit 15 connects and disconnects the external wiring 23 or the external memory 22 and the internal wiring 13 with a control signal from the control signal line 14.

  Hereinafter, how the information processing apparatus 301 and the information processing apparatus 302 reduce power consumption will be described in detail.

  Since the internal wiring 13 is a closed wiring in the IC chip, the wiring width is narrower and the wiring length is shorter than that of the external wiring 23, so that the parasitic capacitance is small and the wiring resistance is also small. Therefore, when the same amount of signal is transmitted, the signal transmission through the internal wiring 13 is lower than the signal transmission through the external wiring 23. Further, the protection circuit 15 has an internal resistor 53 and an internal resistor 63, and if the signal is transmitted between the IC chip 101 and the external memory 22, power is consumed by the internal resistor 53 and the internal resistor 63. Accordingly, the signal transmission within the IC chip 101 is lower in power consumption than the signal transmission between the IC chip 101 and the external memory 22.

  Therefore, power consumption can be reduced by transferring a program held in the external memory 22 to the internal memory 12 and performing signal transmission between the internal memory 12 and the CPU 11 in accordance with the operation mode of the CPU. At this time, the power consumed by the external memory 22 and the protection circuit 15 can be reduced by stopping the external memory 22 and the protection circuit 15.

  The information processing apparatus 301 and the information processing apparatus 302 have execution address transition means for causing the CPU 11 to execute the standby program in the internal memory 12 when waiting for processing and causing the CPU 11 to execute the processing program in the external memory 22 when requesting processing from the outside. And external memory control means for stopping the external memory 22 when waiting for processing and operating the external memory 22 when processing is requested. Furthermore, the information processing device 301 and the information processing device 302 stop the protection circuit 15 when waiting for processing, a protection circuit control unit that operates the protection circuit 15 when processing is requested, and lowers an operation clock at which the CPU 11 operates when waiting for processing, Operation clock changing means for raising the operation clock 11 when a process is requested, and internal memory control means for stopping the program area of the internal memory 12 when the process is requested and operating the program area of the internal memory 12 when waiting for the process. For example, the execution address transition means, the external memory control means, the protection circuit control means, the operation clock change means, and the internal memory control means can be implemented as a program that operates on the CPU 11. The information processing device 301 and the information processing device 302 use these means to reduce power consumption as follows.

  The CPU 11 reads a standby program in the internal memory 12 during processing standby, a standby program reading step for executing the standby program and stopping the external memory 22, and ending the standby program when an external processing request is made. An operation processing step for operating the external memory 22 and a processing program reading step for reading the requested processing program are performed.

  When the CPU 11 is operating normally (active mode), the CPU 11 reads the processing program in the external memory 22. For example, when there is no processing request from the sensor unit 401 for a predetermined time, the CPU 11 enters a standby state (sleep mode). In the standby program reading step, the CPU 11 changes the program reading destination from the external memory 22 to the internal memory 12 by the execution address transition means, and reads and executes the standby program held in the internal memory 12. Here, the execution address transition means will be described in detail. Addresses are allocated to the memory spaces of the internal memory 12 and the external memory 22 as shown in FIGS. The CPU 11 has a program counter in which the address of the memory space to be read is written, and is realized by the execution address transition means changing the program counter. Here, the standby program describes the minimum necessary contents that must be done particularly during sleep. For example, timer management and sensor control.

  If there is no standby program in the internal memory 12, the CPU 11 performs a transfer step before the standby program read step. In the transfer step, the transfer means copies the standby program recorded in the external memory 22 to the internal memory 12.

  In the standby processing step, the CPU 11 transmits a control signal for instructing the external memory 22 to stop using the control signal line 14 by the external memory control means. When the external memory 22 receives the control signal, the external memory 22 turns off the switch 31 and stops the operation of the ROM circuit 32. By stopping the operation of the ROM circuit 32, the power consumed by the external memory 22 can be reduced. Further, since the ROM circuit 32 is a non-volatile memory, the contents written in the memory are not lost even if the power supply is stopped.

  When processing is requested from the sensor unit 401, in the operation processing step, the CPU 11 transmits a control signal for instructing the operation to the external memory 22 using the control signal line 14 in the external memory control means. When the external memory 22 receives the control signal, it turns on the switch 31 and operates the ROM circuit 32. Thereafter, in the processing program read step, the CPU 11 can read the requested processing program from the external memory 22 by the execution address transition means.

  Similarly, in the standby processing step, the CPU 11 may transmit a control signal for instructing the protection circuit 15 to stop using the control signal line 14 by the protection circuit control means. When receiving the control signal, the protection circuit 15 turns off the switch 51 and the switch 61 and stops the operation of the input protection circuit 58 and the output protection circuit 68. Further, the protection circuit 15 may also turn off the switch 54 and the switch 64. The power consumed by the internal resistance 53 and the internal resistance 63 of the input protection circuit 58 and the output protection circuit 68, the current flowing from the external wiring 23 or the external memory 22 to the internal wiring 13, the internal wiring 13 to the external wiring 23 or the external The power due to the current flowing out to the memory 22 can be reduced.

  When processing is requested from the sensor unit 401, in the operation processing step, the CPU 11 transmits a control signal for instructing the protection circuit 15 to operate by the protection circuit control means using the control signal line 14. When receiving the control signal, the protection circuit 15 turns on the switch 51 and the switch 61 and operates the input protection circuit 58 and the output protection circuit 68. The protection circuit 15 also turns on the switch 54 and the switch 64. Thereafter, in the processing program read step, the CPU 11 can receive the requested processing program from the external memory 22.

  As described above, when the operation mode of the CPU 11 is standby (sleep mode), the information processing device 301 and the information processing device 302 operate the external memory 22 and the protection circuit 15 with the external memory control unit and the protection circuit control unit, respectively. The program is stopped and the program in the internal memory 12 is executed. When processing is requested and the operation mode of the CPU 11 is active, the program in either the internal memory 12 or the external memory 22 is executed.

  The CPU 11 executes the program in the external memory 22 when the processing is requested and the operation mode is active. Therefore, in the operation processing step, the CPU 11 may send a control signal to the internal memory 12 using the control signal line 14 by the internal memory control means, and stop the program area of the internal memory 12. Lower power consumption can be achieved. In this case, in the standby processing step, the CPU 11 needs to operate the program area of the internal memory 12 by the internal memory control means. For example, this is effective when an IO control program that collects information from the sensor unit 401 is transferred to the internal memory 12 and the power consumed in the program area is sufficiently smaller than the power consumed in the external memory 22.

  FIG. 7 is a conceptual diagram of the memory space when the CPU 11 can manage the memory space for the program and the memory space for the data separately. Data for operation, a stack, and a register are stored in the data memory space. When the CPU 11 can execute only a program in the program memory space and cannot execute a program in the data memory space, the CPU 11 is unnecessary among the program area of the internal memory 12 and the external memory 22 in the program memory space. Either action can be stopped.

  FIG. 8 is a conceptual diagram of the memory space when the CPU 11 can manage the program memory space and the data memory space in a shared manner. For example, the developer explicitly creates a program so that the standby program copy destination uses the program area of the internal memory 12 and the data uses the data area of the internal memory 12. Of the external memory 22, the operation of the unnecessary one can be stopped.

  Further, in the standby processing step, the CPU 11 may reduce the operation clock for operating itself by the operation clock changing means. That is, the CPU 11 has a plurality of operation clocks with different speeds, and selects the lowest operation clock during the standby state in the sleep mode. The information processing apparatus 301 and the information processing apparatus 302 can reduce power consumption by operating the IC chip at a slow frequency such as 32 kHz while the CPU is on standby. Further, in order to give priority to the processing speed in the active mode, in the operation processing step, the CPU 11 selects an operation clock having a high speed such as 10 MHz by the operation clock changing means.

  A specific control method of the information processing apparatus 301 and the information processing apparatus 302 will be described with reference to FIG. FIG. 9 is a flowchart illustrating a method for controlling the information processing apparatus. First, in step S01, the IC chip 101 is turned on. Thereafter, the CPU 11 is initialized in steps S02 to S04. In step S02, the external memory 22 is powered on. In step S03, the program counter which is the reading destination of the program read by the CPU 11 is set to address F000. In step S04, the CPU 11 calculates a code from address F000 in the memory space. The address F000 in the memory space is the external memory 22, and when the CPU is turned on and started, the program in the external memory 22 is executed first. The program to be executed describes the initial settings of the IC chip and the peripheral circuit.

  Subsequently, the transfer step described above is performed from step S05 to step S06. First, in step S05, the IC chip is initialized. Thereafter, the standby program stored in the external memory 22 is copied to the internal memory 12 in step S06. Here, the copy destination is address 0100 in the memory space, which is a program area in the internal memory 12.

  Subsequently, the standby program reading step described above is performed in step S07. The timing to start step S07 is when the CPU 11 enters a sleep state. In step S07, the CPU 11 calculates a code from address 0100 in the memory space. Specifically, when executing a code on the internal memory 12, the CPU 11 reads a program (execution address transition means) that makes a jump / subroutine call to an address in the memory space allocated to the internal memory 12.

  Subsequently, the above-described standby processing step is performed from step S08 to step S10. In step S08, the CPU 11 transmits a control signal to the protection circuit 15 and the external memory 22 to stop the operation. Further, the operation clock may be lowered to the lowest speed. The CPU 11 is in a standby state until there is a processing request from the sensor unit 401 in steps S09 and S10. With this control method, the power consumption of the information processing apparatus 301 and the information processing apparatus 302 during this period can be reduced.

  Subsequently, the operation processing step described above is performed in step S11. In step 11, the CPU 11 transmits a control signal to the protection circuit 15 and the external memory 22 to start operation. In addition, when the operation clock is lowered to the lowest speed, the speed of the operation clock is increased.

  Subsequently, the processing program reading step described above is performed in step S12. In step 12, the CPU 11 reads the requested processing program stored in the external memory 22. Specifically, the CPU 11 executes a program (execution address transition means) for jumping / subroutine calling to an address of a memory space allocated to the external memory 22.

  The CPU 11 performs the process requested in step S13. When the process is completed, the CPU 11 enters the standby state again in step S14.

  The jump instruction, subroutine call instruction, subroutine call return instruction, interrupt, and interrupt return instruction are instructions for changing the CPU program counter to an arbitrary execution address. Regardless of the instruction, any instruction that changes the program counter is applicable to the present invention.

11: CPU
12: Internal memory 13: Internal wiring 14: Control signal line 15: Protection circuit 18: Interface 22: External memory 23: External wiring 31, 41, 51, 54, 61, 64: Switch 32: ROM circuit 42: RAM circuit 52 -1, 52-2, 62-1, 62-2: Diodes 53, 63: Internal resistor 58: Input protection circuit 65: Pull-up resistor 68: Output protection circuit 101: IC chips 301, 302: Information processing device 401: Sensor unit

Claims (10)

An IC chip having a CPU, an internal memory, and internal wiring for connecting the CPU and the internal memory;
An external memory external to the IC chip and connected to the internal wiring by an interface;
Execution address transition means for causing the CPU to execute a standby program in the internal memory at the time of processing standby, and causing the CPU to execute a processing program in the external memory at the time of an external processing request;
External memory control means for stopping the external memory at the time of the processing standby and operating the external memory at the time of the processing request;
An information processing apparatus comprising: Addresses are allocated to the memory spaces of the internal memory and the external memory,
The information processing apparatus according to claim 1, wherein the execution address transition unit changes a program counter in which an address of a memory space to be read by the CPU is described. The interface has a protection circuit that adjusts electrical characteristics between the external wiring formed outside the IC chip and the internal wiring.
The information processing apparatus according to claim 1, further comprising a protection circuit control unit that further stops the protection circuit when the process is on standby and operates the protection circuit when the process is requested.   The protection circuit control means cuts off a data signal line of the protection circuit that connects the internal wiring and the external memory during the processing standby, and reconnects the data signal line when the processing is requested. The information processing apparatus according to claim 3.   5. The information processing according to claim 1, further comprising an operation clock changing unit that lowers an operation clock for operating the CPU when waiting for the processing and increases the operation clock when the processing is requested. apparatus. The internal memory has a program area for holding the standby program and a data area for holding calculation data in the CPU;
6. The internal memory control means for stopping the program area of the internal memory when the processing is requested and operating the program area of the internal memory when waiting for the processing. An information processing apparatus according to claim 1.   The information processing apparatus according to claim 1, further comprising transfer means for copying the standby program recorded in the external memory to the internal memory. An IC chip having a CPU, an internal memory, and internal wiring for connecting the CPU and the internal memory;
An external memory external to the IC chip and connected to the internal wiring by an interface;
An information processing apparatus control method comprising:
A standby program read step for reading the standby program in the internal memory during processing standby;
A standby processing step of executing the standby program and stopping the external memory;
An operation processing step of ending the standby program at the time of an external processing request and operating the external memory;
A processing program read step for reading the requested processing program in the external memory;
The control method characterized by performing. Addresses are allocated to the memory spaces of the internal memory and the external memory,
In the standby program read step, the program counter in which the address of the memory space to be read by the CPU is changed to the address of the memory space in which the standby program of the internal memory is held,
9. The control method according to claim 8, wherein in the processing program reading step, the program counter is changed to an address of a memory space in which the processing program of the external memory is held.   10. The control method according to claim 8, wherein a transfer step of copying the standby program recorded in the external memory to the internal memory is performed before the standby program reading step.

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