JP4551474B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a technique for suppressing leakage current of a semiconductor integrated circuit.

  In recent years, there has been a problem that a leak current increases with the miniaturization of a transistor formed in an LSI (Large Scale Integration) such as an IC chip.

  The cause of current leakage (leakage) is leakage current due to the quantum tunnel effect. Since a phenomenon that electrons pass between the insulating layers may occur stochastically, the leakage current cannot be ignored as the circuit becomes highly integrated. In addition, when the leakage current increases, the power consumption of the LSI increases, the amount of heat generation increases, and the circuit board is easily damaged.

  In general, power consumption due to leakage current accounts for about half of the total power consumption of LSI. Here, the total power consumption is the sum of the charge / discharge power of the logic and the leak power. For this reason, it is important to suppress the leakage current in order to increase the degree of integration, improve the performance, and save power in the LSI.

  For example, a leak current is considered by a transistor formed on a semiconductor substrate shown in FIG. The transistor is formed on the semiconductor substrate 141 from a gate part 142 (Gate), a source part 143 (Source), a drain part 144 (Drain), and a mixed oxide 145 (Oxide). In the case of such a structure, the gate leak 146 (Gate leakage), the sub-threshold leak 147 (Sub-threshold leakage), etc. occur. All of these leakage currents steadily flow regardless of pure arithmetic operation (logic). Further, not only CMOS (Metal Oxide Semiconductor) LSI but also bipolar transistors have leakage power.

  Conventionally, leakage current has been suppressed by improving device process technology and improving materials. However, that alone is not enough to prevent an increase in leakage current due to high integration.

  According to Patent Document 1, a circuit block that is provided with a power supply stop line that stops supply of power supply voltage during standby and a power supply voltage supply line that is also supplied during standby, and does not need to maintain a state during standby. A circuit that reduces leakage current by connecting to a power supply stop line has been proposed.

  According to Patent Document 2, a logic circuit block that is synchronized with a supplied clock signal, a power supply switch that supplies power to the circuit block, and a control circuit that controls the switch are used to supply power for periods other than those necessary for circuit operation. Proposals have been made to cut off the supply and reduce the leakage current.

  According to Patent Document 3, a system LSI is divided into functional block circuits, each block is connected to an independent power supply line, and a standby control circuit and a power supply control circuit perform power supply to reduce power consumption. Yes.

  According to Patent Document 4, the inside of a chip is divided into a plurality of circuit blocks so that supply of power supply voltage to the block can be cut off, and a signal is output on a path of a signal output from the blockable block to another block. There has been a proposal to reduce power by providing an inter-block interface circuit capable of storing.

  However, a sufficient effect cannot be obtained only by controlling the power supply of each calculation block in the LSI as described above in order to suppress the leakage current that increases due to further miniaturization. That is, the leakage current cannot be suppressed unless the power supply is controlled for each circuit constituting each calculation block in the LSI. For that purpose, it is necessary to control the power supply by grasping the flow and timing of input and output data of each circuit (arithmetic block) in the LSI.

  In Patent Documents 1 to 4, each arithmetic block in the LSI is divided into a buffer unit and a logic unit, and after the data is transferred from the buffer unit, a power supply voltage is supplied to the logic unit, and the logic unit is not stopped until then. That is, a power supply control program is not created according to the configuration and operation of each calculation block, and the power supply control is not performed by the control program.

In addition, when a power control program is created, complicated control is required if there are a plurality of data paths in the LSI, so hardware suitable for power control is required.
JP 2004-015670 A WO99 / 66640 JP 2004-140503 A JP 2003-092359 A Note 1) Nikkei Business Publications, Nikkei Electronics 2004 4-26 no.872, p.99-127.

The present invention has been made in view of the above situation, and by constructing on a circuit a power supply control system that supplies power only to necessary operation blocks when necessary, reducing leakage current and reducing consumption. An object of the present invention is to provide a power supply control circuit that realizes power generation.

A semiconductor integrated circuit provided with an arithmetic block that executes arithmetic processing, which is one aspect of the present invention, receives input data and a Valid signal indicating whether the input data is valid data. A buffer unit of the arithmetic block for holding input data;
When the number of stored data held in the buffer unit reaches a preset number of data, the stored data is used to execute arithmetic processing, and the output data after execution of the arithmetic processing and the output data are valid. A logic part of the arithmetic block that outputs a Valid signal indicating
A power switch control unit that controls a switch unit of the arithmetic block that performs power on / off in order to supply power before the arithmetic processing is performed by the logic unit.

Preferably, the calculation block includes a selector unit configured to set a connection with a data network provided to input the input data and the Valid signal to the calculation block;
A data buffer unit that inputs the input data and the Valid signal via the selector unit and holds the input data for which the Valid signal is valid;
When the Valid signal is valid, the input data and the Valid signal are written to the data buffer unit, a control signal is output, the input data reaches the preset number of data, and the logic unit from the power switch control unit In response to a power supply instruction to the data buffer unit, a read control signal for starting data transfer from the data buffer unit is output to the data buffer unit, and the time from the start of power supply to the logic unit to the end of the arithmetic processing of the logic unit is counted. A W / R control unit.

Preferably, the power switch control unit may periodically notify the switching timing of the switch unit that controls power supply to the logic unit.
Preferably, a desired power consumption is reduced by determining an operating frequency of the logic unit based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation.

  With the above configuration, the circuit of each operation block that constitutes the LSI is subdivided, and the optimal power supply to the circuit that controls the power supply (the logic part of the operation block) can suppress the consumption of leakage current. Power consumption can be reduced. Further, the leakage current consumption can be further reduced by increasing the operating frequency ratio of the circuit capable of controlling the power supply.

According to another aspect of the present invention, a semiconductor integrated circuit provided with an operation block for executing an operation process receives input data and a Valid signal indicating whether the input data is valid data. A buffer unit of the arithmetic block that holds input data and issues a full signal when the number of stored data held reaches a preset number of data;
When the number of accumulated data held in the buffer unit reaches a preset number of data, the accumulated data is used to perform arithmetic processing, and the output data and the output data are valid after the arithmetic processing is performed. A logic part of the arithmetic block that outputs a Valid signal indicating
The logic block receives the power supply permission and the full signal to supply power before the execution of the calculation process, and controls the switch block of the calculation block that performs power on / off. When,
Issuing a token for controlling power on / off to the power control unit, permitting the power supply to the logic unit, and canceling the power supply permission from the power control unit when the logic unit completes the arithmetic processing A token issuing unit that receives the return token;
It comprises.

Preferably, the arithmetic block has a selector unit for setting a connection with the data network provided for inputting the input data and the Valid signal to the arithmetic block;
A data buffer unit that inputs the input data and the Valid signal via the selector unit and holds the input data for which the Valid signal is valid;
When the Valid signal is valid, the input data and the Valid signal are written to the data buffer unit, a control signal is output, the input data reaches the preset number of data, and data transfer from the data buffer unit is started. A W / R control unit that outputs a read control signal and a full signal to the power control unit to the data buffer unit;
When the power supply permission token to the logic unit issued from the token issuing unit and the full signal are received, the switch unit is switched to supply power to the logic unit, and from the start of power supply to the logic unit And a power supply control unit that counts the time until completion of the arithmetic processing of the logic unit.

Preferably, the operating frequency of the logic unit is determined based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation, thereby reducing desired power consumption.
With the above configuration, the program of the power switch control unit can easily create a program by paying attention only to token control without being aware of internal operations such as calculation start and end of A to Z.

A semiconductor integrated circuit provided with a calculation block for performing a calculation process according to another aspect of the present invention,
When input data and a Valid signal indicating whether the input data is valid data are input, the input data is held when the input data is valid, and the number of stored data held reaches a preset number of data A buffer unit of the arithmetic block for issuing a toggle signal;
When the number of stored data held in the buffer unit reaches a preset number of data, the stored data is used to execute arithmetic processing, and the output data after execution of the arithmetic processing and the output data are valid. A logic part of the arithmetic block that outputs a Valid signal indicating
The arithmetic block that receives the toggle signal from the buffer unit to supply power before the arithmetic processing is executed, and controls the switch unit of the arithmetic block that performs power on / off to the logic unit. A power supply control unit.

Preferably, a desired power consumption is reduced by determining an operating frequency of the logic unit based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation.
The above configuration simplifies power supply control. The order of data exchange between the operation blocks (data network topology) is switched, and when there are inputs from a plurality of operation blocks, the connection between the network and the operation blocks becomes complicated. In this case, only the relationship between the transfer source (source) calculation block and the transfer destination (target) calculation block may be defined in the power switch control unit in the calculation block. Further, fine control can be easily performed by subdividing the blocks.

According to the present invention, the consumption of leakage current can be suppressed by subdividing the circuit of each operation block constituting the LSI and supplying the optimum power to the circuit for controlling the power supply (the logic part of the operation block). The power consumption of the entire LSI can be reduced. Further, the leakage current consumption can be further reduced by increasing the operating frequency ratio of the circuit capable of controlling the power supply.

1 is a block diagram illustrating a configuration of Example 1. FIG. FIG. 3 is a block diagram illustrating a configuration of each calculation unit according to the first embodiment. It is a term chart which shows the calculation of a logic part. It is the figure which compared the reduction of leak current. FIG. 3 is a flowchart showing the operation of the first embodiment. It is a flowchart which shows operation | movement. It is a time chart which shows power supply control. 6 is a block diagram illustrating a configuration of Example 2. FIG. FIG. 10 is a block diagram illustrating a configuration of each calculation unit according to the second embodiment. FIG. 6 is a flowchart showing the operation of the second embodiment. 10 is a block diagram illustrating a configuration of Example 3. FIG. FIG. 10 is a block diagram illustrating a configuration of each calculation unit according to a third embodiment. FIG. 10 is a flowchart showing the operation of the third embodiment. FIG. 11 illustrates a structure of a transistor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Example 1
FIG. 1 is a schematic diagram showing the internal configuration of an LSI 1 using the present invention. FIG. 1 shows an example in which the LSI 1 is composed of a power supply unit 2, a data network 3, a power switch control unit 4, arithmetic blocks 5a to 5z, and the like.

  For example, when the function of the LSI 1 is considered as a baseband processing unit of a demodulation unit such as a wireless LAN, each of the operation blocks 5a to 5z can be considered as a circuit that realizes functions such as a filter unit and an FFT unit. When each function is executed serially as in the baseband processing, the arithmetic blocks 5a to 5z perform arithmetic processing and transfer data to the next arithmetic block via the data network 3. If the output of the previous stage calculation block is used as the input of the next stage calculation block after the previous stage calculation block has completed processing, the leakage current can be reduced only by supplying power to only the currently used calculation block. However, the present invention is not limited to the case of serial processing, and is effective in a system in which only the operation block being operated is operating and the other operation blocks are stopped.

  A power supply unit 2 shown in FIG. 1 supplies power to each circuit of the LSI 1. The data network 3 is configured by a crossbar network or a bus network, and is a data path that interconnects the operation blocks 5a to 5z. The data network 3 sends input data and valid data to each computation block, and further outputs output data of each computation block to the computation block and other peripheral circuits via the output network. The valid data is data for determining whether or not the input data used in each calculation block is valid. For example, it is synchronized with the clock and sent together with the data. Data and serial data transfer or parallel data transfer may be used.

  The power switch control unit 4 controls the power supply timing of each of the calculation blocks 5a to 5z. Each arithmetic block 5a-5z is provided with buffer units 6a-6z and logic units 7a-7z. The power supply unit 2 supplies both to the buffer units 6a to 6z and the logic units 7a to 7z. The buffer units 6a to 6z always supply power so that input data can be held at any time. The logic units 7a to 7z execute the arithmetic processing described above, and supply power by controlling the switch units 8a to 8z when performing the arithmetic processing. The configuration of the power switch control unit 4 may be a CPU, reconfigurable hardware, or dedicated hardware. When the program is executed by a CPU or the like or configured by reconfigurable hardware, the program is read when the LSI 1 is started and then executed.

  Next, the configuration of the operation blocks 5a to 5z is shown in FIG. The buffer unit 6 includes a selector unit 21, a W / R control unit 22, a data buffer unit 23, and the like. Input data and a Valid signal are input to the calculation blocks 5a to 5z, and output data and an output Valid signal after the calculation process are output.

  The selector unit 21 sets the connection between the data network 3 and the buffer unit 6 by the circuit setting signal, and takes in the input data and the Valid signal to the calculation block. For each calculation block, transfer source information of a transfer source calculation block that transmits input data and a Valid signal, and transfer destination information of a transfer destination calculation block that outputs input data and a Valid signal are set as output of the calculation block. .

  The W / R control unit 22 performs control for writing input data input via the selector unit 21 into the data buffer unit 23. The input data has data used in the logic unit 7 and is synchronized with a data input clock. Further, only valid input data is written into the data buffer unit 23 based on the Valid signal input via the selector unit 21. A power supply control signal (external operation start trigger) is periodically acquired from the power supply switch control unit 4, and transfer of data and a Valid signal to the logic unit 7 is started. For example, when a predetermined number of data is accumulated in the data buffer unit 23 and an external operation start trigger is received, the W / R control unit 22 outputs a read control signal to the data buffer unit 23 and starts transfer.

  The data buffer unit 23 performs data transfer to the logic unit 7. The data buffer unit 23 stores input data in the memory and transfers the data to the logic unit 7. The data write (Write) to the memory may be a method of storing data at a general address, or may be stored in the order of input like a FIFO.

  The switch unit 8 can control power supply by a transistor. For example, the inverter 24 and the transistors 25 and 26 are used for control. In this example, since the transistors 25 and 26 use different junctions, the power control signal (external operation start trigger) from the power switch control unit 4 is inverted by the inverter 24 and input to the transistor 25. One transistor 26 is input without being inverted.

Here, power on / off of the logic unit 7 is performed on the VDD side and the GND side of the logic unit 7, but only the VDD side may be used. When only the VDD side is used, the area is not wasted compared to the case where both are turned on compared to the case where the power is turned on / off on both sides. When inserted on the GND side, a potential difference may occur between the gate and the Si substrate of the transistor in the circuit block or between the gate and the drain (source), and the factor causing the gate leakage current may not be completely removed.
(Description of operation)
The input data is transferred from the input port to the operation blocks 5a to 5z via the data network 3 based on the data network setting previously set by the register. Then, the processed output data and the output Valid signal are output to another calculation block or output port.

  Here, consider a case where the calculation block 5a has a 64-point FFT, an operating frequency f = 40 MHz, and an operating frequency ratio m = 2. FIG. 3 shows a timing chart of (1) input data signal waveform, (2) data buffer unit 23 output signal waveform, and (3) change in Vdd '(power control signal).

  The waveform of (1) is sent to the calculation block 5a via the data network 3 on the operating frequency f = 40 MHz. Since the arithmetic block 5a operates at an operating frequency of f × m = 80 MHz, valid data is received once every two cycles. In the case of 64-point FFT, since 64 data are required for one FFT operation, 64 data are acquired over 128 cycles * (1/80 MHz). Next, 64 pieces of data are transferred from the buffer unit 6 to the logic unit 7. At that time, power is supplied to the logic unit 7 (Vdd 'is supplied), and Vdd' is shut off after the calculation is completed. The leakage current can be reduced only during the period when the supply of Vdd 'is stopped.

となる。Here, the memory size of the data buffer unit 23 differs depending on the operation assigned to the block unit 7. A 64-point FFT requires a minimum of 64 cycles. Assuming that the ratio of the leakage current of the logic unit 7 and the charge / discharge current for calculation is 1: 1, the current consumption is smaller than the conventional one.

It becomes.

When m = 2, the power consumption can be reduced to 3/4 of the conventional one as shown in FIG. Conventionally, at the frequency f = 1, the calculation process requiring power consumption 2 (the sum of the leak power 1 and the logic charge / discharge power 1) over the calculation time 0 to 2 in FIG. By doubling the power, the power source can be turned on for half the time of the prior art, and the leakage power can be reduced to ½. As a result of FIG. 5B, the effect of reducing the total power to 3/4 can be obtained. (Equation 1) shown above generalizes the power reduction effect with respect to the parameter m. The current consumption can be reduced as the operating frequency ratio m is increased. Further, as the circuit block is subdivided, the power source can be controlled more finely, and the current can be minimized by optimal control.
(Operation flow)
Next, the operation flow of the first embodiment will be described with reference to FIG.

  In step S51, a control program for the power switch control unit 4 is set. In step S52, as described above, the power control signal is transferred to each computation block to notify the power on / off timing.

  In step S53, each calculation block is set. In the W / R control unit 22, the number of accumulated data (Ndata) and the logic unit processing time (Toutoff) are set as constants by a circuit setting signal, and the data reading count number (Counter) and the logic unit processing time count number ( timer) is initialized. In the figure, initialization is set to 0 and up-counting is performed, but down-counting may be performed. Also, parameters for realizing functions are set for the logic unit 7. The parameters corresponding to the real part and imaginary part of the complex data are set by the circuit setting signal shown in FIG. For digital filter operation, the corresponding filter coefficient is set as a parameter.

  In step S54, the selector unit 21 of each calculation block shown in FIG. 2 is set (SEL) by the circuit setting signal shown in FIG. Here, the order of steps S51 to S54 of the setting process surrounded by a broken line does not limit the present invention. The setting process is a setting by a CPU or dedicated hardware responsible for overall control.

In step S55, the input data of each arithmetic unit and the Valid signal are taken into the data buffer unit 23 and the W / R control unit 22 based on the connection (SEL) of the selector unit 21.
In step S56, the W / R control unit 22 writes only data for which the Valid signal is valid to the data buffer unit 23. A write control signal is output to the data buffer unit 23 for writing. The W / R control unit 22 increments the data reading count (Counter) every time one valid data is written. Here, counting counts the number of valid data, and counts valid data.

  In step S57, it is determined whether a predetermined number of valid input data has been written in the data buffer unit 23. That is, it is determined whether the data reading count number (Counter) = the number of accumulated data (Ndata) is satisfied. If established (YES), the process proceeds to step S58, and if not established, the process loops at S57 until established.

  In step S58, the power supply control signal (external operation start trigger) from the power supply switch control unit 4 controls and turns on the switch unit 8 that supplies power to the logic unit 7 of the corresponding calculation block, and the logic unit processing time count number (Timer) starts counting up.

  In step S59, the data buffer unit 23 transfers the accumulated data for Ndata to the logic unit. In step S510, the logic unit 7 receives data and starts calculation. Thereafter, the data for which the operation has been completed is output from the logic unit 7 in step S511.

  Step S512 After the processing of the logic unit 7 is completed, if the logic unit processing time (Toutoff) = the logic unit processing time count (timer), the power supply is shut off. Also initialize variables.

  Next, as shown in FIG. 5, the process proceeds to step S55 in order to perform calculation processing in the next calculation block. For example, consider a case where the calculation block A shown in FIG. 6 is the first stage, the calculation block to be processed next is the calculation block B, and the processing up to the calculation block Z is sequentially processed. The calculation block B acquires input data from the calculation block A or the data network 3. The calculation block B completes the processing of the buffer unit and the processing of the logic unit in the same manner as the calculation block A, and moves to the calculation block C in the next stage. This process is repeated until the calculation up to the calculation block Z is performed.

Here, there is no problem even if the calculation block A and the calculation block B perform the calculation at the same time. When such parallel processing is necessary, the control program of the power switch control unit 4 is different from that shown in FIG. You can do it.
(Power control)
The operation of power supply will be described with reference to FIG. The waveform of period (c) shown in (a) of FIG. 7 indicates switching of the switch unit 8 (transistors 25 and 26 shown in FIG. 2). When the power supply to the logic unit 7 is started, the power supply voltage of the logic unit 7 shown in (b) rises, and after the period (b) in FIG. The period calculation process shown in FIG. Then, after the calculation is completed, the switch unit 8 is switched to cut off the power supply. Thus, when the control program of the power switch control unit 4 is created, it is necessary to provide a period (b) in which the logic unit 7 is in a stable operation state.

  As described above, only when the logic unit 7 operates, the power switch control unit 4 supplies power to the corresponding calculation block, so that power supply is stopped by stopping the power supply path every time the calculation process is completed. . However, the buffer unit 6 is always supplied with power. This is because data input is always possible regardless of the power supply state. The same applies to the buffer units 6 of all operation blocks. For this reason, it is possible to transfer data without being aware of the state of power supply to each other.

Further, as a clock to be given to the LSI 1 having the above system, a clock having an operating frequency m times as high as that of the input data is given to the logic unit to reduce the calculation time to 1 / m. As a result, the calculation time can be reduced to 1 / m, and the power supply time can be reduced to 1 / m of the conventional time, and the leakage current of the logic unit can be stopped during the power supply stop period.
(Example 2)
The second embodiment is not a direct control between the calculation block and the power switch control unit as shown in the first embodiment. A token bus is provided between the token issuing unit and each calculation block to supply power using a token (power supply right). Immediately after the LSI 81 is activated, a right is given to the first calculation block and the calculation is performed. Then, as soon as the computation in the computation block is completed, the right is returned to the power switch control unit. The token issuing unit that has received the return token passes the token to the next calculation block and starts supplying power.

FIG. 8 shows an example in which the LSI 81 is composed of a power supply unit 82, a data network 83, a token issuing unit 84, arithmetic blocks 85a to 85z, and the like.
For example, when the function of the LSI 81 is considered as a baseband processing unit of a demodulation unit such as a wireless LAN as in the first embodiment, each of the operation blocks 85a to 85z is a circuit that realizes functions such as a filter unit and an FFT unit. In addition, each of the operation blocks 85a to 85z performs an operation process and transfers it to the next operation block via the data network 83. If the output of the previous-stage calculation block is used as the input of the next-stage calculation block after the previous-stage calculation block completes processing, power is supplied only to the currently used calculation block, so that the leakage current can be reduced.

  The power supply unit 82 supplies power to each circuit of the LSI 81. The data network 83 is a data path that interconnects the operation blocks 85a to 85z configured by a crossbar network or a bus network. The data network 83 sends the input data and valid data to each arithmetic block, and further transfers the output data of each arithmetic block and the output Valid signal to other peripheral circuits via the arithmetic block and the output port. The valid data is data for determining whether or not the input data used in each calculation block is valid.

  The token issuing unit 84 controls the power supply timing of each of the operation blocks 85a to 85z. Each arithmetic block 85a to 85z is provided with buffer units 86a to 86z and logic units 87a to 87z. The power is supplied together with the buffer units 86a to 86z and the logic units 87a to 87z. The buffer units 86a to 86z always supply power so that input data can be held at any time as in the first embodiment. The logic units 87a to 87z supply power by controlling the switch units 88a to 88z by the power control units 89a to 89z only when executing the above-described arithmetic processing.

  The configuration of the token issuing unit 84 may be a CPU, reconfigurable hardware, or dedicated hardware. When the program is executed by a CPU or the like or configured by reconfigurable hardware, the program may be read and executed when the LSI 81 is activated.

Next, the operation blocks 85a to 85z have the configuration shown in FIG. The buffer unit 86 includes a selector unit 91, a W / R control unit 92, a data buffer unit 93, and the like.
Input data and a Valid signal are input to the operation blocks 85a to 85z. Output data and an output Valid signal are output from the arithmetic block.

The selector unit 91 presets the connection between the data network 83 and the buffer unit 86 by the circuit setting signal, and takes in the input data and the Valid signal to the calculation block.
The W / R control unit 92 performs control for writing the input data and the valid signal input via the selector unit 91 into the data buffer unit 93. The input data has a data value used in the logic unit 87 and is synchronized with a data input clock. Further, only valid input data is written to the data buffer unit 93 based on the Valid signal input via the selector unit 91.

  The data buffer unit 93 stores input data in the memory and transfers the data to the logic unit 87. The data write (Write) to the memory may be a method of storing data at a general address, or may be stored in the order of input like a FIFO. Further, data transfer to the logic unit 87 is performed.

  The power supply control unit 89 in the calculation block switches the switch unit 88 when detecting that a predetermined number of data is accumulated in the data buffer unit 93 and a token is acquired from the token issuing unit 84. Then, power is supplied to the logic unit 87. Transfer of accumulated data to the logic unit 87 is started in the data buffer unit 93.

The switch unit 88 controls power supply by transistors 95 and 96. For example, control is performed using an inverter 94 and transistors 95 and 96. In this example, since the transistors 95 and 96 use different junctions, the power supply control signal (operation start trigger) from the power supply control unit 89 is inverted by the inverter 94 and input to the transistor 95. The signal is input to one transistor 96 without being inverted. The power supply is turned on / off on the VDD side and the GND side. In this example, the GND side is switched by the transistor 96, but only the VDD side may be switched.
(Description of operation)
Next, the operation flow of the second embodiment will be described with reference to FIG.

  In step S101, the token issuing unit 84 sets a control program for issuing a token. As described above, a token is issued to each calculation block to give a right to the calculation block and notify the power on / off timing.

  In step S102, parameters for realizing the function are set for the logic unit. The parameters corresponding to the real and imaginary parts of the complex data are set by the circuit setting signal shown in FIG. If it is a digital filter operation, a corresponding filter coefficient parameter is set.

In step S103, the selector unit 91 of each calculation block shown in FIG. 10 is set (SEL) by the circuit setting signal shown in FIG.
In step S104, the power supply of each calculation block is set. In the W / R control unit 92, the number of accumulated data (Ndata) and the logic unit processing time (Toutoff) are set as constants. In step S105, a data reading count number (Counter) and a logic unit processing time count number (timer) are initialized as variables. In the figure, initialization is set to 0 and up-counting is performed, but down-counting may be performed. Here, the order of steps S101 to S105 in the setting process surrounded by a broken line is not limited. The setting process is a setting by a CPU or dedicated hardware responsible for overall control.

In step S106, the token issuing unit 84 issues a token to the target calculation block.
In step S107, the input data of each arithmetic unit and the Valid signal are fetched based on the connection (SEL) of the selector unit 91.

  In step S <b> 108, the W / R control unit 92 writes only data for which the Valid signal is valid to the data buffer unit 93. When the Valid signal is valid, the input data and the Valid signal are written to the data buffer unit 93 and a control signal is output. Each time one piece of Valid data is written, the data reading count (Counter) is incremented.

  In step S109, the power supply control unit 89 receives the token, and determines whether a predetermined number of valid input data has been written in the data buffer unit 93. That is, it is determined whether the data reading count number (Counter) = the number of accumulated data (Ndata) is satisfied. If established (YES), the process proceeds to step S1010, and if not established, the process loops at S109 until established. When the number of data set in advance is reached, the W / R control unit outputs a read control signal for starting data transfer from the data buffer unit 103 and a full signal to the power control unit 103 to the data buffer unit 103.

  In step S1010, the power supply control signal (operation start trigger) from the power supply control unit 89 controls and turns on the switch unit 88 that supplies power to the logic unit 87 of the corresponding calculation block, and the logic unit processing time count (timer). ) Starts counting up.

  In step S1011, the data buffer unit 93 transfers the accumulated data for Ndata to the logic unit. In step S1012, the logic unit 87 receives data and starts calculation. Thereafter, the data for which the calculation has been completed is output from the logic unit 87 in step S1013.

  In step S1014, after the processing of the logic unit 87 is completed, the power is turned off when the logic unit processing time (Toutoff) = the logic unit processing time count (timer). Also initialize variables.

In step S 1015, the power supply control unit 89 returns the right to the token issuing unit 84. In step S1016, the token issuing unit 84 receives the return token.
Then, the process proceeds to step S106 in order to perform calculation processing in the next calculation block. For example, the calculation block A is the first stage, the calculation block to be processed next is the calculation block B, and the calculation block Z is processed in order. The calculation block B acquires input data from the calculation block A or the data network 3. The calculation block B completes the processing of the buffer unit and the processing of the logic unit in the same manner as the calculation block A, and moves to the calculation block C in the next stage. This process is repeated until the calculation up to the calculation block Z is performed.

Here, there is no problem even if the calculation block A and the calculation block B perform the calculation at the same time. If such parallel processing is required, the control program of the token issuing unit 84 may be a parallel program different from that shown in FIG. Good.
(Example 3)
When the order of data transfer between blocks (data network topology) is switched, or when there are inputs from a plurality of operation blocks, the connection between the network and the operation blocks becomes complicated. In that case, only the relationship between the source computation block and the target computation block need be defined in the power supply control unit. Fine-grained control can be easily performed by subdividing the calculation block.

FIG. 11 shows an example in which the LSI 111 is configured from a power supply unit 112, a data network 113, arithmetic blocks 114a to 114z, and the like.
For example, when the function of the LSI 111 is considered as a baseband processing unit of a demodulation unit such as a wireless LAN as in the first embodiment, each of the operation blocks 114a to 114z is a circuit that realizes functions such as a filter unit and an FFT unit. In addition, each of the operation blocks 114 a to 114 z performs an operation process and transfers it to the next operation block via the data network 113. If the output of the previous-stage calculation block is used as the input of the next-stage calculation block after the previous-stage calculation block completes processing, power is supplied only to the currently used calculation block, so that the leakage current can be reduced.

  The power supply unit 112 supplies power to each circuit of the LSI 111. The data network 113 is a data path that interconnects the operation blocks 114a to 114z configured by a crossbar network or a bus network. The data network 113 sends the input data and the valid signal to each arithmetic block, and further transfers the output data of each arithmetic block and the output Valid signal to other peripheral circuits via the arithmetic block and the output port.

  Each calculation block 114a-114z is provided with buffer part 115a-115z and logic part 116a-116z. The power is supplied to the buffer units 115a to 115z and the logic units 116a to 116z. The buffers 115a to 115z always supply power so that input data can be held at any time. The logic units 116a to 116z execute the arithmetic processing described above, and supply power by controlling the switch units 117a to 117z when performing the arithmetic processing. The power control units 118a to 118z of the calculation blocks 114a to 114z control power supply timing.

  Next, the calculation blocks 114a to 114z have the configuration shown in FIG. The buffer unit 115 includes a selector unit 121, a W / R control unit 122, a data buffer unit 123, and the like.

The operation blocks 114a to 114z are provided with an input port for inputting input data and a Valid signal and an output port for output data from the operation block.
The selector unit 121 sets the connection between the data network 113 and the buffer unit 115 based on the circuit setting signal, and takes the input data and the Valid signal into the calculation block.

  The W / R control unit 122 performs control for writing the input data input via the selector unit 121 into the data buffer unit 123. Further, the W / R control unit 122 switches the switch unit 117 by a toggle signal. When a predetermined number of data is accumulated in the data buffer unit 123, transfer to the logic unit 116 is started. The input data has data used in the logic unit 116 and is synchronized with the data input clock. Further, only valid input data is written into the data buffer unit 123 based on the Valid signal input via the selector unit 121.

  The data buffer unit 123 stores input data in the memory and transfers the data to the logic unit 116. The data write (Write) to the memory may be a method of storing data at a general address, or may be stored in the order of input like a FIFO.

  The switch unit 117 can control power supply by the transistors 125 and 126 and the like. For example, control is performed using an inverter 124 and transistors 125 and 126. In this example, since the transistors 125 and 126 are different junctions, the signal from the power supply control unit 118 is inverted by the inverter 124 and input to the transistor 125. The signal is input to one transistor 126 without being inverted.

In this example, the transistor 126 is switched on the GND side, but only the transistor 125 is used and only the VDD side is switched.
(Description of operation)
In the third embodiment, after setting of the logic unit 116, the W / R control unit 122, and the selector unit 121 is completed by a circuit setting signal, (1) input data is taken into the calculation block via the selector unit. Only input data for which the Valid signal is valid is selected by the W / R control unit 122 and written to the data buffer unit 123. The data buffer unit 123 transfers the data to the logic unit 116 when a certain number of data determined by the circuit setting signal is accumulated in the data buffer unit 123. The W / R control unit 122 turns on the power supply Vdd ′ and the ground GND ′ to supply power by sending a signal serving as a toggle for conducting the switch to the power supply control unit 118 simultaneously with data writing. In addition, after the processing data is output from the logic unit 116, the W / R control unit 122 sends a toggle signal to shut off the power supply. Timing setting from power supply to shut-off is performed by a circuit setting signal.

Next, the operation flow of the third embodiment will be described with reference to FIG.
In step S131, parameters for realizing the function are set for the logic unit. The parameter corresponding to the real part and the imaginary part of the complex data is set by the circuit setting signal shown in FIG. If it is a digital filter operation, a corresponding filter coefficient parameter is set.

In step S132, the selector 121 of each calculation block is set (SEL) by the circuit setting signal shown in FIG.
In step S133, the power supply of each calculation block is set. In the W / R control unit 122, the number of accumulated data (Ndata) and the logic unit processing time (Toutoff) are set as constants. In step 134, the data reading count number (Counter) and the logic section processing time count number (timer) are initialized as variables. In the figure, initialization is set to 0 and up-counting is performed, but down-counting may be performed. Here, the order of steps S131 to S134 in the setting process surrounded by a broken line is not limited.

In step S135, the input data of each arithmetic unit and the Valid signal are fetched based on the connection (SEL) of the selector unit 121.
In step S136, only data for which the Valid signal is valid is written to the data buffer unit 123, and the data reading count (Counter) is incremented each time one piece of Valid data is written. When the Valid signal is valid, the input data and the Valid signal are written to the data buffer unit 123 and a control signal is output.

In step S137, it is determined whether a predetermined number of valid input data has been written in the data buffer unit 123. That is, it is determined whether the data reading count number (Counter) = the number of accumulated data (Ndata) is satisfied. If it is satisfied (YES), the process proceeds to step S138, and if it is not satisfied, the process loops at S137 until it is satisfied. When the number of data set in advance is reached, the W / R control unit outputs a read control signal for starting data transfer from the data buffer unit 123 and a full signal to the power control unit 123 in step S138. The control unit 118 receives and controls the switch unit 117 that supplies power to the logic unit 116 to make it conductive. Then, the logic unit processing time count number (timer) starts to be counted up.

  In step S139, the data buffer unit 123 transfers the accumulated data for Ndata to the logic unit 116. In step S1310, the logic unit 116 receives data and starts calculation. Thereafter, the data and the Valid signal are output from the logic unit 106 in step S1311 for the data for which the operation has been completed.

  In step S1312, after the processing of the logic unit 116 is completed, if the logic unit processing time (Toutoff) = the logic unit processing time count (timer), the power supply is shut off. Also initialize variables.

  Then, the process proceeds to step S135 in order to perform calculation processing in the next calculation block. For example, the calculation block A is the first stage, the calculation block to be processed next is the calculation block B, and the calculation block Z is processed in order. The calculation block B acquires input data from the calculation block A or the data network 3. The calculation block B completes the processing of the buffer unit and the processing of the logic unit in the same manner as the calculation block A, and moves to the calculation block C in the next stage. This process is repeated until the calculation up to the calculation block Z is performed.

Here, there is no problem even if different calculation blocks perform calculations simultaneously.
The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.

Claims (9)

A semiconductor integrated circuit provided with an arithmetic block for executing arithmetic processing,
A buffer portion of the arithmetic block that receives input data and a Valid signal indicating whether the input data is valid, and holds the input data when the data is valid;
When the number of stored data held in the buffer unit reaches a preset number of data, the stored data is used to execute arithmetic processing, and the output data after execution of the arithmetic processing and the output data are valid. A logic part of the arithmetic block that outputs a Valid signal indicating
A power switch control unit that controls a switch unit of the computation block that performs power on / off to supply power before the logic unit performs computation processing;
A semiconductor integrated circuit comprising: The calculation block is:
A selector unit for setting a connection with a data network provided for inputting the input data and the Valid signal to the arithmetic block;
A data buffer unit that inputs the input data and the Valid signal via the selector unit and holds the input data for which the Valid signal is valid;
When the Valid signal is valid, the input data and the Valid signal are written to the data buffer unit, a control signal is output, the input data reaches the preset number of data, and the logic unit from the power switch control unit In response to a power supply instruction to the data buffer unit, a read control signal for starting data transfer from the data buffer unit is output to the data buffer unit, and the time from the start of power supply to the logic unit to the end of the arithmetic processing of the logic unit is counted. A W / R control unit,
The semiconductor integrated circuit according to claim 1, comprising: The power switch controller
2. The semiconductor integrated circuit according to claim 1, wherein a switching timing of the switch unit that controls power supply to the logic unit is periodically notified.   2. The semiconductor according to claim 1, wherein a desired power consumption is reduced by determining an operating frequency of the logic unit based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation. Integrated circuit. A semiconductor integrated circuit provided with an arithmetic block for executing arithmetic processing,
When input data and a Valid signal indicating whether the input data is valid data are input, the input data is held when the input data is valid, and the number of stored data held reaches a preset number of data A buffer unit of the operation block for issuing a full signal;
When the number of accumulated data held in the buffer unit reaches a preset number of data, the accumulated data is used to perform arithmetic processing, and the output data and the output data are valid after the arithmetic processing is performed. A logic part of the arithmetic block that outputs a Valid signal indicating
The logic block receives the power supply permission and the full signal to supply power before the execution of the calculation process, and controls the switch block of the calculation block that performs power on / off. When,
Issuing a token for controlling power on / off to the power control unit, permitting the power supply to the logic unit, and canceling the power supply permission from the power control unit when the logic unit completes the arithmetic processing A token issuing unit that receives the return token;
A semiconductor integrated circuit comprising: The calculation block is:
A selector unit for setting a connection with a data network provided for inputting the input data and the Valid signal to the arithmetic block;
A data buffer unit that inputs the input data and the Valid signal via the selector unit and holds the input data for which the Valid signal is valid;
When the Valid signal is valid, the input data and the Valid signal are written to the data buffer unit, a control signal is output, the input data reaches the preset number of data, and data transfer from the data buffer unit is started. A W / R control unit that outputs a read control signal and a full signal to the power control unit to the data buffer unit;
When the power supply permission token to the logic unit issued from the token issuing unit and the full signal are received, the switch unit is switched to supply power to the logic unit, and from the start of power supply to the logic unit A power supply control unit that counts the time until the arithmetic processing of the logic unit is completed;
The semiconductor integrated circuit according to claim 5, comprising:   6. The semiconductor according to claim 5, wherein a desired power consumption is reduced by determining an operating frequency of the logic unit based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation. Integrated circuit. A semiconductor integrated circuit provided with an arithmetic block for executing arithmetic processing,
When input data and a Valid signal indicating whether the input data is valid data are input, the input data is held when the input data is valid, and the number of stored data held reaches a preset number of data A buffer unit of the arithmetic block for issuing a toggle signal;
When the number of stored data held in the buffer unit reaches a preset number of data, the stored data is used to execute arithmetic processing, and the output data after execution of the arithmetic processing and the output data are valid. A logic part of the arithmetic block that outputs a Valid signal indicating
The arithmetic block that receives the toggle signal from the buffer unit to supply power before the arithmetic processing is executed, and controls the switch unit of the arithmetic block that performs power on / off to the logic unit. A power control unit of
A semiconductor integrated circuit comprising:   6. The semiconductor according to claim 5, wherein a desired power consumption is reduced by determining an operating frequency of the logic unit based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation. Integrated circuit.

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