JP2004152321A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor capable of dynamically terminating operation stop of a built-in circuit of which the operation is stopped by a selective operation stopping function, and of executing fine low power consumption control. <P>SOLUTION: This data processor includes: a central processor (2) for executing instructions; first circuits (3 and 4) connected to the central processor via internal buses (13 and 14); and a stop control circuit (12C) for selectively stopping the operation of the circuits. The central processor has an instruction control means (2C) used for, when an instruction using the first circuits is decoded by inputting stop control signals SFPU and SMLT outputted from the stop control circuit, starting the execution operation of the instruction after terminating the operation stop state of the first circuits by the stop control circuit in the case where the stop control signals order the stop. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a data processing device capable of selectively stopping operation of a built-in circuit in order to reduce power consumption, and more particularly to a data processing device in which an instruction to a built-in circuit in a stopped state is executed improperly or erroneously. A technology for preventing malfunctions, and a technology for performing low power consumption control, for example, a technology effective when applied to a semiconductor integrated circuit data processing device such as a single-chip microcomputer or a single-chip microcontroller. It is.

  There is known a technique for selectively stopping the operation of a built-in circuit module in order to reduce the power consumption of a data processing device. For example, a control register is provided in a clock signal generation circuit that forms an internal operation clock signal of the data processing device. Control bits are assigned to each of the built-in circuit modules in the control register, and the control bits are assigned according to the logical value of the control bits. Supply of the clock signal to the built-in circuit module can be selectively stopped. Such a technique is described in Patent Document 1, for example.

JP-A-7-287699

  However, when the operation of the built-in circuit module is selectively stopped for low power consumption, if an instruction for processing the built-in module is executed illegally or erroneously, an illegal memory access or register access may cause The present inventor has found that data may be destroyed or malfunction may occur.

  For example, in a microcomputer having a built-in floating point arithmetic unit and timer together with a central processing unit, the supply of an operation clock signal to the floating point arithmetic unit and timer can be selectively stopped individually. I do. The floating-point arithmetic unit has a data register, and the data register is loaded with operation data from a memory, and the operation data is stored in the memory from the register. At this time, performing the addressing operation for load and store processing between the memory and the data register by the central processing unit is excellent in suppressing an increase in circuit scale. This is because it is not necessary for the floating point arithmetic unit to have the same addressing mode as that of the central processing unit. However, when the supply of the clock signal to the floating-point arithmetic unit is stopped, if the central processing unit incorrectly or erroneously executes the floating-point instruction, the store operation from the data register of the floating-point arithmetic unit to the memory is not performed. It may be performed as desired. If this is the case, the data in the memory at the storage destination is undesirably destroyed by the addressing operation performed by the central processing unit even though the floating-point arithmetic unit is not actually operated. Further, when the supply of the clock signal to a specific peripheral circuit is stopped, if the central processing unit incorrectly or erroneously executes a store instruction using the data register of the peripheral circuit as a source, the data register of the peripheral circuit The store operation to the memory is performed undesirably. If so, the data in the memory at the storage destination is undesirably destroyed by the addressing operation performed by the central processing unit, even though the peripheral circuit is not actually operated.

  In addition, the present inventor has studied the release of the operation stop of the built-in circuit whose operation has been stopped by the selective operation stop function in the microcomputer. In the related art, when the operation is desired to be resumed, it is not possible to execute an instruction using the built-in circuit relating to the operation stop unless the setting of the control register is changed in advance. Therefore, when necessary, the operation of the built-in circuit related to the operation stop cannot be immediately restarted.

  SUMMARY OF THE INVENTION It is an object of the present invention to provide a data processing device capable of preventing an illegal memory access caused by erroneously operating a circuit stopped by a selective operation stop function.

  Another object of the present invention is to provide a data processing device capable of dynamically releasing the suspension of operation of a built-in circuit that has been suspended by a selective suspension function and capable of finely controlling power consumption. It is in.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

  [1] A data processing device (1) according to a first aspect of the present invention includes a central processing unit (2) for executing instructions and a data processing device coupled to the central processing unit via internal buses (13, 14). And a stop control circuit (12) for selectively stopping the operation of the first circuit, wherein the central processing unit outputs a stop control signal output from the stop control circuit. When inputting (SFPU, SMLT) and decoding the command using the first circuit, the command using the first circuit is invalid or the condition that the stop control signal indicates a stop. An instruction control means (2B) for processing as an invalid instruction is provided. As a result, an instruction in which the first circuit whose operation is selected to be stopped by the operation stop function of the built-in circuit is erroneously operated is processed as an invalid instruction or an invalid instruction. Can be prevented. When invalidated, the central processing unit executes the next instruction. When the instruction is invalidated, the central processing unit branches to exception processing and executes an exception processing routine defined by a user or the like.

  [2] A data processing device (1C) according to a second aspect of the present invention includes a central processing unit (2) for executing an instruction and a central processing unit coupled to the central processing unit via internal buses (13, 14). And a stop control circuit (12C) for selectively stopping the operation of the first circuit, wherein the central processing unit outputs a stop control signal output from the stop control circuit. When inputting (SFPU, SMLT) and decoding the instruction using the first circuit, if the stop control signal indicates stop, the stop control circuit stops the operation of the first circuit. And an instruction control means (2C) for starting the execution of the instruction after canceling the instruction. Thus, when an instruction is executed such that the first circuit whose operation has been selected to be stopped by the operation stop function of the internal circuit is executed, the operation stop state of the first circuit is released. As a result, the suspension of the operation of the built-in circuit can be dynamically released, and fine low power consumption control can be performed.

  [3] In the first and second aspects, the first circuit may be, for example, a floating unit which is controlled by the central processing unit executing a floating-point processing instruction and is subjected to addressing control by the central processing unit. A decimal point arithmetic unit (3) can be used. Further, the first circuit is a product-sum operation device (4) that is controlled by the central processing unit executing a product-sum operation processing instruction and that is operated under addressing control by the central processing unit. be able to.

  [4] A data processing device (1) according to a third aspect of the present invention comprises a central processing unit (2) for executing an instruction and an interface with the central processing unit via an internal bus (13, 14). An arithmetic unit (3, 4) which receives addressing control and arithmetic control of the processing unit; and a bus state controller (6) coupled to the internal bus, which interfaces with the central processing unit to control access of the central processing unit. Receiving peripheral circuits (9, 10, 11), an external bus interface circuit (8) for externally connecting the bus state controller, and a stop control circuit (27) capable of selectively stopping operations of the arithmetic unit and the peripheral circuits. 12), the bus state controller outputs a first stop control signal (SSCI, TMR, enter the SADC), and outputs a bus error signal when it detects the access to the peripheral circuit operation stopped by the first stop control signal is indicated (24) as an exception process request signal by the central processing unit. Thus, when an instruction that causes the peripheral circuit whose operation stop is selected by the operation stop function of the built-in peripheral circuit to be erroneously operated is executed, a bus error is generated, and exception processing is performed for the bus error. Therefore, the occurrence of an illegal memory access can be prevented.

  [5] In the above [4], the central processing unit inputs a second stop control signal (SFPU, SMLT) for the arithmetic unit output from the stop control circuit, and issues an instruction to use the arithmetic unit. When decoding the instruction, the instruction control means (2B) for processing an instruction using the arithmetic unit as an illegal instruction or an invalid instruction on condition that the second stop control signal indicates stop. . As a result, an instruction in which the operation device selected to stop the operation by the operation stop function of the built-in circuit is erroneously operated is processed as an invalid instruction or an invalid instruction, and as a result, an illegal memory access occurs. Can be prevented.

  [6] A data processing device (1C) according to a fourth aspect of the present invention includes a central processing unit (2) for executing an instruction and an interface with the central processing unit via an internal bus (13, 14). An arithmetic unit (3, 4) that receives addressing control and arithmetic control of the processing unit; and a bus state controller (6C) coupled to the internal bus to interface with the central processing unit to control access to the central processing unit. Receiving peripheral circuits (9, 10, 11), an external bus interface circuit (8) for externally connecting the bus state controller, and a stop control circuit (27) capable of selectively stopping operations of the arithmetic unit and the peripheral circuits. 12C), wherein the bus state controller (6C) outputs a first stop control signal for the peripheral circuit output from the stop control circuit. (SSCI, STMR, SADC), and when detecting an access to a peripheral circuit whose operation is instructed by the first stop control signal, release the operation stop state of the peripheral circuit, and Activate the bus cycle. With this, when the peripheral circuit whose operation stop is selected by the operation stop function of the built-in peripheral circuit is operated, the operation stop state of the peripheral circuit is released. As a result, the suspension of the operation of the built-in peripheral circuit can be dynamically released, and fine low power consumption control can be performed.

  [7] In the above [6], the central processing unit inputs a second stop control signal (SFPU, SMLT) for the arithmetic unit output from the stop control circuit, and issues an instruction using the arithmetic unit. When the second stop control signal indicates stop, an instruction control means for releasing the operation stop state of the arithmetic unit by the stop control circuit and then starting the execution of the instruction (2C). Thus, when the operation device whose operation stop is selected by the operation stop function of the built-in circuit is operated, the operation stop state of the operation device is released. As a result, the suspension of the operation of the built-in circuit can be dynamically released, and fine low power consumption control can be performed. In the above [6], the central processing unit inputs a second stop control signal for the arithmetic unit output from the stop control circuit, and decodes a command using the arithmetic unit when the second stop control signal is input. Command control means for processing a command using the arithmetic device as an illegal command or an invalid command on condition that the stop control signal indicates stop. As a result, an instruction to operate the arithmetic unit whose operation is selected to be stopped is processed as an illegal instruction or an invalid instruction, thereby preventing occurrence of an illegal memory access and the like, and preventing the built-in peripheral circuit from being executed. Can dynamically release the suspension of operation.

  The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.

  That is, it is possible to prevent an illegal memory access caused by erroneously operating a circuit that has been stopped by the selective operation stop function in the data processing device. In addition, the operation stop of the built-in circuit whose operation has been stopped by the selective operation stop function in the data processing device can be dynamically released, and fine low power consumption control can be performed.

<< Invalid instruction (illegal instruction), memory protection by bus error >>
FIG. 1 shows a single-chip microcomputer (called a microcomputer) 1 as a first example of a data processing device according to the present invention. Although not particularly limited, the microcomputer 1 shown in FIG. 1 is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The microcomputer 1 includes, but is not limited to, a central processing unit (CPU) 2 for performing an integer operation and a floating-point operation unit (FPU) 3 for performing a floating-point operation. Further, it has a product-sum operation device 4 specialized for the product-sum operation frequently used in digital signal processing.

  Central processing unit 2 is coupled to internal address bus 14 and internal data bus 13. Although not particularly limited, the central processing unit 2 controls an operation unit 2A represented by a general-purpose register or an arithmetic and logic unit, a control register group such as a program counter, and fetching and decoding instructions and an instruction execution procedure. It has an instruction control unit 2B for performing arithmetic control. The central processing unit 2 fetches an instruction from an unillustrated external memory connected to the external buses 17 and 18 or an unillustrated internal memory connected to the internal buses 13 and 14, decodes the instruction, and decodes the instruction. By generating a control signal corresponding to the result, data processing according to the command is performed.

  The floating point arithmetic unit (FPU) 3 and the product-sum arithmetic unit 4 are coupled to the internal data bus 13. The floating-point arithmetic unit (FPU) 3 and the product-sum arithmetic unit 4 have a data register together with an arithmetic circuit (not shown). The data register is loaded with arithmetic data from a memory, and the arithmetic result data is loaded from the register to the memory. Stored. The CPU 2 performs the addressing operation for the load, store, and the like. Therefore, the FPU 3 and the product-sum operation device 4 do not need to have a memory addressing capability for memory access. This is to save the chip area by eliminating the need for the memory addressing circuit by the FPU 3 and the product-sum operation unit 4.

  Internal data bus 13 and internal address bus 14 are coupled to bus state controller 6. External access by the microcomputer 1 is performed by an external bus interface circuit 8 connected to the bus state controller 6. The external bus interface circuit 8 is connected to the external data bus 18 and the external address bus 17. The bus state controller 6 is connected to the clock generation circuit 7, the system controller 12, the serial communication interface controller (SCI) 9, the timer 10, and the A / D converter via the peripheral data bus 16 and the peripheral address bus 15, for example. 11 are combined. These peripheral circuits have a data register and a control register, and these registers are accessed by the CPU 2 via the bus state controller 6.

  The assignment of address areas to the internal memory space and the external memory space managed by the CPU 2 and peripheral circuits such as the SCI 9, timer 10, and A / D converter 11 is determined in advance. The bus state controller 6 has a bus control register (not shown) in which the number of access cycles, bus width, and the like are set by the CPU 2 for each access area. Bus control such as the number of access cycles is performed to activate a bus cycle. An access instruction from the CPU 2 is given to the bus state controller 6 as a bus command 23. The bus command 23 includes designation of an access size and strobe signals such as read, write, and memory access.

  The interrupt controller 5 performs priority control, mask control, and the like on a plurality of interrupt requests, and supplies an interrupt signal 25 to the CPU 2. The interrupt request is given by a bus error signal 24 from the bus state controller 6, an SCI 9, a timer 10, the A / D converter 11, and an external interrupt request signal (not shown).

  Although not particularly limited, the microcomputer 1 is operated in synchronization with clock signals CLK0 to CLK2 output from the clock generation circuit 7. The clock signal CLK0 is supplied to a clock driver (not shown) included in each of the CPU 2, the product-sum operation device 4, an internal memory (not shown), and the FPU 3, and the CPU 2, the product-sum operation device 4, FPU 3, and the illustration are omitted. The operation reference clock signal of the internal memory to be used. The clock signal CLK1 is a synchronous clock signal for external access, and is supplied to a clock driver (not shown) of the external bus interface circuit 8. The clock signal CLK2 is supplied to a clock driver (not shown) for the SCI 9, the timer 10, and the A / D 11, and is used as a synchronous clock signal for the SCI 9, the timer 10, and the A / D 11. The bus state controller 6 synchronizes input / output operations on the internal buses 13 and 14 with the clock signal CLK0, synchronizes input / output operations on the peripheral buses 15 and 16 with the clock signal CLK3, and inputs / outputs via the external bus interface circuit 8. The output operation is synchronized with the clock signal CLK2. Needless to say, an operation clock signal (not shown) is supplied to other circuits.

  The system controller 12 controls the operation stop of the built-in module of the microcomputer 1. That is, the system controller 12 has a clock stop control register 12R accessed by the CPU 2, and clock control bits SFPU, SMLT, SSCI, STMR, and SADC are assigned to the register 12R. The clock control bits SFPU, SMLT, SSCI, STMR, and SADC are supplied to control terminals of the FPU 3, the product-sum operation device 4, the SCI 9, the timer 10, and the clock driver (not shown) built in the A / D converter 11, When it is set to the set state (logical value “1”), the output of the clock driver of the corresponding built-in module is fixed at a fixed level, and the operation of the built-in module is stopped. In the reset state (logic value “0”), the clock output operation of the corresponding clock driver is enabled, and the corresponding built-in module is enabled.

  FIG. 2 shows a configuration for memory protection by invalid instruction (illegal instruction). The clock control bits SFPU and SMLT are also supplied to the CPU 2 for memory protection by invalidating instructions (invalid instructions). Accordingly, when decoding the instruction using the FPU 3, the instruction control unit 2B of the CPU 2 processes the instruction as an illegal instruction or an invalid instruction on condition that the clock control bit SFPU is set. Similarly, when the instruction control unit 2B of the CPU 2 decodes an instruction using the product-sum operation unit 4, the instruction control unit 2B processes the instruction as an illegal instruction or an invalid instruction on condition that the clock control bit SMLT is set. The invalid instruction is a so-called NOP (non-operation), and the next instruction is executed. The illegal instruction is a so-called undefined instruction, the execution of the instruction currently being processed is interrupted, and the process branches to a process defined by an exception handling routine defined by the user. In any case, the execution of the instruction using the FPU 3 and the product-sum operation unit 4 is stopped at that time. Therefore, when the operation of the FPU 3 or the multiply-accumulate operation unit 4 is stopped, it is possible to prevent a possibility that an instruction using them is erroneously or improperly executed, resulting in improper memory access and data corruption. You can do it.

  FIG. 3 shows a configuration for performing memory protection by generating a bus error. Clock control bits SSCI, STMR, and SADC are also supplied to the bus state controller 6 to generate a bus error and protect the memory. As a result, the bus state controller 6 outputs a bus error signal 24 to the interrupt controller 5 when detecting an access to a peripheral circuit whose operation is instructed by the clock control bits SSCI, STMR, and SADC. In accordance with this, the interrupt controller 5 asserts the interrupt signal 25 to the CPU 2, and the CPU 2 performs exception processing according to the exception factor (bus error). Here, the exception process is a first exception process in which the process being executed is interrupted and the process is not returned to the interrupted process after the exception process is performed. The exception process is interrupted after the process in progress is interrupted and the exception process is performed. There is a second exception process that returns to the completed process, but the exception process for the bus error belongs to the category of the first exception process. Thereby, when the operation of the peripheral circuits such as the SCI 9 is stopped, the possibility that the instructions using them are erroneously or incorrectly executed, resulting in improper memory access and data corruption is prevented. Can do things.

  A specific configuration for protecting the memory by invalidating or invalidating instructions by the CPU 2 will be further described. Although the instruction of the CPU 2 is not particularly limited, the instruction is a 16-bit fixed-length instruction, and a specific field, for example, 4 bits from the most significant side is a code for roughly classifying the instruction type. The kind value is, for example, a logical operation instruction, a shift instruction, a branch instruction, a system control instruction, a floating-point instruction, a product-sum operation instruction, and the like. Incidentally, the four most significant bits of the floating point instruction are set to "1111". The four most significant bits of the product-sum operation instruction are set to “0011”. The four most significant bits constitute an operation code together with the instruction codes of other predetermined fields. When an instruction has an operand designation field, it designates an address area to be accessed by a register or an instruction according to an addressing mode.

  FIG. 4 shows a schematic configuration of the instruction control unit 2B. The instruction control unit 2B has a predecoder 200 and a hard wired logic 201. The hard wired logic 201 has logical operation control logic, branch processing control logic, floating point operation control logic, product-sum operation control logic, illegal instruction control logic, invalid instruction (NOP) control logic, and the like, and performs processing according to the instruction. Is provided for outputting a control signal for realizing the above. The predecoder 200 is supplied with an instruction code and the clock control bits SFPU, SMLT, SSCI, STMR, SADC, and the like. The predecoder 200 decodes the instruction code and outputs entry designation data corresponding to the decoding result to the hard wired logic 201. The hard-wired logic 201 selects a logic specified by the entry specification data and outputs various control signals. The control signals indicated by 20, 21, 22 are representatively representative of the control signals supplied to the product-sum operation unit 4, the FPU 3, and the operation unit 2A of the CPU 2.

  At this time, the pre-decoder 200 refers to the clock control bits SFPU, SMLT, SSCI, STMR, and SADC to perform the invalid instruction or invalid instruction processing.

  FIG. 5 shows an example of a logical configuration for performing the invalid instruction conversion process. The predecoder 200 decodes the four most significant bits of the instruction code by the decoder 210. The decoder 210 asserts the FPU instruction detection signal 211 to a high level when the input 4 bits are “1111” (a floating point instruction), and when the input 4 bits are “0011” (a product-sum operation instruction), Assert the product-sum operation instruction detection signal 212 to a high level. The signals 211 and 212 take a logical product (AND) with the clock control bits SFPU and SMLT, respectively, and the logical product signals 213 and 214 take a logical sum (OR). The OR signal 215 is used as a selection signal of the selector 216. The selector 216 selects an invalid instruction code 218 output from a circuit 217 that generates an instruction code of an invalid instruction (NOP) as a fixed value or an instruction code 219 to be fetched and executed by the CPU 2. When the OR signal 215 is at a high level, that is, when the clock signals of the FPU 3 and the product-sum operation unit 4 are stopped by the clock control bits SFPU and SMLT, when the FPU instruction and the MLT instruction are executed, the selector 216 The invalid instruction code 218 is selected. The instruction code selected by the selector 216 is decoded by the predecode logic 220. Thus, the FPU instruction and the MLT instruction are invalidated when the clocks of the FPU 3 and the product-sum operation unit 4 are stopped. When processing as an illegal instruction, a circuit for generating an illegal instruction code may be employed instead of the circuit 217.

  FIG. 6 illustrates signal generation logic for causing the bus state controller 6 to generate a bus error for memory protection. The bus controller 6 has an address decoder 600 capable of decoding an address signal supplied from the CPU 2 and detecting an access to the peripheral circuit SCI9, the timer 10, and the A / D converter 11. The decoding logic of the address decoder 600 is determined according to the mapping address of the peripheral circuit. A signal 601 is an access detection signal for the SCI 9, a reference numeral 602 is an access detection signal for the timer 602, and a reference numeral 603 is an access detection signal for the A / D converter 11, which is set to a high level when an access is detected. Each of the access detection signals 601, 602, and 603 is ANDed with the clock control bits SSCI, STMR, and SADC, and the OR signal for each AND signal is used as the bus error signal 24. Therefore, when the clock signals of the SCI 9, the timer 10, and the A / D converter 11 are stopped by the clock control bits SSCI, STMR, and SADC, the bus error signal 24 is executed by an instruction for accessing the peripheral circuit whose clock is stopped. Then, the bus error signal 24 is asserted. As a result, the instruction execution for accessing the peripheral circuit is interrupted, and the process branches to exception processing. As a result, data corruption in the memory is prevented.

《Dynamic release of clock stop》
FIG. 7 shows a single-chip microcomputer (referred to as a microcomputer) 1C as a second example of the data processing apparatus according to the present invention. Although not particularly limited, the microcomputer 1C shown in FIG. 1 is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. When the microcomputer 1C shown in FIG. 1 executes an instruction for operating a circuit module whose clock signal is stopped, or when an access to such a module occurs, the clock stop state of the circuit module is accordingly set. Can be dynamically released.

  The microcomputer 1C shown in FIG. 7 is different from the microcomputer 1 shown in FIG. 1 in the configuration of an instruction control unit 2C, a bus state controller 6C, and a system controller 12C. Other configurations are the same as those in FIG.

  The clock control bits SFPU, SMLT, SSCI, STMR, and SADC of the system controller 12C can be reset by clear signals CLR0 to CLR4 in addition to the bus access by the CPU 2. The clear signals CLR0 to CLR4 correspond to the clock control bits SFPU, SMLT, SSCI, STMR, and SADC, and their high level indicates reset. The clear signals CLR0 and CLR1 are generated by the instruction control unit 2C, and the clear signals CLR2 to CLR4 are generated by the bus controller 6C.

  FIG. 8 shows a configuration for dynamically releasing the clock stop state under the control of the CPU 2. The clock control bits SFPU and SMLT are also supplied to the CPU 2 for dynamically releasing the clock stop state. Accordingly, when decoding the FPU instruction, the instruction control unit 2C of the CPU 2 sets the clock control bit SFPU to the reset state with the clear signal CLR0 if the clock control bit SFPU is in the set state, and enables the FPU 3 to operate. , To start the execution of the instruction. Similarly, when decoding the multiply-accumulate operation instruction, the instruction control unit 2C of the CPU 2 sets the clock control bit SMLT to the reset state by the clear signal CLR1 to reset the multiply-accumulate operation device 4 when the clock control bit SMLT is in the set state. The operation is enabled, and thereafter, the execution operation of the instruction is started.

  FIG. 9 shows an example of a logical configuration for the CPU 2 to dynamically release the clock stop state. The predecoder 200C uses the decoder 210 to decode the four most significant bits of the instruction code. The decoder 210 asserts the FPU instruction detection signal 211 to high level when the input 4 bits are “1111” (floating point instruction), and outputs the MLT instruction detection signal 212 when it is “0011” (product-sum operation instruction). Assert high. The signals 211 and 212 are ANDed with the clock control bits SFPU and SMLT, respectively, and the AND signals are supplied to the system controller 12C as clear signals CLR0 and CLR1. The hard wired logic 201C starts the output operation of the control signal after the clock control bits SFPU and SMLT corresponding to the clear signals CLR0 and CLR1 are reset. Thus, when the clock signals of the FPU 3 and the product-sum operation unit 4 are stopped by the clock control bits SFPU and SMLT, when the FPU instruction and the MLT instruction are executed, the FPU 3 and the product-sum operation unit 4 Are released, and after the release, the FPU instruction and the MLT instruction are executed.

  FIG. 10 shows a configuration for dynamically releasing the clock stop state under the control of the bus state controller 6C. Clock control bits SSCI, STMR, and SADC are also supplied to the bus state controller 6C so that the bus state controller 6C dynamically releases the clock stop state. When the bus state controller 6C detects an access to a peripheral circuit whose operation is instructed by the clock control bits SSCI, STMR, and SADC, the bus state controller 6C releases the operation stop state of the peripheral circuit with the clear signals CLR2, CLR3, and CLR4. Then, access to the peripheral circuit is started.

  FIG. 11 shows an example of a logical configuration for dynamically releasing the clock stop state by the bus state controller 6C. The bus controller 6C has an address decoder 600 that can decode an address signal supplied from the CPU 2 and detect an access to the peripheral circuit SCI9, the timer 10, and the A / D converter 11. The decoding logic of the address decoder 600 is determined according to the mapping address of the peripheral circuit. A signal 601 is an access detection signal for the SCI 9, a reference numeral 602 is an access detection signal for the timer 602, and a reference numeral 603 is an access detection signal for the A / D converter 11, which is set to a high level when an access is detected. Each of the access detection signals 601, 602, and 603 is ANDed with the clock control bits SSCI, STMR, and SADC, and the respective AND signals are used as the clear signals CLR2, CLR3, and CLR4. Therefore, when the clock signals of the SCI 9, the timer 10, and the A / D converter 11 are stopped by the clock control bits SSCI, STMR, and SADC, a clear signal is issued when an instruction to access the peripheral circuit whose clock is stopped is executed. CLR2, CLR3, and CLR4 are asserted. The bus state controller 6C starts a bus cycle after the clock control bit corresponding to the asserted clear signal is inverted to the reset state.

  According to the microcomputer 1C of the second example, when execution of an instruction for operating a circuit module whose clock signal has been stopped or access to such a module has occurred, the clock stop state of the circuit module is activated accordingly. , And low power consumption control can be performed finely.

  Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the gist of the invention.

  For example, it is also possible to adopt a configuration of invalidating instructions (invalidating instructions) for the FPU and the product-sum operation device, and a dynamic release of the clock stop state for peripheral circuits. Further, the arithmetic unit is not limited to the FPU and the product-sum arithmetic unit, and may be any circuit that is access-controlled by the CPU.

  Further, the peripheral circuit built in the data processing device is not limited to the SCI or the timer, and can be changed as appropriate. Further, the data processing device may have a built-in memory management unit or cache memory. Further, the instruction control means is not limited to hard-wired logic, but may be a control storage format using micro instructions and further nano instructions.

  In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer, which is the field of use as the background, has been described. However, the present invention is not limited to this, and the present invention is not limited to this. The present invention can also be applied to a data processing device.

FIG. 1 is a block diagram of a microcomputer according to a first example of the present invention that implements memory protection by invalidating instructions (illegal instructions) and making bus errors. FIG. 2 is a block diagram showing an extracted configuration for memory protection by invalidating instructions (improper instructions) in the microcomputer of FIG. 1. FIG. 2 is a block diagram showing an extracted configuration for performing memory protection by generating a bus error in the microcomputer of FIG. 1. FIG. 2 is a block diagram illustrating a schematic configuration of an instruction control unit in the microcomputer of FIG. 1. FIG. 4 is a block diagram illustrating an example of a logical configuration for performing invalid instruction conversion processing. FIG. 3 is a block diagram showing an example of signal generation logic for causing a bus state controller to generate a bus error for memory protection. FIG. 10 is a block diagram of a microcomputer according to a second example of the present invention that performs dynamic cancellation of clock stop. FIG. 8 is a block diagram illustrating a configuration for dynamically releasing a clock stop state under control of a CPU in the microcomputer of FIG. 7. FIG. 8 is a block diagram showing an example of a logical configuration of a CPU for dynamically releasing a clock stop state in the microcomputer of FIG. 7; FIG. 8 is a block diagram illustrating a configuration for dynamically releasing a clock stop state under control of a bus state controller in the microcomputer of FIG. 7. FIG. 8 is a block diagram showing an example of a logical configuration of a bus state controller for dynamically releasing a clock stop state in the microcomputer of FIG. 7;

Explanation of reference numerals

1,1C microcomputer 2 CPU
2A operation unit 2B, 2C instruction control unit 3 FPU
4 Product-sum operation unit 5 Interrupt controller 6, 6C bus state controller 7 Clock generation circuit CLK0-CLK4 Clock signal 9 SCI
10 timer 11 A / D converter 12, 12C system controller 12R clock stop control register 13 internal data bus 14 internal address bus 15 peripheral address bus 16 peripheral data bus 17 external address bus 18 external data bus SFPU, SMLT, SSCI, STMR, SADC Clock control bit 20 Product-sum operation device control signal 21 FPU control signal 22 CPU operation unit control signal 23 Bus command 24 Bus error signal 25 Exception processing signal 200, 200C Predecoder 201, 201C Hardwired logic CLR0 to CLR4 Clear signal 210 Decoder 211 FPU instruction detection signal 212 Product-sum operation instruction detection signal 213 Logical product signal of SFPU and FPU instruction detection signal 214 Theory of SMLT and product-sum operation instruction detection signal Logical sum signal 215 213 and 214 OR signal 216 selector 217 invalid instruction code generation circuit 218 invalid instruction code 219 fetched instruction code 220 predecode logic 600 address decoder 601 SCI access detection signal 602 timer access detection signal 603 A / D Converter access detection signal

Claims (5)

A central processing unit for executing instructions, a first circuit coupled to the central processing unit via an internal bus, and a stop control circuit for selectively stopping operation of the first circuit; The control circuit outputs a value of a clock control register accessed by the central processing unit as a stop control signal, and the central processing unit receives a stop control signal output from the stop control circuit, When decoding a command using a circuit, if the stop control signal indicates stop, the stop control circuit releases the operation stop state of the first circuit and then starts the execution operation of the command. A data processing device comprising command control means. 2. The floating-point arithmetic unit according to claim 1, wherein the first circuit is controlled by the central processing unit executing a floating-point processing instruction, and is subjected to addressing control by the central processing unit. Data processing equipment. 2. The product-sum operation device according to claim 1, wherein the first circuit is controlled by the central processing unit executing a product-sum operation instruction, and is subjected to addressing control by the central processing unit. The data processing device according to claim 1. A central processing unit that executes instructions, a processing unit that is interfaced to the central processing unit via an internal bus and receives addressing control and operation control of the central processing unit, and a bus state controller coupled to the internal bus A peripheral circuit which is interfaced with the central processing unit and receives access control of the central processing unit; an external bus interface circuit which connects the bus state controller to the outside; and an operation of the arithmetic unit and the peripheral circuit can be selectively stopped. A stop control circuit, the stop control circuit outputs a value of a clock control register accessed by the central processing unit as a stop control signal, and the bus state controller outputs the stop output from the stop control circuit. A first stop control signal for the peripheral circuit among the control signals; When detecting access to a peripheral circuit for which operation stop is instructed by the first stop control signal, the operation stop state of the peripheral circuit is released and a bus cycle for the peripheral circuit is started. A data processing device, comprising: The central processing unit receives a second stop control signal for the arithmetic unit among the stop control signals output from the stop control circuit, and decodes a command using the arithmetic unit. When the stop control signal indicates stop, the instruction control means for canceling the operation stop state of the arithmetic unit by the stop control circuit and then starting the execution of the instruction is provided. 5. The data processing apparatus according to claim 4, wherein the data processing apparatus is provided.

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