JPH04195311A - Microcomputer - Google Patents

Abstract

PURPOSE:To outputs the control signal for an AC induction motor and a general-use pulse signal by adding a circuit which reads the contents of a comparing register out in synchronism with the operation of other comparing registers and using hardware effectively. CONSTITUTION:A coincidence signal EQi is passed through an AND gate 113, etc., and connected to the reset/set input of a D latch 119, etc. Further, coincidence signals EQ0 and EQ1 are connected to a D latch 140 through an OR gate 138. The output of the D latch 140 comes to the readout signal of a comparing register 109 through an OR gate 142 which inputs a signal RDCM4 at the other input terminal. Similarly, coincidence signals EQ2 and EQ3 are inputted to a D latch 141, whose output comes to the readout signal of the comparing register 110 through an OR gate 143 inputting a signal RDCM5 at the other input terminal. A counter bus 104 which connects respective comparing registers and a counter 112 is connected even to a multiplexer 137.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer (hereinafter referred to as "microcomputer") having a timer function that outputs a programmable waveform.

[Prior Art] The field of application of microcomputers has expanded rapidly in recent years, and microcomputers are used in many fields. Particularly recently, microcomputers are increasingly being used to control motors that move objects due to automation, automation, etc.

Motor control requires a microcomputer with hardware suitable for motor control.

In general, a microcomputer is configured as shown in FIG. Controls external devices by outputting control signals to external devices connected to the device and inputting status signals from external devices. Hardware suitable for the motor control belongs to this peripheral control circuit 3.

As motor control, a method of controlling an AC induction motor will be explained. Generally, a drive system using a PWM inverter is used as an AC induction motor drive system (OHM magazine, July 1984 issue, pages 33-36). As shown in Figure 9, the AC induction motor is driven by three-phase sine wave signals (A, B, C). However, since the microcomputer cannot output sine wave signals, the sine wave signals Assuming a carrier wave with a higher frequency than the frequency of A rectangular signal is called a PWM signal, and the high level width of the rectangular signal corresponds to the opposite value of the amplitude of the sine wave signal. When the PWM signal is input to the PWM inverter, the PWM inverter rotates the AC induction motor. let

FIG. 1O is a configuration diagram of a timer unit that outputs a PWM signal. The counter 112 counts up every time a count clock is input.

Conveyor register 105.106.107.108.
109°110, Ill is RDCMO, by the CPU (not shown) outputting the addresses of the respective conveyor registers 105 to Ill to the address bus 101 and outputting the read signal 102 or the write signal 103.
WRCMI, ・RDCM6. The WRCM6 signal is output from the read/write control circuit 147, the output of the OR gate 149 becomes "1", and the bus connection circuit +50 connects the data bus 100 and the bus 104 connecting each conveyor register 105 to II+. Therefore, the values of each conveyor register 105 to I11 are read to the data bus 100, and the data on the data bus 100 is written to each conveyor register 105 to Ill. Each conveyor register 105 to 111 normally compares the written data with a counter 112, and when the value of the counter 112 and the data written to the conveyor registers 105 to 111 match, a match signal EQO is generated. ,EQ1
．． EQ2゜EQ3. EQ4. EQ5. Outputs EQ6. - Match signals EQO and EQI, EQ2 and EQ3, and EQ4 and EQ5 form a pair, and when they occur, they reset the RS flip-flops 213, 214, and 215, respectively (the contents are “
O"), set (content is "1"), - match signal EQ6
occurs, an interrupt request signal is sent to the CPU,
Further, the counter 112 is cleared and the value is returned to the initial value "○". The counter 112 continues counting the count clock after being cleared. In addition, port latch 1 with 8-bit configuration
23 is a CP similar to each conveyor register 105 to 111.
RD generated from the read/write control circuit 147
It is accessed again by the PL and WRPL signals. The output of the RS flip-flop 213.214.215 is sent to the output port po via a multiplexer (MPX) 124.125.126 and an output buffer 128.129.130.

It is output to the outside of the microcontroller from PI and P2. Furthermore, bits 0.1.2 of the port latch 123 are input to the other input of the multiplexer 124, 125, and 126. The multiplexers 124, 125, and 126 output the contents of the port latch +23 when the separately controlled mode signal is "O", and output the contents of the RS flip-flops 213 to 215 when the mode signal is "1". make certain movements. This is because, since microcomputers are used in various application fields, it is considered that the output ports PO to P2 can somehow be used as general-purpose output ports even in application fields that do not use PWM signals. Output boat P
3, P4. P5. P6. The contents of bits 3, 4, 5, and 6.7 of port latch +23 are output from P7 via output buffers 131, 132, 133, 134, and 135, respectively. The output of the counter 112 is normally output to the bus 104, but when accessed by the CPU, the read signal 1
02. Bus connection circuit +53 by write signal 103 signal
to disconnect the counter 112 from the bus 104.

Next, a method of generating a PWM signal using the timer unit shown in FIG. 1O will be explained. Conveyor register 11.
1, write data corresponding to the time indicated by T of the A-phase PWM signal in FIG.
5. Data corresponding to times indicated by T 2 and T + are written in 106, respectively. When the mode signal is "1" and the counter 112 counts up from the clear state, and a match signal EQI is generated after time T1, R
Since the S flip-flop 213 is set, the output port PO becomes "1". Next, after 12 hours, the coincidence signal E
When QO occurs, the RS flip-flop 213 is reset, so the output port PO becomes "0". next,
A match signal EQ6 is generated after time T5, and the counter 112
is cleared, and one cycle of the PWM signal ends. CPU
writes data corresponding to the next PWM signal to the conveyor registers 105 and 106 based on the interrupt request signal generated by the occurrence of the match signal EQ6. Conveyor registers +07 and 108, conveyor register +0 similarly for B phase (output boat PI) and C phase (output boat P2) shown in FIG.
By controlling 9 and 110, a PWM signal can be output. By repeating the above control, the ninth
The A-phase, B-phase, and C-phase PWM signals shown in the figure can be generated to control an AC induction motor.

[Problems to be Solved by the Invention] Microcomputers are used in a wide variety of applications, so conventional microcomputers with a built-in timer unit as shown in Figure 10 are used in fields other than the control of AC induction motors. It is also possible. In that case, the output boat will send the mode signal “
0" and use it as a general-purpose output port. However,
Not only is it a huge waste because the circuit of the timer unit is never used, but users in application fields other than the control field of AC induction motors have to purchase a microcontroller at a price that includes circuits that are never used, making it uneconomical. It is true. In addition, the conventional microcontroller equipped with the timer unit shown in Figure 1O is difficult to use in application fields other than the control field of AC induction motors, so the application field of microcontrollers has become very narrow, and the sales volume and production volume of microcontrollers have decreased. does not increase much, the mass production effect cannot be achieved, and as a result, the unit price of conventional microcontrollers cannot be lowered.

An object of the present invention is to provide a microcomputer that can be applied to fields other than the control field of AC induction motors.

[Means to solve the problem]

The microcomputer of the present invention includes: a counter that updates its contents based on a supplied clock; a plurality of conveyor registers that compare the contents of the counter with held contents; and the contents of the conveyor register and the contents of the counter. an output signal generation circuit that generates an output signal corresponding to the conveyor register where a match has occurred when the contents of the conveyor register and the counter match, and an output signal generation circuit that reads the contents of the conveyor register when the contents of the conveyor register and the counter match and an output control circuit that selectively outputs either the contents of the conveyor register read by the readout circuit or the output signal generated from the output signal generation circuit to the outside of the microcomputer.

(Function) In general, microcomputers suitable for applications that control external equipment are required to have a so-called real-time processing function that outputs a predetermined pulse signal at a predetermined timing.

The present invention adds a circuit to a conventional microcomputer equipped with an AC induction motor control circuit to read out the contents of a conveyor register constituting the AC induction motor control circuit in synchronization with the operation of other conveyor registers. By effectively using hardware, control signals for an AC induction motor and general-purpose pulse signals can be output.

[Example] Next, an example of the present invention will be described with reference to the drawings.

Fig. 1 is a block diagram of the timer unit according to the first embodiment of the present invention, Fig. 2 is a detailed block diagram of the conveyor registers 105 to 111, and Fig. 3 is the timer unit when the counter mode signal is "O". Fig. 4 is an operation timing diagram of the timer unit when the counter mode signal is "'', and Fig. 5 is a timing diagram of the pulse train output from the output port when the counter mode signal is "1". It is.

Counter 112, conveyor register 105.106°107, 108.109.110. ! II is the counter 112, conveyor register 105, 106, 107, 108, 109, 110, .
Since it operates in the same way as Ill, the explanation will be omitted. Match signals EQO, EQ1, EQ2 . EQ3. EQ4. EQ5 is an anime game [13, 114, 115, 116, 117,
It is connected to the reset input, set input, reset input, set input, +21 reset input, set input of D latch 119, which has set and reset functions, respectively, through 118. Also, the match signals EQO and EQI
is connected to D latch +40 via OR gate 138. The output of the D latch 140 is the conveyor register +0
9 read signals.

Similarly, match signals EQ2 and EQ3 are input to D latch +41 via OR gate 139, and the output of D latch +41 becomes a read signal for conveyor register 110 via OR gate 143 whose input is the RDCM5 signal. Each conveyor register 105 to Ill and counter 1
A counter bus 104 connecting 12 is an 8-bit bus, and is also connected to multiplexer (MPX) +37. Multiplexer +37 selects the upper 4 bits of data on counter bus +04 when the output of D latch 136 is "1" and outputs it to 4-bit buffer bus 148. Furthermore, when the output of the D latch 136 is "O", the data of the lower 4 bits of the counter bus 104 is transferred to the buffer bus 1.
Output to 4B. The 0 bit, 1 bit, 2 bit, and 3 bit of the buffer bus 148 are D latches with set and reset functions, respectively! +9.120.121 and D latch 1
22 inputs. Furthermore, the match signals EQI and EQ3 are connected to the input of the D latch 136 via the OR gate 144, and when either the match signal EQI or EQ3 is "1", the output of the D latch 136 is "1". The output of 142.143 is or game [4
5, D latch +19.12 via AND gate 146
0. It is a latch clock of 121.122,
Timer mode signal is “1” and count clock is “0”
When D latch 119°120, 121. 122
writes data on buffer bus 148. Also, when the timer mode signal is "O", the AND gate 113.11
4. ■5.136.117. The output of 118 is “O”
Then, due to the coincidence signal, D latch 1]9°120.12
1 is not set or reset.

Port latch 123, multiplexer 124.125°126, output buffer 128.129.130.13
1.132°133.134. 135, read/write control circuit 147, bus connection circuit] 50, OR gate 1
49 is the port latch shown in FIG. 10] 23, multiplexer 124, 125, 126, output buffer 12
8 to 135, Read/Write Control Circuit] Since the operation is similar to that of 47, the explanation will be omitted. Also, D latch】22
performs the same operation as the other D latches 119, 120, 121.

1 bit 300 of conveyor registers 105 to +11 is
The contents of the counter bus 04 are written to the D latch 302 by the write signal W RCM n, and the output of the D latch 302 is read onto the counter bus 104 via the read buffer 301 when the read signal RDCMn is "1". Further, the output of the D latch 302 is input to the exclusive OR gate 303 together with the counter bus 04. When there is no access from the CPU, the contents of the counter 112 are output on the counter bus 104, and the exclusive OR gate 3
03 compares the output of the D latch 302 and the counter 112. When the contents of the counter ]12 match the contents of the D latch 302, the output of the exclusive OR gate 303, that is, the 1-bit match output of the conveyor registers 105 to I1 becomes "O".
The match output of each bit of 1 is input to the NOR gate 304, and all inputs, that is, conveyor registers 105 to 1
When all the bits of the counter 11 and all the bits of the counter 112 completely match, the output of the NOR gate 304 becomes "1", and when the count clock is "0", the output match signal EQn of the AND gate 306 becomes "1", and the corresponding Set or reset the D latch.

Now, the timer mode signal is “0” and the mode signal is “1”
The operation in this case will be explained using FIG. Conveyor register I11 has 58) I, conveyor register +05 has 56. , 51H is stored in the conveyor register 106. The contents of the counter 112 are incremented in synchronization with the rise of the count clock. When the content of the counter 112 reaches 51.4, a match signal EQI is output in synchronization with the rising edge of the count clock, and D latch +19 is set in synchronization with the falling edge of the subsequent counting clock, and the output becomes "L". Therefore, when the output capo) PO becomes "1", the match signal EQO is outputted when the content of the counter 112 becomes 56.4, and the D latch 119 is reset, so the output becomes "0". Then, the output port PO becomes "0".

As described above, the PWM signal is output from the output boat PO, and the AC training motor can be controlled.

Next, the timer mode signal is “1” and the mode signal is “1”.
The operation in the case of " is explained using FIGS. 4 and 5. Now, 51H is placed in the conveyor register 105, 56.
, it is assumed that FFH data is written in conveyor register III. Normally, the contents of the second counter are output to the counter bus +04. The content of the counter 112 is 51. In this case, a match signal EQO is output. Then, "1" is written into the D latch 140 at the next rise of the count clock, and "O" is written into the D latch 136 at the next rise of the count clock. Then,
OR gate 14 in the next count clock cycle
The output of 2.145.151 is "1".

Then, the counter 112 is disconnected from the counter bus 104 by the bus connection circuit +53, and at the same time the contents 25.4 of the conveyor register 109 are output to the counter bus 104. Then, 5H is output to the buffer bus 148, and when the count pulse falls and becomes "0", the output of the D latch 119.121 becomes "L" and the D latch 120.1
Since the output of 22 is “0”, the output port terminals PO, P
i, P2. P3 is “1”, “0°°,” “1”, respectively.
It becomes “0”. Next, the contents of the counter 112 are 56)I
When this happens, the match signal EQI becomes "1", so the contents of the D latch 136 become "1" in the next count clock cycle.Then, the contents of the conveyor register +09 read out onto the counter bus 104 25. Since the upper byte 2H of is output to the buffer bus 148, the D latches 119.120.121.122 and the output ports PO, P1. P2. P3 data is 0” and 1” respectively
, “0”, “0”. In addition, conveyor register 11
If A 5 H is written to EQ2.0, the match signal EQ2. E
When Q3 occurs, each data is sent to the output port PO.
~P3, and can generate output pulses as shown in FIG.

As described above, in this embodiment, a 4-bit predetermined pulse train can be generated at a predetermined timing using the data written to the conveyor registers 109 and 110, so that externally connected control equipment can be controlled in real time. I can do it.

FIG. 6 is a configuration diagram of a timer unit according to a second embodiment of the present invention, and FIG. 7 is a diagram showing the configuration of a timer unit according to a second embodiment of the present invention.
FIG. 3 is a timing diagram of a pulse train output from an output port when ".

In FIG. 6, circuits with the same numbers and names as in FIG. 1 perform the same operations. In FIG. 6, D latches 154, 140,
+41 has match signals EQO and EQI.

EQ2 is connected. Counter mode signal is “1”
, when the mode signal is “l”, the match signals EQO, EQ
When I and EQ2 occur, in synchronization with the next count clock, the conveyor register +08.109.11 respectively.
0 (7) The contents are read out to the counter hash lo4, D latch +19.120.121.122.156°157
．． 158. 159. Then, the output boats PO, PI, P2. P3. P4. P5. Multiplexers 124, 125, 126, 1 from P6 and P7, respectively.
D latch 119 via 27.160.161.152.163, +20. 121. 122,156.
157.158. 159 data are output.

Now, if 89□, 27□, and CAM are written to conveyor registers 108, 109, and 110, respectively, when the match signals EQO, EQI, and Eo2 are generated, the output ports PO,
PI, P2. P3. P4. P5.
P6゜P7 to 89. , 27□, CAM data is output, and an 8-bit pulse train having a waveform as shown in FIG. 7 can be generated.

Therefore, conveyor register 108.109.110
Since a predetermined 8-bit pulse train can be generated at a predetermined timing using the data written to the controller, externally connected control equipment can be controlled in real time.

[Effects of the Invention] As explained above, the present invention improves the control of an AC induction motor by adding a circuit that reads out the contents of a conveyor register constituting an AC induction motor control circuit in synchronization with the operation of other conveyor registers. It is now possible to output control and general-purpose pulse signals, which has the effect of providing microcontrollers with a wide range of applications6.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the timer unit according to the first embodiment of the present invention, Fig. 2 is a detailed block diagram of the conveyor registers 105 to Il+, and Fig. 3 is the timer unit when the counter mode signal is "0". Figure 4 is an operation timing diagram of the timer unit when the counter mode signal is "1", and Figure 5 is a timing diagram of the pulse train output from the output port when the counter mode signal is "L". ,
FIG. 6 is a configuration diagram of a timer unit according to a second embodiment of the present invention, and FIG.
Fig. 8 is a configuration diagram of a general microcomputer, Fig. 9 is an AC induction motor control signal and an AC induction motor control signal input to a PWM inverter. 10 is a diagram showing the configuration of a conventional timer unit. 100...Data bus, +01...Address bus, 102...Read signal, +03 ...Write signal, 105~Ill...Conveyor register, +12
...Counter, 113-118...And gate,
119~]22...D latch, 123...Port latch, 124~+27 ・”;'/L, Chibrexa (M
PX), 128 to 135... Output buffer, +36... D latch, 137... Multiplexer (MPX), 138, 13
9...Or gate, 140.141...D latch,
142-145...OR gate, +46...AND gate, +47...Read/write control circuit, +48...Buffer bus, 149...OR gate, +50...
・Transfer gate, +51...OR gate, +52...Inverter, 153...Transfer gate, +54...D latch, 155...OR gate, 156-159...D latch, 160-163... -Multiplexer (MPX).

Claims (1)

[Claims] 1. In a microcomputer, a counter whose contents are updated based on a supplied clock, a plurality of conveyor registers which compare the contents of the counter with held contents, and a plurality of conveyor registers of the conveyor register. an output signal generation circuit that generates an output signal corresponding to a conveyor register in which a match occurs when the content of the counter matches the content of the conveyor register; a readout circuit that reads the contents of a conveyor register other than the register; and a readout circuit that selectively outputs either the contents of the conveyor register read by the readout circuit or the output signal generated from the output signal generation circuit to the outside of the microcomputer. A microcomputer characterized by comprising an output control circuit for outputting data.