JPH04192842A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPH04192842A
JPH04192842A JP2321194A JP32119490A JPH04192842A JP H04192842 A JPH04192842 A JP H04192842A JP 2321194 A JP2321194 A JP 2321194A JP 32119490 A JP32119490 A JP 32119490A JP H04192842 A JPH04192842 A JP H04192842A
Authority
JP
Japan
Prior art keywords
speed
data signal
data transmission
channels
phase difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2321194A
Other languages
Japanese (ja)
Inventor
Koji Tsutsui
筒井 孝司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2321194A priority Critical patent/JPH04192842A/en
Publication of JPH04192842A publication Critical patent/JPH04192842A/en
Pending legal-status Critical Current

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To correct the delay between channels in the subsequent data transmission phase, and to execute the data transmission at a speed of an integer multiple of a speed determined to a circuit by detecting a phase difference between prescribed channels at the time of calling, and absorbing the phase difference by the buffer control. CONSTITUTION:The system is constituted of a pattern generating circuit 1, an INS network circuit, two selecting circuits 2, a phase difference deciding circuit 3, and two buffer circuits 4. In such a state, a high speed data signal of a speed of N folds of a prescribed speed is divided into N and allocated and inputted to N circuits, a delay difference in a public transmission circuit network of the data signal is absorbed, and by this absorption, N pieces of signals whose phases coincide with each other are synthesized and an output signal corresponding to the high speed data signal is obtained. In such a way, a difference the delay quantity between channels is eliminated, and the data signal of a high speed can be transmitted by using plural circuits of a low speed channel.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、INSネット回線のような回線網を利用した
データ伝送方式に関し、特に複数回線を使用した時のデ
ータ伝送方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission system using a line network such as an INS net line, and particularly to a data transmission system when using a plurality of lines.

[従来の技術] INS回線などを利用したデータ伝送方式においては、
各回線の速度は決まっており1現在ではBチャネル(6
4k b / s )の速度を持つデータ伝送を行うの
がふつうである。そして実際面では契約四線は2回線又
はそれ以上の場合が多い。−方64に以上の高い速度を
持つデータ伝送を行うためには特別の高い速度の回線も
用意されてはいるが、この回線では低速のBチャネルの
伝送はできない。従って高速のチャネルの使用頻度が低
いときは、当然のことながら不経済である。
[Conventional technology] In data transmission systems using INS lines, etc.
The speed of each line is fixed.1Currently, the speed of the B channel (6
It is common to perform data transmission with a speed of 4k b/s). In reality, the number of lines contracted is often two or more. A special high-speed line is also prepared to perform data transmission at higher speeds than the above-mentioned 64, but this line cannot transmit low-speed B channels. Therefore, when a high-speed channel is used infrequently, it is naturally uneconomical.

[発明が解決しようとする課題] このため、Bチャネル複数回線を使用している場合に、
64kXN (Nは2以上の整数)の速度を有するデー
タ信号をBチャネル分割して伝送できれば、前述の不経
済性は解決できるはずである。
[Problem to be solved by the invention] For this reason, when using multiple B channels,
If a data signal having a speed of 64kXN (N is an integer of 2 or more) can be transmitted by dividing it into B channels, the above-mentioned uneconomical problem should be solved.

しかしこのようにして構成した(NB+D)回線では、
Bチャネル単位の回線接続であるため、Bチャネル間の
遅延量が異っていて合成ができす。
However, in the (NB+D) line configured in this way,
Since the line connection is for each B channel, the amount of delay between B channels is different and can be combined.

分割伝送は不可能である。Split transmission is not possible.

従って本発明は上記のチャネル間遅延量の差異を最終的
にはなくすことにより、高速のデータ信号を低速チャネ
ルの複数回線を用いて伝送する方式を提供しようとする
ものである。  ′[課題を解決するための手段] 本発明によれば、データ信号を所定の速度のチャネルで
公共共通回線網を介して伝送する方式であって、少なく
とも2つ(以下Nで表す)の回線が使用可能な場合に於
けるデータ伝送方式において、前記所定の速度のN倍の
速度の高速データ信号をN分割して前記N回線に割当て
入力し、前記データ信号の前記公共回線網に於ける遅延
差を吸収し、この吸収により位相の一致したN個の信号
を合成して前記高速データ信号に対応する出力信号を得
るようにしたことを特徴とするデータ伝送方式が得られ
る。
Therefore, the present invention aims to provide a system for transmitting high-speed data signals using a plurality of low-speed channels by ultimately eliminating the above-mentioned difference in the amount of delay between channels. [Means for Solving the Problems] According to the present invention, there is provided a system for transmitting data signals via a public common line network using a channel at a predetermined speed, the method comprising at least two lines (hereinafter referred to as N). In a data transmission method when a high-speed data signal having a speed N times the predetermined speed is divided into N parts and allocated to the N lines, the data signal is transmitted to the public line network. A data transmission system is obtained in which a delay difference is absorbed, and N signals having the same phase are synthesized by this absorption to obtain an output signal corresponding to the high-speed data signal.

また本発明によれば、データ信号を所定の速度のチャネ
ルで公共共通回線を介して伝送する方式であって、N回
線が使用可能な場合に於けるデータ伝送方式において、
前記データ信号を発信する側に、パタン列を発生するパ
タン発生回路と、前記N回線に設けられ1発呼時に前記
パタン列を同時に選択し、その後に続く動作時に前記デ
〜り信号を選択して出力するN個の選択回路とを備え。
Further, according to the present invention, in a data transmission method in which a data signal is transmitted via a public common line using a channel at a predetermined speed, when N lines can be used,
On the side that transmits the data signal, there is provided a pattern generation circuit that generates a pattern sequence, and a pattern generation circuit that is provided on the N line and that simultaneously selects the pattern sequence when one call is made and selects the de-signal during subsequent operations. and N selection circuits for output.

前記データ信号を受信する側に、前記N個の選択回路か
ら出力されたパタン列を入力し、該パタン列相互の位相
差を検出し、検出した位相差から後に続く前記N個のデ
ータ信号の遅延差を決定する位相差判定回路と、該決定
された遅延差を回線毎に吸収するバッファ回路とを備え
た事を特徴とするデータ伝送方式が得られる。
The pattern strings output from the N selection circuits are input to the data signal receiving side, the phase differences between the pattern strings are detected, and the subsequent N data signals are determined based on the detected phase difference. A data transmission system is obtained that is characterized by comprising a phase difference determination circuit that determines a delay difference, and a buffer circuit that absorbs the determined delay difference for each line.

なお前記パタン列の周期を前記公共回線網の最大遅延時
間の少なくとも2倍にすることは効果的である。
Note that it is effective to make the period of the pattern sequence at least twice the maximum delay time of the public line network.

し実施例] 次に本発明について図面を参照して説明する。Examples] Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の構成をあられす図である。FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

パタン発生回路1はINSネット回線の最大遅延時間の
少なくとも2倍の周期を有するパタン列を発生し、この
パタン列は発呼回線接続時に2つの選択回路2により出
力信号として選択される。
A pattern generation circuit 1 generates a pattern sequence having a period at least twice the maximum delay time of the INS net line, and this pattern sequence is selected as an output signal by two selection circuits 2 when a calling line is connected.

この第1図の方式は2つのBチャネルを使用して128
 k b / sのデータ信号を伝送する場合であり、
前述のパタン列は2つのBチャネルに送出される。
This scheme in Figure 1 uses two B channels to
When transmitting a data signal of k b / s,
The aforementioned pattern sequence is sent out on two B channels.

一方相手局では、対をなす位相差判定回路3により2つ
のBチャネルから受信時にパタン列を入力とし、そのパ
タン列の位相差からBチャネル間の遅延差ΔTを決定す
る。
On the other hand, at the partner station, the paired phase difference determination circuit 3 inputs the pattern sequence from the two B channels when receiving, and determines the delay difference ΔT between the B channels from the phase difference between the pattern sequences.

第2図は上記の動作の一例を示す図でr B I +B
2は2つのBチャネルを示し、Tはパタン列P1〜P、
の周期をあられし、ΔT(”BI   B2)は両Bチ
ャネルの遅延差をあられしている。INS回線の最大遅
延時間をT。とすると、さきに述べたように、B、−8
2すなわちΔTはなる関係を有している。このΔTの極
性によってB、、B2チャネルの位相差が分る。この例
ではB1が82より61分遅延している。
Figure 2 is a diagram showing an example of the above operation.
2 indicates two B channels, T indicates pattern rows P1 to P,
, and ΔT("BI B2) is the delay difference between both B channels. If the maximum delay time of the INS line is T, then as mentioned earlier, B, -8
2, that is, ΔT has the following relationship. The phase difference between the B and B2 channels can be determined by the polarity of this ΔT. In this example, B1 is delayed by 61 minutes from 82.

このようにして対の位相差判定回路3で得られた結果は
対のバッファ回路4に入力され、ここでBチャネル間の
遅延差が吸収される。したがって対の出力の位相差はB
チャネル間で一致する。
The results thus obtained by the pair of phase difference determination circuits 3 are input to the pair of buffer circuits 4, where the delay difference between the B channels is absorbed. Therefore, the phase difference between the outputs of the pair is B
Match across channels.

なお以上の説明はBチャネルを2本使用した場合につい
て説明し・たが、チャネル数を2でなく更に数多く (
−殻内には2以上のN)してもよい。
Note that the above explanation is based on the case where two B channels are used, but if the number of channels is not 2 but many more (
- Two or more N) may be present in the shell.

また6 4 k b / sの速度のチャネルを用いた
が。
Although a channel with a speed of 64 kb/s was also used.

他の速度のチャネルを用いてもよい。Channels of other speeds may also be used.

[発明の効果コ 以上説明したように2本発明は発呼時に例えばBチャネ
ル間の位相差を検出し、バッファ制御により位相差を吸
収させることにより、その後のデータ伝送フェーズにお
いてBチャネル間の遅延補正が可能となり1回線にきめ
られた速度の整数倍の速度のデータ伝送が実現できる。
[Effects of the Invention] As explained above, the present invention detects, for example, the phase difference between B channels at the time of calling, and absorbs the phase difference by buffer control, thereby reducing the delay between B channels in the subsequent data transmission phase. Correction becomes possible, and data transmission at a speed that is an integral multiple of the speed determined for one line can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のデータ伝送方式の一実施例の構成を示
す図、第2図はその動作を説明するための図である。 記号の説明=1・・・パタン発生回路、2・・選択回路
、3・・・位相差判定回路、4・・バッファ回路。
FIG. 1 is a diagram showing the configuration of an embodiment of the data transmission system of the present invention, and FIG. 2 is a diagram for explaining its operation. Explanation of symbols = 1...Pattern generation circuit, 2...Selection circuit, 3...Phase difference determination circuit, 4...Buffer circuit.

Claims (3)

【特許請求の範囲】[Claims] (1)データ信号を所定の速度のチャネルで公共共通回
線網を介して伝送する方式であって、少なくとも2つ(
以下Nで表す)の回線が使用可能な場合に於けるデータ
伝送方式において、 前記所定の速度のN倍の速度の高速データ信号をN分割
して前記N回線に割当て入力し、前記データ信号の前記
公共回線網に於ける遅延差を吸収し、この吸収により位
相の一致したN個の信号を合成して前記高速データ信号
に対応する出力信号を得るようにしたことを特徴とする
データ伝送方式。
(1) A method of transmitting data signals via a public common line network using channels at a predetermined speed, the method comprising at least two (
In a data transmission method when a line (hereinafter referred to as N) is available, a high-speed data signal with a speed N times the predetermined speed is divided into N parts and allocated to the N lines, and the data signal is A data transmission system characterized in that a delay difference in the public line network is absorbed, and N signals having the same phase are synthesized by this absorption to obtain an output signal corresponding to the high-speed data signal. .
(2)データ信号を所定の速度のチャネルで公共共通回
線を介して伝送する方式であって、N回線が使用可能な
場合に於けるデータ伝送方式において、 前記データ信号を発信する側に、パタン列を発生するパ
タン発生回路と、前記N回線に設けられ、発呼時に前記
パタン列を同時に選択し、その後に続く動作時に前記デ
ータ信号を選択して出力するN個の選択回路とを備え、 前記データ信号を受信する側に、前記N個の選択回路か
ら出力されたパタン列を入力し、該パタン列相互の位相
差を検出し、検出した位相差により後に続く前記N個の
データ信号の遅延差を決定する位相差判定回路と、該決
定された遅延差を回線毎に吸収するバッファ回路とを備
えた事を特徴とするデータ伝送方式。
(2) In a data transmission method in which a data signal is transmitted via a public common line using a channel at a predetermined speed, and when N lines can be used, the side transmitting the data signal has a pattern. a pattern generation circuit that generates a sequence, and N selection circuits that are provided on the N lines and simultaneously select the pattern sequence when a call is made, and select and output the data signal during a subsequent operation; The pattern strings output from the N selection circuits are input to the data signal receiving side, the phase difference between the pattern strings is detected, and the detected phase difference is used to select the following N data signals. A data transmission system comprising: a phase difference determination circuit that determines a delay difference; and a buffer circuit that absorbs the determined delay difference for each line.
(3)請求項第(2)項のデータ伝送方式において、前
記パタン列の周期を前記公共回線網の最大遅延時間の少
なくとも2倍にしたことを特徴とするデータ伝送方式。
(3) The data transmission system according to claim (2), wherein the period of the pattern sequence is at least twice the maximum delay time of the public line network.
JP2321194A 1990-11-27 1990-11-27 Data transmission system Pending JPH04192842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2321194A JPH04192842A (en) 1990-11-27 1990-11-27 Data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2321194A JPH04192842A (en) 1990-11-27 1990-11-27 Data transmission system

Publications (1)

Publication Number Publication Date
JPH04192842A true JPH04192842A (en) 1992-07-13

Family

ID=18129843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2321194A Pending JPH04192842A (en) 1990-11-27 1990-11-27 Data transmission system

Country Status (1)

Country Link
JP (1) JPH04192842A (en)

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