JPS58184851A - Hdlc receiver - Google Patents

Abstract

PURPOSE:To control an HDLC line in a high speed by a CPU in a slow processing speed, by providing two sets of high level data link control (HDLC) reception sections, and switching data and flag pattern inputs alternately. CONSTITUTION:The HDLC reception section is provided with the 1st and the 2nd HDLC reception sections 2, 2A, to each of which a switch circuit 7 is connected. A flag pattern generating circuit 5 is connected to the circuit 7 and an external data line 1 and a detection circuit 6 detecting the frame from the line 1 are connected. A memory 3 storing the data inputted to the sections 2, 2A, and a CPU4 managing the procedure of the HDLC and preparing the reception of the sections 2, 2A are connected to the reception sections 2, 2A. The input data from the line 1 and the flag pattern from the circuit 5 are switched at the circuit 7 alternately and stored in the memory 3, the CPU4 in a slow processing speed is used to process the data of the line 1 in a large speed.

Description

[Detailed description of the invention] H for receiving rolls (hereinafter abbreviated as HDLC)
The present invention relates to a DLC receiving device.

Conventionally, this type of receiving device has an HDLC receiving section, which is a controller for HDLC reception on an external data line, and stores data input from the data line via the HDLC receiving section, as will be explained in detail later. memory to
A central processing unit (hereinafter abbreviated as CPU) that manages HDLC procedures and sets reception preparations for the HDLC receiving unit.
It consists of However, in such a configuration, as will be explained later, when the HDLC data line speed is high, a high-speed CPU must be used, and therefore it is not very desirable from a cost standpoint. Ta.

Therefore, an object of the present invention is to provide an HDLC data line that can use a CPU with a slow processing speed even if the speed of the HDLC data line is high.
I'm trying to get a DLC receiver.

In order to achieve the above object, the present invention provides two sets of HDLC receivers, and while one of the HDLC receivers is inputting data, the other HDLC receiver inputs a flag pattern and receives the flag pattern. The flags are switched alternately each time one frame is received, so that the CPU can be set to prepare for reception slowly until the last flag of the next frame of data is input. be.

That is, according to the present invention, H
A controller for DLC reception) - IDLC reception section, which transmits data input from the data line to the HD
In the receiving device, the H
A flag pattern generation circuit that includes first and second HDLC reception sections as DLC reception sections, further includes a flag pattern generation circuit that generates a flag pattern in HDLC, and a frame detection circuit that detects an HDLC format frame input from the data circuit; 1. Each time the detection is performed, the output of the data line and the output of the flag pattern generation circuit are individually transmitted to the first HD.
There is obtained an HDLC receiving device characterized in that it is provided with a switch circuit for alternately connecting the input of the LC receiving section and the ≠ power of the second HDLC receiving section.

Next, a detailed explanation will be given with reference to the drawings.

FIG. 1 is a diagram showing the basic data format in HDLC. In the figure, the number in parentheses 0 indicates the number of bits, where n is an integer greater than or equal to 1, and the flag is 0111111.
It is a fixed pattern of 0.

FIG. 2 is a block diagram showing the configuration of a conventional HDLC receiver. The HDLC receiver shown in Fig. 2 is
Data input line 1, which is an external data line; HDLC receiving section 2, which is a controller for HDLC reception (C
2. A memory for storing input data (including an interface section with the PU); and a CPU 4 that controls the HDLC receiving section 2 and manages the HDLC control procedure, and the CPU 4 sends the 9th order data frame to the HDLC receiving section 2 every time it receives one data frame from the data input line 1. Before the first data character (8 bits) of the next data frame is input for reception,
Settings were being made to prepare for reception. Therefore, as a CPU, there is a drawback that a high-speed CPU is recommended because the time required for the CPU to prepare for reception is shorter than the interval between one character and one character of the signal inputted from the data input line.

FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 3, the same reference numerals as in FIG. 2 indicate the same components as in FIG. This HDLC receiver shown in FIG.

Data input line 1, HDLC receiver reception memory 3,
In addition to the CPU 4, there is another HDLC receiver 2A and a flag node in the HDLC. A 7-lag noise generation circuit 5 for generating a turn, and a data input line 1
A frame detection circuit 6 that detects HDLC format frames input from ! : Each time a frame in HDLC format is detected, the inputs of the two HDLC receivers 2 and 2A are individually connected to the data input line 1 and the flag signal.
It has a switch circuit 7 which is alternately connected to the output of the turn generating circuit 5.

The data input line 1 is now connected to the HDLC receiving section 2.

It is assumed that seven lag signal generation circuits 5 are connected to the HDLC receiving section 2A. When a data frame like the one shown in FIG. 1 is input from the data input line 1 in such a state, the frame detection circuit 6 detects the flag that follows the data, A flag pattern generation circuit 5 is provided in the HDLC receiving section 2.
Switch and connect the data input lines to the two HDLC receivers. As a result, the HDLC receiving section 2 connected to the data input line 1 before switching is switched to the flag pattern generation circuit 5 after switching.
Input fragno or turn from the output of . Here the CPU
4, settings are made to the HDLC reception section 2 to prepare for reception.

This setting can be performed while the flag pattern is being input to the HDLC receiving section 2.

The reception preparation setting for the HDLC receiving section 2 of the CI'U 4 can be performed within a relatively long period of time until the last flag of the next data frame is input. That is, C
Even if the PU 4 is not a high-speed one, it is possible to set reception preparation for the HDLC receiving section 2.

The following describes an example in which the HDLC receiver 2 is connected to the data input line 1 in the initial state, but the situation is exactly the same when the HDLC receiver 2A is connected to the data input line 1. It is. According to the present invention,
HD with high speed 11y even when using a slow processing speed CPU
The LCl line can be controlled.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic data format in HDLC, FIG. 2 is a block diagram showing the configuration of a conventional HDLC receiver, and FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention. be. Explanation of symbols: 1 is the data line, 2 is the (first) (DLC
2A is a (second) HDLC receiver, 3 is a memory, 4 is a central processing unit (CPU), 5 is a flag pattern generation circuit, 6 is a frame detection circuit, and 7 is a switch circuit. .

Claims (1)

[Claims] 1. An HDLC receiving unit that is a controller for HDLC reception on an external data line, a memory that stores data input from the data line via the HDLC receiving unit, and an HDLC procedure management and the HDLC
In a receiving device having a central processing unit that performs reception preparation settings of a C receiving section, two HDLC receiving sections, a first and a second HDLC receiving section are provided as the HDLC receiving section, and
a flag pattern generation circuit that generates a flag mother turn; a frame detection circuit that detects an HDLC format frame input from the data circuit; and a frame detection circuit that detects an HDLC format frame input from the data circuit; An HDLC receiving device characterized in that it is provided with a switch circuit for alternately connecting the input and the tidal force of the second HDLC receiving section.