JPH04192331A - Forming method of wiring - Google Patents

Abstract

PURPOSE:To prevent the increase of contact resistance, by forming a plurality of series type silicide wiring layers mutually connecting impurity-doped regions of different conductivity type, by a wiring formation processing conducted for a plurality of times, so as to come into contact with each other while mutually interposing grain boundaries. CONSTITUTION:Silicide is deposited on an insulative film 16 so as to cover a first silicide wiring layer 18A and a contact hole 16B. By patterning, a second wiring region 18B which comes into ohmic contact with an impurity-doped region 14 and comes into contact with the first silicide wiring layer 18A via a grain boundary GB is formed. After that, the first and the second silicide wiring layers 18A, 18B are subjected to heat treatment. Since silicide grains form a discontinuous surface on the grain boundary GB, P-type or N-type impurities sucked up from an impurity-doped region 12 or 14 are prevented from diffusing by the grain boundary GB. Thereby low contact resistance can be obtained in the contact part of the impurity-doped region 12 or 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for forming silicide interconnects used in semiconductor devices such as LSIs.

[Summary of the Invention] The present invention provides a method for connecting a plurality of series silicide wiring layers interconnecting, for example, P+ type and N'' type impurity doped regions to each other through a grain boundary by a plurality of wiring formation processes. By forming the conductivity type impurity in the subsequent heat treatment step, the diffusion of the conductivity type determining impurity through the silicide layer P1. is prevented at the grain boundary, and a decrease in the impurity concentration at the contact portion of each impurity doped region is suppressed. This is what I did.

[Prior Art] Conventionally, a method illustrated in FIG. 6 has been proposed as a method for forming silicide wiring interconnecting impurity-doped regions of different conductivity types.

That is, the P+ type and N'v type impurity doped regions 12
．． 14 and an insulating film 16 having contact holes corresponding to these regions 12 and 14, respectively, is prepared.

After depositing silicide on the upper surface of the substrate by sputtering or the like, this deposited layer is patterned to form a region 12.1.
A single silicide wiring layer 18 is formed to interconnect the 4 interconnections.

[Problems to be Solved by the Invention] According to the conventional method described above, after forming the silicide wiring layer 18, if heat treatment is performed at, for example, 900 to 1000° C. in order to lower the resistance of the wiring layer 18, the result will be as shown by the broken line arrow. As shown, the P type impurity in the P1 type impurity doped region 12 diffuses into the N type impurity doped region 14 via the silicide wiring layer 18, and the N type determined impurity in this region 14 diffuses into the region 14 via the silicide wiring N18. Spread to 12. Then, the impurity concentration in the contact portion of region 12 is lowered by the diffused N-type determining impurity, and
The impurity concentration of No. 4 is lowered by the diffused P-type determining impurity.

Therefore, the conventional method has the disadvantage that contact resistance increases due to a decrease in impurity concentration in the contact portion.

- An object of the present invention is to provide a novel wiring formation method that can avoid an increase in contact resistance.

[Means for Solving the Problems] The wiring forming method according to the present invention includes: (a) a semiconductor substrate on which first and second impurity-doped regions having different conductivity types are formed; first and second impurity doped regions respectively;
and (b) preparing an insulating film having a second contact hole formed so as to cover the surface; (b) replacing the first and second impurity doped regions with the first
and (c) forming a plurality of series silicide wiring layers interconnected via a second contact hole so as to be in contact with each other via a grain boundary through a plurality of wiring formation processes; This process includes a step of performing heat treatment to lower the resistance of the wiring layer.

[Operation] According to the method of the present invention, a plurality of series silicide wiring layers are formed so as to be in contact with each other through the grain boundaries, so that impurities sucked up from each impurity doped region during heat treatment are absorbed at the grain boundaries. The spread is prevented. Therefore, in the contact part of each impurity doped region,
A decrease in impurity concentration due to diffused impurities from other impurity doped regions does not occur, and an increase in contact resistance can be avoided.

[Example 1] Figures 1 to 4 show a wiring forming method according to an embodiment of the present invention, and the steps (1) to (4) corresponding to each figure are
) will be explained in order.

(1) First, as a semiconductor substrate 10 made of silicon,
A P1 type impurity doped region 12 and an N" type impurity doped region 14 are formed on the surface, and these regions 12.
An insulating film 16 having contact holes 16A and 16B corresponding to the contact holes 16A and 14B is formed so as to cover the surface thereof. The impurity doped region 12 or 14 is formed by selective ion implantation using a photoresist as a mask, for example. In this case, after removing the photoresist layer as a mask, the insulating film 16 is formed by oxidizing the substrate surface or depositing an insulating material on the upper surface of the substrate by CVD or the like.

Contact holes 16A and 16B corresponding to impurity doped regions 12 and 14, respectively, are then formed using a well-known photolithography technique.

(2) Next, silicide is deposited on the insulating film 16 by sputtering or the like to cover the contact holes 16A and 16B. Then, the first silicide interconnection layer 1 is formed into ohmic contact with the impurity doped region 12 by patterning the silicide deposited layer by a well-known photolithography process.
Form 8A. In this case, the contact hole 16B may be covered with a suitable mask material during silicide deposition, and the mask material may be removed when or after etching the silicide.

(3) Next, silicide is deposited and patterned on the insulating film 16 to cover the first silicide wiring layer 18A and the contact hole 1.6B, thereby making ohmic contact with the impurity doped region 14 and making contact with the impurity doped region 14. The second silicide wiring layer 18A contacts the first silicide wiring layer 18A through the grain boundary GB.
A silicide wiring layer 18B is formed.

(4) After this, the first and second silicide wiring layers 18A
For example, 900 to 10 to lower the resistance of 18B.
Heat treatment is performed at 00°C. As shown in the enlarged view of part P of grain boundary (B) in the upper right of FIG. 4, at grain boundary GB, silicide grains form a discontinuous surface. The P-type or N-type determining impurity sucked up from the grain boundary GB is prevented from diffusing.Therefore, the P-type and N-type determining impurities are not introduced into the impurity doped regions 14 and 12, respectively. The amount of impurities sucked up from the region 14 or 12 is also smaller than in the case of FIG. 6 due to the diffusion inhibiting property.

Therefore, in the contact portion of the impurity doped region 12 or 14, the impurity concentration decreases only slightly, and a low contact resistance can be obtained.

FIG. 5 shows another embodiment of the present invention, in which the same parts as in FIG. 4 are given the same reference numerals and detailed explanations are omitted.

The feature of the embodiment shown in FIG. 5 is that the first silicide wiring layer 18
After forming the second silicide wiring layer 18B in ohmic contact with the impurity doped region 14 by reusing the process for forming A, the first and second wiring layers are formed by a second wiring formation process in the same manner as described in FIG. A third silicide wiring layer 18C is formed to interconnect the silicide wiring layers 18A and 18B. In this case, there is a grain boundary G between the first and third silicide wiring layers 18A and 18C.
B1 is the second and third silicide wiring layer 188'E
Grain boundaries GB occur between L and 18C, respectively. Since the grain boundaries GBI and GB2 prevent impurity diffusion from the regions 12 and 14 during the heat treatment after interconnection formation, the effect of reducing contact resistance can be obtained as in the case of FIG. 4.

[Effects of the Invention] As described above, according to the present invention, a plurality of serial silicide wiring layers interconnecting impurity-doped regions of different conductivity types are formed so as to form grain boundaries with each other by multiple wiring formation IA processes. Since the grain boundary prevents the conductivity type determining impurity from diffusing through the silicide wiring layer in the subsequent heat treatment process, the impurity concentration at the contact portion of each impurity doped region is This has the effect of suppressing the decrease and realizing wiring with low contact resistance.

[Brief explanation of the drawing]

1 to 4 are cross-sectional views of a substrate showing a wiring forming method according to one embodiment of the present invention, FIG. 5 is a cross-sectional view of a substrate showing another embodiment, and FIG. 6 is a conventional wiring forming method. FIG. 2 is a cross-sectional view of a substrate for explaining an example. DESCRIPTION OF SYMBOLS 10... Semiconductor substrate, 12.14... Impurity doped region, 16... Insulating film, 16A, 16B... Contact hole, 18.18A-18C... Silicide wiring layer. Applicant Yamaha Co., Ltd. Company Agent Patent Attorney Akisa Izawa Figure 1 (Contsuku) 7L type precept) Figure 2 (Wiring formation) Figure 3 (6 Sei formation) Figure 4 (Hakarimasu) )

Claims (1)

[Scope of Claims] (a) A semiconductor substrate in which first and second impurity-doped regions having different conductivity types are formed on the surface thereof, each corresponding to the first and second impurity-doped regions, respectively. The first
and (b) preparing an insulating film having a second contact hole formed so as to cover the surface; (b) replacing the first and second impurity doped regions with the first
and (c) forming a plurality of series silicide wiring layers interconnected via a second contact hole so as to be in contact with each other via a grain boundary through a plurality of wiring formation processes; A wiring forming method including a step of performing heat treatment to lower the resistance of the wiring layer.