JPH04191679A - Integrated circuit - Google Patents

Abstract

PURPOSE:To dispense with a substrate for evaluating a margin by providing preceding and succeeding interface margin adjusting means evaluating the interface between preceding and succeeding apparatuses in an integrated circuit. CONSTITUTION:Test data is outputted from a data investigation means 500 to be inputted to a preceding interface margin adjusting means 300 having delay wire groups having various delay quantities. Next, the respective wire groups of the adjusting means 300 are successively selected and the data signals passed through the delay wire groups are inputted to a logic part 200. Subsequently, the output of the logic part 200 is inputted to a succeeding interface margin adjusting means 400 having delay wire groups having various delay quantities and outputted through the successively selected delay wires. This output is inputted to an output data investigating part 502 and the interface margin of the whole of an integrated circuit is evaluated and the delay wire developing the optimum margin is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit used in switching equipment, electronic computers, etc., and particularly relates to an integrated circuit incorporating a circuit for evaluating an interface margin therein.

[Prior Art] Generally, in integrated circuits such as ICs and LSIs that are constructed by combining many circuit elements on one substrate to form a logic section, the circuit itself is In addition to performing a functional evaluation to evaluate the functionality of the circuit, we also evaluate the interface margin (difference in data exchange timing) between this and other systems connected to it to ensure proper circuit operation. being done. For example, when evaluating the interface margin between an integrated circuit such as an LSI and a preceding or subsequent device connected to it, a dedicated LSI test jig or actual board may be used.
Measurements were performed by connecting an oscilloscope, logic analyzer, etc. to this.

Then, calculate the margin in advance, incorporate this value into the test jig or actual board, and adjust it on the board.
Margin evaluations were performed while checking signals using connected oscilloscopes and logic analyzers.

[Problems to be Solved by the Invention] However, as described above, the conventional interface margin evaluation method has the following problems.

(1) One evaluation board per LSI, including circuits for margin evaluation and function test circuits between an LSI as an integrated circuit and the preceding or succeeding devices connected to it. It was required separately.

(2) In the case of a signal line with a tight margin between the LSI and the previous or subsequent stage equipment, it is necessary to insert a separate delay line on the above board to provide time margin, which is a complicated adjustment. It was needed.

(3) Even if the above delay line is installed and tied into the system, it is difficult to judge whether or not the input is correct as it was when it was implemented for the device connected to the output. there were.

The present invention has focused on the above-mentioned problems and has been devised to effectively solve the problems. An object of the present invention is to provide a circuit that can evaluate the interface margin between the logic section of an integrated circuit and the preceding and succeeding devices to be connected thereto and set the optimum margin (optimal timing for data exchange). The purpose of the present invention is to provide an integrated circuit that is integrated into an integrated circuit.

[Means for Solving the Problems] In order to solve the above problems, the present invention is applied to an integrated circuit formed by combining many circuit elements to form a logic section.

In such an integrated circuit, a pre-stage interface margin adjustment means is provided on the input side of the logic section and adjusts the timing of data exchange between the logic section and a pre-stage device to be connected thereto; post-interface margin adjustment means provided on the output side of the logic section for adjusting the timing of data exchange between the logic section and a subsequent-stage device to be connected thereto; and test data being sent to the pre-stage interface adjustment means. and data consideration means for examining the timing of data exchange in the logic section based on the output signal output from the latter-stage interface margin adjustment means, and transmitting the test data from the expected value detection means to the previous-stage interface. In addition to the margin adjustment means, the interface margin of the integrated circuit itself is evaluated by examining the output from the last stage.

[Operations] According to the present invention, since the integrated circuit is configured as described above, test data is outputted from the data consideration means and inputted to the front-stage interface margin adjustment means. This adjustment means has delay line groups having various delay amounts, and each delay line group is selected in sequence. The data signal that has passed through the selected delay line group is input to the logic section which is the main body of the integrated circuit, and the output from there is input to the subsequent interface margin adjustment means. This adjusting means has a delay line group having a plurality of types of delay amounts, similar to the above-mentioned front-stage interface margin adjusting means, and sequentially introduces the output from the logic section into each selected delay line and outputs it. This output is introduced into an output data review section where the data is reviewed to evaluate the interface margin of the entire integrated circuit.

Then, a delay line that provides the optimum margin is selected.

[Embodiment] A preferred embodiment of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a schematic configuration diagram showing an integrated circuit of the present invention, and FIG. 2 is a detailed diagram of the integrated circuit shown in FIG. 1.

As shown in the figure, this integrated circuit includes a logic section 200 that combines many circuit elements on one substrate and essentially performs various arithmetic processing, etc., and a pre-stage interface margin provided on the input side of this logic section 200. adjustment means 300, rear-stage interface margin adjustment means 400 provided on the output side of the logic section 200, each of the above means 300,
400 and a data consideration means 500 that inputs test data to the logic section 200 and evaluates the interface margin based on the output signal. Built into an integrated circuit.

The data examination means is composed of a data generation section 501 that generates test data and an output data examination section 502 that specifically checks the waiting value.

Specifically, the above-mentioned front-stage interface margin adjustment means 300 is a front-stage device (not shown) to be connected thereto.
This is for adjusting the timing (interface margin) of data transfer between the logic unit 200 and the logic unit 200, and in the illustrated example, two delay line groups 105 and 106 are used.
Each delay line group 105.106 has a plurality of delay lines 105, 105N, 106. ~106N.

Note that the number of delay line groups 105 and 106 is the same as that of the logic section 200.
This corresponds to the number of 0 Å force terminals, and it goes without saying that it is not limited to two.

Each delay line 105 . of the delay line group 105 . The input sides of ~105N are connected to the outputs of the selectors 103°~103N of the selector group 103, respectively, and the delay line group 106
The input sides of each of the delay lines 1061 to 106N are connected to the outputs of the selectors 1041 to 104N of the selector group 104, respectively. And each selector 1031 to 103
A common input terminal 1 and a common signal line 20 for inputting test data supplied from the data generating section 501 are connected to the input side of the N.

Further, the input side of each of the selectors 1041 to 104N is connected to a common input terminal 3 and a common signal line 21 for inputting test data different from the above test data. And each selector 103 of each selector group 103.104
．． ~103N-1041~104 FJ selects the input terminal 1.3 signal and signal line 2 by the selection signal supplied to terminal 4.
0.21 signal can be selected alternatively. Each signal line 20.21 is connected to a buffer 100.
101 and a common F/F circuit 102 to the data generating section 501 of the data examining means 500.

These buffers 100 and 101 each have the same delay amount as the sum of the delay amount between the output buffer of the preceding stage device and the large-power buffer of the integrated circuit. This F/F
The circuit 102 can be regarded as an F/F circuit at the output end of the previous stage device, and exhibits a similar function.

Each delay line 1051 to 10 of the delay line group 105 is
All the outputs of 5N are input to the selector 107, and the outputs thereof are input to the logic section 200. Furthermore, all the outputs of the delay lines 106 to 106N of the delay line group 106 are input to the selector 108, and the outputs thereof are similarly input to the logic section 200. Each selector 107.108
each selects an input signal by a selection signal applied to terminal 2.5.

The front-stage interface margin adjustment means 300 is configured as described above.

On the other hand, the latter-stage interface margin circuit 400
It has two delay line groups 109.110 similar to those described above, and each of these delay line groups 109.110 has a plurality of delay lines 109.110 so as to hold a plurality of types of delay amounts including zero delay.
~109N, 1101~11ON. The delay amount of each of these delay line groups 109 and 110 is calculated from the output of the final stage F/F circuit of this integrated circuit to the first stage F/F circuit of the subsequent stage device.
The minimum value of the delay amount to the F circuit (Minimum direct),
Standard value (Typical value), maximum value (Max
i mum value) is determined by calculation, and the value between these is determined by appropriately dividing into a plurality of values, and a plurality of delay lines corresponding to each delay amount are provided.

Each delay line 109 . of the delay line group 109 . The input sides of the delay lines 1091 to 109N are commonly connected to the output signal line 30 of the logic section 200, and the output sides of the delay lines 1091 to 109N are all input to the selector 112. Also, each delay line 110 . of the other delay line group 110 . The input side of ~11ON is also commonly connected to the other output signal line 31 of the logic section 200, and each of the delay lines 110
The output sides of 1 to 11ON are all input to the other selector 113.

Each of the selectors 112 and 113 is connected to the input terminal 10.
The delay line groups 109 and 110 selectively output signals having different delay amounts inputted from the delay line groups 109 and 110, depending on the selection signals supplied thereto. The outputs from each selector 112 and 113 are connected to output terminals 50 and 52, respectively, for output to the next stage device, and at the same time, these outputs are sent to the output data consideration section 502 for checking the output data. It is also man-powered.

Specifically, one of the outputs from the selector 112 is input to the exclusive OR circuit 114 that constitutes a part of the output data consideration section 502, and is connected here to the signal line 510 from the data generation section 501. An exclusive OR is taken. On the other hand, one of the outputs from the selector 113 is sent to the other exclusive OR circuit 1 which similarly constitutes a part of the output data consideration section 502.
15, where exclusive OR is performed with the other signal line 511 from the data generating section 501.

The outputs from the exclusive OR circuits 114 and 115 are respectively input to buffers 119 and 120 having a predetermined amount of delay, and the outputs are respectively input to F/F circuits 116 and 111.
7 is input. And each F/F circuit 116.117
The output from the OR circuit 118 is inputted to an OR circuit 118 to perform a logical sum.The output of the OR circuit 118 is connected to the output terminal 51, and the interface margin is checked by this output.

Here, the buffers 119 and 120 each have a delay amount equal to the sum of the delay amount between the output buffer of this integrated circuit and the input buffer of the next stage device.

In addition, clocks are input to the clock systems of the F/F circuits 116 and 117 from the clock terminal 6 via delay lines 111 corresponding to the clock buffer delay amount of the next-stage device. F circuit 116.1
17 can be regarded as the first stage F/F circuit of the next stage or subsequent stage device. This allows signals with different delay amounts from the delay line group to pass through the F/F circuits 116 and 117, which can be regarded as the first stage of the next stage device, thereby making it possible to accurately evaluate the interface margin. can.

The data generation circuit 501 has input terminals 7, 8 and 9 for inputting drive signals thereto, and by applying a signal thereto, the F/F circuit 102 of the front-stage interface margin adjustment means 300 Test data will be sent to the

Next, the operation of the above embodiment will be explained.

First, the case of evaluating interface merging will be explained.

First, by accessing the input terminals 7.8.9 of the data generation section 5010, this generation section outputs test data as logic manual data to the F/F circuit 102. The test data output from this F/F circuit 102 passes through a buffer 100 or 101, respectively, and passes through a selector group 1.
03 or 104, each selector 1031-103N or 1041-104. It is input to J. Each selector group 1
03.104, the signal line from the input terminal 1.3 is selected by the selection signal from the terminal 4, and the selected signal is connected to the delay line 105, each having a different amount of delay.
1 to 105N or 1061 to 106N and are all introduced into selector 107 or 108. In these selectors 107 and 108, signals having various delay amounts are sequentially selected and outputted by a selection signal from terminal 2 or a selection signal from terminal 5, and are inputted to logic section 200.

Each signal that passes through this logic section 200 and is output is
The selector group 109 or 11 of the subsequent interface margin adjustment means 400 via signal lines 30 and 31, respectively.
delay lines 109.0 and each having a different amount of delay. ~109N or 1101~11ON. All of the signals given different delay amounts are input to the selector 112 or 113, and are sequentially selected and output by the selection signal from the terminal 10.

The output signal from each selector 112 or 113 is output to the output terminal 50 or 52, respectively, and at the same time, the exclusive OR circuit 11 of the output data consideration section 502
4 or 115 as well. In this circuit 114, the output signal from the selector 112 and the signal line 510 from the data generation circuit 501 are compared and exclusive ORed, and the result is sent to the F/F circuit 116 via the buffer 119. will be introduced to

On the other hand, in the exclusive OR circuit 115, selector 1
13 output signal and other signal line 5 of data generation circuit 501
11 are compared and their exclusive OR is taken, and the result is introduced into the F/F circuit 117 via the buffer 120. The output signals from each F/F circuit 116 and 117 indicate the deviated state of the data exchange timing, and these signals are input to the OR circuit 118 and logically summed. It is output and the interface margin is evaluated. Here, the exclusive OR circuit 114 or 115 outputs "H" when the inputs to be compared do not match, and outputs "L+1" when they match.

Furthermore, the clock input to the previous F/F circuits 116 and 117 is passed through delay line 1 corresponding to the clock buffer delay of the next stage.
11, each F/F circuit 116.117
can be regarded as the first stage F/F circuit of the next stage device.

Therefore, by sequentially changing the delay amount of the output signal from the selector 112.113 connected to the delay line group 109.110 and inputting this signal to the F/F circuit 116.117, the interface can be configured as before. Margins can be evaluated.

Next, normal operation will be explained.

During this normal operation, the selector groups 103 and 104 of the front-stage interface margin adjustment means 300 are set to select only the signal from the input terminal 1 or 3. Further, in the delay line groups 105 and 106, settings are made so that the delay line that gave the optimum delay amount in the previous interface margin evaluation is selected. Further, the subsequent interface margin adjustment means 400
Similarly, the delay line groups 109 and 110 are set so that the delay line that gave the optimum delay amount in the previous interface margin evaluation is selected. Thereby, the signal input to the input terminal 1.3 during normal operation is output from the output terminals 5o and 52 after being processed with an optimal interface margin.

[Effects of the Invention] In summary, according to the present invention, inside the integrated circuit itself,
Since we have provided a front-stage interface margin adjustment means and a rear-stage interface margin adjustment means for evaluating the interface margin between the front-stage device or the rear-stage device, it is possible to not only satisfy the interface with peripheral devices, but also improve the interface margin that was previously required. This eliminates the need to separately provide a board for margin evaluation.

Even if there is a tight margin between the front and rear devices, it is possible to select a delay line with the corresponding amount of delay, which eliminates the need to insert a delay line on the board, which was previously required. operations can be eliminated.

Since the amount of delay can be accurately selected by adjusting the front-stage interface margin adjustment means and the rear-stage interface margin adjustment means, it is possible to input a signal with an optimal margin to the rear-stage device at the time of mounting.

Even when integrating integrated circuits of the same quality into circuits on different substrates, it is possible to easily adjust appropriate interface margins for each circuit.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an integrated circuit according to the present invention, and FIG.
The figure is a detailed diagram of the circuit shown in FIG. 1. 102.116.117...Flip-flop circuit,
200...Logic section, 300...Previous stage interface margin adjustment means, 400...Later stage interface margin adjustment means, 500...Data consideration means, 5
01...Data generation section, 502...Output data consideration section.

Claims (2)

[Claims] (1) In an integrated circuit formed by combining many circuit elements to form a logic section, an integrated circuit is provided on the input side of the logic section to transfer data between the logic section and a preceding device to be connected to it. a front-stage interface margin adjustment means for adjusting the timing of transmission and reception; and a rear-stage interface margin adjustment means provided on the output side of the logic section for adjusting the timing of transmission and reception of data between the logic section and a rear-stage device to be connected thereto. an interface margin adjustment means; and a data consideration means for inputting test data into the first-stage interface adjustment means and examining timing of transmitting and receiving data in the logic section based on an output signal output from the second-stage interface margin adjustment means. An integrated circuit characterized by: (2) The integrated circuit according to claim 1, wherein the first-stage and second-stage interface margin adjustment means each include a group of delay lines each having a plurality of selectable delay amounts.