JPS6088370A - Logical circuit - Google Patents

Abstract

PURPOSE:To make it possible to perform the functional test of a complicated circuit within a short time, by providing an exclusive logical sum circuit wherein signals at plural points in a logical part are imparted as one input and the output of the previous stage is applied to the other input. CONSTITUTION:The level of the control signal SIG inputted to an initial stage EX-OR circuit 34 is changed, for example, from zero to 1 and, if there is no trouble in the connection of EX-OR circuits 34-36 at this time, the level change in the control signal SIG is transmitted to the output signal from the circuit 36. If it is cleared that there is not trouble in the signal routes of the circuits 34-36, a predetermined pattern is inputted to a logical part 21 from an input terminal 22. By comparing the output signal from an output terminal 23 with an expected value at this time, the functional test of the logical part 21 is performed. At the same time, by comparing the output signal of the circuit 36 with an expected value, signal tests at circuit points 25, 27, 29 in the logical part 21 can be performed. By this mechanism, a functional test can be performed even with respect to a circuit having a complicated circuit constitution within a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a logic circuit that facilitates internal function testing.

[Technical background of the invention and its problems]

When performing a functional test on a logic circuit having a predetermined logic function, conventionally, for example, a logic circuit 10 as shown in FIG.
A test) is inputted from a plurality of input terminals 11 of
This is done by comparing the output from the device with an expected value prepared in advance. However, according to this conventional method, the internal configuration of the logic circuit is complicated.
This causes the inconvenience that the test takes a long time.

Furthermore, a sequential circuit among logic circuits can be expressed as a combination of a plurality of registers 13 and a combinational circuit 14 made up of various gate circuits, etc., as shown in FIG. Tests are conventionally conducted in the following manner. That is, this method is generally called the scan/guss method, etc.
In response to the switching signal SW, the shift registers 13 are configured such that the contents of the previous stage are input to those of the subsequent stage, and during a functional test, a transfer pulse φ is applied to these registers 13 in parallel. The contents of each register 13 are sequentially taken out as the register output of the final stage, and this value is observed. According to this method, the number of input tests and mother turns is reduced compared to the one in Fig. 1. However, the observable values are limited to the contents of the register 13.

Therefore, if the number of turrj points is increased, it is necessary to add an extra register 13. However, since the register 13 has a higher proportion of component elements than a general glue circuit, there is a disadvantage that the scale of the entire circuit becomes larger.Furthermore, according to method C, the resistor 13 As the number of data increases, the time it takes to extract these contents to the outside becomes longer, resulting in an inconvenience that the test time becomes longer.

[Purpose of the invention]

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to improve the circuit structure of Shino's functionalized circuit structure, which is complex and has a single circuit configuration. It is an object of the present invention to provide a logic circuit whose function test can be performed in a short time.

[Summary of the invention]

The logic circuit according to the present invention guides a signal at an arbitrary circuit point in a logic section having a predetermined logic function to each of a plurality of signals rN, and further provides υ exclusive OR circuits separately from the logic section. Exclusive OR circuits are connected in multiple stages such that the output of the previous stage is used as one input of the latter stage, and each signal of the plurality of signal lines is provided as the other input, and a control signal is supplied as one input of the first stage. When a test)/4 turn is input to the logic section, the output of the final stage of the plurality of exclusive OR circuits connected in multiple stages is observed.

Furthermore, the logic circuit according to the present invention is capable of controlling the output of each signal when guiding a signal at an arbitrary circuit point to the plurality of signal lines, so that only the signal at an arbitrary one circuit point can be output from the exclusive OR of the final stage. I am trying to output it from the circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a circuit diagram showing the configuration of an embodiment of the logic circuit according to the present invention. In the figure, 2 is a logic section which is composed of each rM'f-) circuit, register, etc. and has a predetermined logic function, 22 is an input terminal for supplying the tlC input to this logic section 21, and 23 is this logic section. This is an output terminal to which a signal from the section 21 is output. Further, a plurality of arbitrary circuit points in the logic section 21, that is, circuit points whose signals need to be observed, for example, AND'y' as shown in the figure.
-to z4tD output point 25, OR dart 26 output point 27
The output point 29 of the inverter 28 is connected to signal lines 31, 32, and 33 that carry the signals of the respective circuit points.

Furthermore, in addition to the logic section 2, there is also one signal line 31, 32.
Three exclusive OR circuits (hereinafter referred to as EX
-OR circuits) 34, 35° 36 are provided. As shown in the figure, the three EX-OR circuits 34, 35, and 36 have the output of the previous stage given as one input of the latter stage, and the three signal lines 31,
The circuits are connected in multiple stages so that 32.degree. and 33. signals are applied thereto, and a control signal SIG is inputted as one input of the first stage EX-(IR circuit 34).

A functional test of a logic circuit having such a configuration is performed as follows. First, prior to the functional test of the logic section 2), the l::X-0R circuit 34, , ? 5.

It is tested whether or not a failure has occurred in the signal path consisting of 36. This test is performed by changing the level of the control signal SIG input to the first-stage EX-OR circuit 34- from, for example, 0 to 1. At this time, the EX-OR circuit 34, ,?5
, ,? If there is no failure in the wiring connecting the two EX-OR circuits 34, 35, and 36 themselves, the change in the level of the control signal S■G is transmitted to the output signal from the EX-OR circuit 36 at the final stage. Ru. Therefore, if the output signal from this EX-OR circuit 36 is observed, EX
- It can be determined whether a failure has occurred in the signal path consisting of the OR circuits 34, 35, and 36.

EX-OR circuits 34, 35, 36 according to the above test
If it is determined that no failure has occurred in the signal path consisting of the following, a predetermined test pattern is inputted to the logic section 2 from the input terminal 22. At this time, the function of the logic section 2 is tested by comparing the output signal from the output terminal 23 with an expected value. Furthermore, at the same time, the final stage EX-
By multiplying the output signal of the OR circuit 36 by one stage from the expected value, the signals at circuit points 25, 27.degree. 29 inside the logic section 2 can be tested. (This is a certain test) When a turn is input, if logic section 2 is normal, the signals at each circuit point 25, 27, and 29 are uniquely determined, and the output of the EX-011 circuit 36 at the final stage is determined. There is also one signal”, “o
In this case, the fljIJ control signal SIG is set to either level 111'' or @Q.Here, if the above circuit points 25° and 26 .27, if one signal is opposite to the normal level, this signal is passed to the EX-OR of the final stage.
When the signal is propagated to the circuit 36, the output signal of the EX-OR circuit 36 becomes a value different from the expected value.

Therefore, by measuring the output signal of this EX-OR circuit 36, it is also possible to determine the function m1 of the logic section 2. It should be noted that the test numbers and turns inputted from the input terminal 22 are such that they can predict and detect failures occurring in the logic section 21 in advance.

By the way, when performing a functional test of the logic section 21, the kl il! ! The greater the number of signals that can be input, the more the number of test pattern inputs can be reduced.

In the above embodiment circuit, not only the signal from the output terminal 23 but also the signal at the internal circuit point can be observed, and this circuit point can be set at a point where it is difficult to detect a failure from the outside. The number of inputs for test numbers and turns can be significantly reduced compared to conventional methods. Therefore, a functional test can be performed in a short time even on a logic circuit which is highly functional and has a complicated circuit +4 configuration.

On the other hand, compared to the conventional scan path method, the scan path method can only observe the contents of internal registers, and if the number of registers is small, the number of signals that can be observed decreases. On the other hand, in the above embodiment, any number of circuit points can be used as required. Moreover, these signals can be taken out to the outside in a short time via the lThX-0R circuit. Therefore, the test time can be significantly shortened compared to the scan path method.

FIG. 4 is a circuit diagram showing the configuration of another embodiment of the logic circuit according to the present invention. In the example circuit shown in Figure @3 above,
If the signal at an odd numbered circuit point among the three circuit points 25, 27 and 29 differs from the normal level, this can be determined as a failure. However, if the signals at an even number of circuit points simultaneously reach levels different from their normal levels, this cannot be determined to be a failure. Therefore, the embodiment circuit of FIG. 3 is effective if implemented in a logic circuit in which the occurrence of failures is relatively low. On the other hand, in the circuit shown in FIG. 4, even if the signals at even numbered circuit points simultaneously differ from their normal levels, this can be determined as a failure. In FIG. 4, parts corresponding to those in FIG. 3 are designated by the same reference numerals and will be explained. In this example circuit, the circuit points 2.5, 27, 29
The signal line 31.32,? ,? In this case, it is necessary to connect it directly. At each circuit point 2. 5, 2 7, 2
9 AND) I"-to 41.42° Connect each one of the incoming ends of 43 to the heel of these A, NO darts 41.42.
The output ends of 43 are connected to signal lines 31, 32 and 33, respectively. Furthermore, the above AND dirt 4, 4
Each of the other input terminals of 2.43 is connected to one of the three outputs f of the decoder 5 provided at the new/ζ.

For example, when a 2-bit signal is input to this decoder 51KFi, one of the three output terminals is set to f"l" and the rest are set to 0" according to the level state of this 2-bit signal. ing.

According to such a configuration, a signal set to 1'' among the three output terminals of the decoder 51 is inputted to the tail 3-11).
One of the three circuit points 26, 27, 29 outputs one signal to one of the signal lines 31, 32, ?2. By changing the settings of the input signals to the EX-OR circuit 36, the signals at all circuit points 25°27.29 (F: Even if circuit point No. 48 at the same time differs from the normal level, this can be determined as a failure.

In the case of this embodiment, the test time is slightly longer than that in Fig. 3 because it is necessary to change the input signal settings of the decoder 51 and sequentially extract the signals at circuit points 25, 27, and 29 to the outside. However, it is extremely effective for logic circuits with a high probability of failure.

In the above embodiment, the signals at circuit points 25, 27, and 29 are independently output depending on the output of the 7'' coder 5), so that the EX-OR circuits 34, 35°, ? It is also possible to use a simple OR dart as the substitute force for 6. By using this OR dart, the number of constituent elements can be reduced compared to when using an EX-OR circuit, and it is extremely effective when there are many circuit points that need to be observed within the logic section 21. becomes.

It goes without saying that the present invention is not limited to the embodiment 11 described above, and that multiple modifications can be made. For example, the case where there are three circuit points for signal viewing 11+17 in the logic section 21 has been explained, but it is only necessary to provide as many circuit points as necessary. The number should also increase. Therefore, M
The decoder 5 in Figure 4 is also not limited to the one with the two-person car 3 output.

〔Effect of the invention〕

As explained above, according to the present invention, a predetermined logic machine h
1 and 1 of any circuit point in the logic section having
! Directly to each signal line of the concubine or selectively lead, also V・
614 'It! The I logical sum circuit is connected to the δ stage J7 in such a way that the output of the previous stage is given as one input of the latter stage, and each signal of the above-mentioned repulsive signal line is given as the input of the counter, and one of the first stages is manually operated. -C1lIII is also 1t
Give l signal 2 and manually test and turn the logic section /C
This is intended to provide a general lesson on how to output the last stage of the plurality of multi-stage connected logic circuits 41. Therefore, it is possible to provide a logic circuit that can perform a functional test in a short time even when the circuit configuration is complicated due to the high 1<μ function.

[Brief explanation of drawings]

11g and 2 are circuit diagrams for explaining the functions of conventional logic circuits, FIG. 3 is a circuit diagram showing a configuration according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of another embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration according to an embodiment. 21...Logic section, 22...Input terminal, 23...Output Pl'At child, 25, 27.29...Circuit point 1.11' in logic section, 32.33...Signal line 1. ? 4
,35, ,? 6=...1Jli transitive disjunctive sum M(
EX-on circuit), 41, 42゜43...ANI)
r~t, 51...decoder.

Claims (1)

[Claims] il+ A logic section having a predetermined logic function, a plurality of signal lines for guiding signals at arbitrary circuit points within this logic section, and a %+1Lil signal being given as one input of the first stage, and an output of the previous stage. 1. A logic circuit comprising: a plurality of exclusive OR circuits connected in multiple stages such that one input of the plurality of signal lines is given as one input of the latter stage, and each signal of the plurality of signal lines is given as the other input. (2) A logic section having a predetermined logic function, a means for receiving signals from a plurality of arbitrary circuit points in this logic section and controlling the output of each input signal to each of the plurality of signal lines, and one input of the first stage. 1. A logic circuit having multiple axes so that one side network signal is applied, the output of the previous stage is applied as one input of the latter stage, and each signal of the plurality of signal lines is applied as the other input. (3) The logic circuit according to claim 2, wherein the OR type r-) circuit is an exclusive OR circuit. (4) The logic circuit according to claim 2, wherein the logical sum f-) circuit is an OR r-) circuit.