JPH04188723A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04188723A JPH04188723A JP31755690A JP31755690A JPH04188723A JP H04188723 A JPH04188723 A JP H04188723A JP 31755690 A JP31755690 A JP 31755690A JP 31755690 A JP31755690 A JP 31755690A JP H04188723 A JPH04188723 A JP H04188723A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductive layer
- contact hole
- insulating film
- laser beam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000001678 irradiating effect Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 9
- 239000004411 aluminium Substances 0.000 abstract 1
- 239000002356 single layer Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野]
本発明は半導体装置の導電層間のコンタクト形成方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming contacts between conductive layers of a semiconductor device.
[従来の技術]
従来技術においては、半導体基板上の第1の導電層上に
設けられた絶縁膜上にコンタクトホールを形成後、層構
成が少なくとも一層以上である第2の導電層を形成する
方法が一般的であった。[Conventional technology] In the conventional technology, after forming a contact hole on an insulating film provided on a first conductive layer on a semiconductor substrate, a second conductive layer having a layer structure of at least one layer is formed. The method was common.
[発明が解決しようとする課題]
しかしながら前述の従来技術においては、微細加工技術
の進展とともにコンタクトホールのサイズがサブミクロ
ンと極端に小さくなってきた場合、コシタクト抵蹴が増
大し、かつ大きなばらつきを持つ。そこで本発明はこの
ような問題点を解決するもので、その目的とするところ
はコンタクト抵抗値とそのばらつきを低減させることに
ある。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, when the size of contact holes becomes extremely small to sub-micron size with the progress of microfabrication technology, the resistance to tact increases and large variations occur. have The present invention is intended to solve these problems, and its purpose is to reduce the contact resistance value and its variation.
[11題を解決するための手段]
本発明の半導体装置は、半導体基板上の第1の導電層上
に設けられた絶縁膜にコンタクトホールを形成後、レー
ザー光を照射してアニール処理し、しかる後に層構成が
少なくとも一層以上である第2の導電層を形成すること
を特徴とする。[Means for Solving Problem 11] A semiconductor device of the present invention includes forming a contact hole in an insulating film provided on a first conductive layer on a semiconductor substrate, and then performing an annealing treatment by irradiating laser light. After that, a second conductive layer having a layer structure of at least one layer is formed.
[実施例]
以下本発明について実施例に基づき説明する。第1図は
本発明の実施例を工程順に示す断面図である。第1図(
a)において1はシリコン基板、2は第1の導電層であ
る不純物拡散層、3は絶縁膜であり、4は絶縁膜に開口
したコンタクトホールであり、5はアニール処理のため
照射したエキシマレーザ−光である。第1図(b)は1
例としてエキシマレーザ−光によりアニール処理を実施
した後、層構成が少なくとも一層以上である第2の導電
層として、6に示す1%シリコンを含有するアルミニウ
ムをスッパッタリング法にて堆積後、バターニングした
ものである。第2図は従来技術と本実施例によるコンタ
クト抵抗の測定結果をヒストグラムに示したものである
。これらはコンタクトサイズ1ミクロン角のコンタクト
抵抗をケルビン法にて測定した結果であり、第1の導電
層はN型拡散層、また第2の導電層は1%シリコンを含
有するアルミニウムである。第2図(a)は従来技術に
よるコンタクト抵抗の測定結果、また第2図(b)は本
実施例によるコンタクト抵抗の測定結果である。第2図
から、明かのように、本発明によればコンタクト抵抗の
平均値とばらつきを大幅に低減することが可能となる。[Examples] The present invention will be described below based on Examples. FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps. Figure 1 (
In a), 1 is a silicon substrate, 2 is an impurity diffusion layer which is the first conductive layer, 3 is an insulating film, 4 is a contact hole opened in the insulating film, and 5 is an excimer laser irradiated for annealing treatment. -It is light. Figure 1(b) is 1
For example, after performing annealing treatment with excimer laser light, as a second conductive layer having a layer structure of at least one layer, aluminum containing 1% silicon as shown in 6 is deposited by a sputtering method, and then This is the one that has been edited. FIG. 2 is a histogram showing the measurement results of contact resistance according to the prior art and this embodiment. These are the results of measuring contact resistance with a contact size of 1 micron square using the Kelvin method, and the first conductive layer is an N-type diffusion layer, and the second conductive layer is aluminum containing 1% silicon. FIG. 2(a) shows the measurement results of contact resistance according to the conventional technique, and FIG. 2(b) shows the measurement results of contact resistance according to the present embodiment. As is clear from FIG. 2, according to the present invention, it is possible to significantly reduce the average value and variation in contact resistance.
ところで本実施例においては、第1の導電層としてシリ
コン基板上の不純物拡散層を例として用いたが、これは
多結晶シリコン、またはチタン、タングステン、モリブ
デン等のポリサイドまたはシリサイド、またはチタン、
タングステン、モリブデン等の高融点金属においてもま
ったく同様に適用可能である。By the way, in this embodiment, an impurity diffusion layer on a silicon substrate is used as an example of the first conductive layer.
It can be applied in exactly the same way to high melting point metals such as tungsten and molybdenum.
また層構成が少なくとも一層以上である第2の導電層と
して、1%シリコンを含有するアルミニウムを例として
説明したが、これは多結晶シリコン、またはチタン、タ
ングステン、モリブデン等のポリサイドまたはシリサイ
ド、またはチタン、タングステン、モリブデン等の高融
点金属、または銅やパラジウムを含むアルミニウム、ま
たはチタン、チタンナイトライド、チタンタングステン
等の高融点金属並びにその化合物等とアルミニウム並び
にアルミニウム合金との積層配線においてもまったく同
様に適用可能である。In addition, aluminum containing 1% silicon has been described as an example of the second conductive layer having a layer structure of at least one layer. The same applies to laminated wiring of high melting point metals such as tungsten and molybdenum, or aluminum containing copper and palladium, or high melting point metals such as titanium, titanium nitride, and titanium tungsten, and their compounds, and aluminum and aluminum alloys. Applicable.
[発明の効果]
以上述べてきたように本発明によれば、コンタクトホー
ル形成後、レーザー光を照射することによりアニール処
理を実施し、コンタクト抵抗の低減とばらつきの減少が
可能となる[Effects of the Invention] As described above, according to the present invention, after the contact hole is formed, an annealing process is performed by irradiating the contact hole with laser light, thereby making it possible to reduce contact resistance and variation.
第1図は本発明の実施例を工程順に示す断面図であり、
第2図は従来技術と本実施例によるコンタクト抵抗の測
定結果を示すヒストグラムである。
1 シリコン基板
2 不純物拡散層
3 絶縁膜
4 コンタクトホール
5 レーザー光
61%シリコンを含有するアルミニウム以上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴木喜三部(他1名)第1図(b)FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps;
FIG. 2 is a histogram showing the measurement results of contact resistance according to the prior art and this embodiment. 1 Silicon substrate 2 Impurity diffusion layer 3 Insulating film 4 Contact hole 5 Laser light Aluminum containing 61% silicon or more Applicant Seiko Epson Corporation Representative Patent attorney Kizobe Suzuki (and 1 other person) Figure 1 (b)
Claims (1)
ンタクトホールを形成後、レーザー光を照射してアニー
ル処理し、しかる後に層構成が少なくとも一層以上であ
る第2の導電層を形成することを特徴とする半導体装置
の製造方法。After forming a contact hole in an insulating film provided on a first conductive layer on a semiconductor substrate, an annealing treatment is performed by irradiating a laser beam, and then a second conductive layer having a layer structure of at least one layer is formed. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31755690A JPH04188723A (en) | 1990-11-21 | 1990-11-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31755690A JPH04188723A (en) | 1990-11-21 | 1990-11-21 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04188723A true JPH04188723A (en) | 1992-07-07 |
Family
ID=18089576
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31755690A Pending JPH04188723A (en) | 1990-11-21 | 1990-11-21 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04188723A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7554055B2 (en) | 2005-05-03 | 2009-06-30 | Hitachi Global Storage Technologies Netherlands B.V. | Method for making ohmic contact to silicon structures with low thermal loads |
-
1990
- 1990-11-21 JP JP31755690A patent/JPH04188723A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7554055B2 (en) | 2005-05-03 | 2009-06-30 | Hitachi Global Storage Technologies Netherlands B.V. | Method for making ohmic contact to silicon structures with low thermal loads |
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