JPH04186926A - Clock generating device - Google Patents

Abstract

PURPOSE:To constitute this device so that the synchronization can be taken at a high speed by allowing it to coincide with a rough frequency by digital control, thereafter, executing the fine adjustment of the frequency coincidence with an analog PLL operation. CONSTITUTION:A reference voltage generator 18 outputs a voltage [V/2] of a half of a control voltage range [V] of a VCO 22 with a frequency band variable function. A VCO setting device 21 sets a band of the VCO 22 with a frequency band variable function to a center band. Consequently, the VCO 22 with a frequency band variable function operates as an oscillator for fixing a frequency. The VCO setting device 21 sets a switch 17 to the side of an LPF 14. After this time, this device executes the same PLL operation as a conventional clock generating device. In such a manner, the fine adjustment of an output frequency is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock generation device used in digital equipment, and more particularly to a clock generation device for multiplying a reference frequency by N.

Conventional technology FIG. 3 shows the configuration of a conventional clock generator.

In FIG. 3, 1 is an input terminal to which a reference signal is input, and is connected to a phase comparator 3. The output end of the phase comparator 3 is connected to the input end of the LPF 4, and the output end of the LPF 4 is connected to the input end of the VCO 6. VCO6
The output terminal of is connected to the output terminal 7 and the 1/N frequency divider 80 input terminal. The pressure of the l/N frequency divider 8 is determined by the phase comparator 3.
is connected to the control input terminal of the

Next, the operation of the above conventional example will be explained.

In FIG. 3, in the initial state, the VCO 6 is free-running oscillating. This output signal is frequency-divided by a 1/N frequency divider 8 and input as a control signal to a phase comparator 3, and the phase comparator 3 outputs a voltage proportional to the phase difference between the control signal and the reference signal. This voltage value includes a frequency component of the reference signal in addition to the DC component, and the LPF 4 removes this component to extract only the DC component. This DC voltage is input to VC○6, which operates so that the frequency-divided signal and the reference signal are in the same phase.

In this way, even the conventional clock generation device described above can generate a carrier wave signal that is N times the reference signal.

Problems to be Solved by the Invention However, in the above-mentioned conventional tarok generator, the vC
When converting O6 into an integrated circuit (LSI), there is a large frequency drift due to fluctuations in power supply voltage and ambient temperature, etc.
It was necessary to widen the frequency variable range as shown by the control voltage V with respect to the output frequency f in the figure. In this case, LPF4
A high S/N ratio characteristic of DC output is required. For this reason, L
The cutoff frequency of PF4 becomes lower. As a result, there is a problem in that the clock generation device takes a long time to acquire synchronization, making it impossible to achieve high-speed synchronization.

The present invention solves these conventional problems,
The purpose of this invention is to provide an excellent tarock generator capable of high-speed synchronization.

Means for Solving the Problems In order to achieve the above object, the present invention provides a VC with a frequency band variable function that can vary the amount of frequency offset in a plurality of stages.
When controlling O, the frequency offset amount is changed to roughly match the frequencies using digital control means,
Thereafter, an analog control means is provided for performing fine adjustment for frequency matching using an analog PLL operation.

Effects The present invention has the following effects due to the above structure. That is, when controlling C○ with the frequency band variable function, first, by digital control, the frequency offset is moved to the optimum stage, that is, the frequency is made to match the approximate frequency. After this, fine adjustment of frequency matching is further performed by analog PLL operation.

Therefore, the time required to obtain synchronization by analog PLL operation can be significantly shortened, and synchronization can be achieved at high speed even when the time required for digital control is taken into account.

Example FIG. 1 shows the configuration of an embodiment of the present invention.

In FIG. 1, 10 is an input terminal to which a reference signal is supplied, and is connected to a timer 11 and a phase comparator 12. Phase comparator 12 is connected to LPF 14. A 1/N frequency divider 5 and a counter I6 are connected to the phase comparator 12, and a switch 17 connected to the LPF 14 has a
Furthermore, a reference voltage generator 18 and a vCo setting device 21 are connected. The VC○ setting device 21 is a V with frequency band variable function.
Connected to CO22.

This VCO 22 with variable frequency band function can change the frequency offset in n stages as shown in Fig. 2. In this case, the frequency variable range at each stage is equal to that of the conventional VCO.
It is narrow compared to O. V with variable frequency band function
CO22 is connected to the output terminal 24 and the 1/N frequency divider 15. The 1/N frequency divider 15 is connected to the phase comparator 12 and the counter 16. Timer 11 is connected to counter 16. Counter 16 is connected to VCO setter 21.

Next, the operation of the above embodiment will be explained.

In FIG. 1, first, the output frequency is roughly adjusted by digital control.

The reference voltage generator 18 is a VCO 22 with variable frequency band function.
outputs a voltage CV/2) that is half of the control voltage range (V). The VCO setter 21 first selects the switch 17 to the reference voltage generator 18 side.

In addition, the vCO setting device 21 is a VC with a variable frequency band function.
Set the O22 band to the center band. As a result, the frequency band variable function-equipped vC○22 operates as a fixed frequency oscillator.

The output of the frequency band variable VCO 22 is frequency-divided by a 1/N frequency divider 15 and counted by a counter 16. The period during which the counter 16 counts is determined by the timer 11. The timer 11 determines the period for which the counter I6 counts based on the reference signal input to the input terminal 10. Based on the count result of the counter 16, the VCO setter 21 detects the difference between the input frequency and the output frequency, and selects the VCO with variable frequency band function in the band where the frequency difference is the smallest.
Perform CO22 settings.

As described above, the output frequency is roughly adjusted by digital control.

Next, fine adjustment of frequency matching is performed by analog PLL operation.

The VCO setter 21 sets the switch 17 to the LPF 14 side. From this point on, a PLL operation similar to that of a conventional clock generator is performed. Through the above steps, the output frequency is finely adjusted. Even when this analog PLL operation is being performed, the timer 11 and counter 16 continue to operate, and when the count value exceeds a certain range, the vCO setting device 21 detects that it is out of the band and adds the frequency band variable function. VCO
Reset the band of 22. This makes it possible to generate a signal that is N times the reference signal.

In this way, according to the above embodiment, the optimal band of the VCO setter 21 or the frequency band variable VCO 22 is set, so that the VCO can be used with less sensitivity than the conventional vCo. Therefore, in order to obtain the same loop gain as the conventional type, it is possible to use an LPF 14 with a high cut-off frequency and small attenuation, so the synchronization acquisition time can be shortened.
It is possible to synchronize at high speed. And furthermore, L, C
All circuits except LPF l4, which is a lumped constant, or CMO
3, making it suitable for LSI implementation. Since the cutoff frequency of the LPF 14 can be increased, it becomes easier to incorporate the LPF 14 into an LSI, and the circuit configuration becomes easier.

Effects of the Invention As is clear from the above embodiments, when controlling a vCO with a frequency band variable function, the present invention first matches the approximate frequency by digital control, and then matches the frequency by analog PLL operation. Since the fine adjustment is made, it is possible to significantly shorten the time required to obtain synchronization using an analog PLL operation, and there is an advantage that synchronization can be achieved at high speed even when the time required for digital control is taken into account.

Furthermore, since all the circuits other than the LPF can be constructed of CMO3, it has the advantage of being suitable for LSI implementation. Also, L
Since the cut-off frequency of the PF can also be made high, it becomes easier to incorporate the LPF into an LSI, which also has the effect of simplifying the configuration.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a clock generation device according to an embodiment of the clock generation device of the present invention, and FIG. 2 is a characteristic diagram of the output frequency and control voltage of the vCO with a variable frequency band function in the embodiment shown in FIG. 1. , FIG. 3 is a block diagram showing the configuration of a conventional clock generator, and FIG. 4 is a characteristic diagram of the output frequency and control voltage of the VCO shown in FIG. 3. 10...Input terminal, 11...Timer, 12...Phase comparator, 14...LPF, 15...1/N frequency divider, 16...Counter, 17...Switcher , 18...
Reference voltage generator, 21... vCO setting device, 22...
vCO124 with variable frequency band function...output terminal. Fil+”= Isthmus plexus fusuma vein 1g2 diagram gendou vein fusuma

Claims (1)

[Claims] A VCO with a variable frequency band function that can vary the amount of frequency offset in a plurality of stages, and a VCO with a variable frequency band function that changes the amount of frequency offset to roughly match the frequencies when controlling the VCO with the variable frequency band function. A clock generation device comprising: digital control means that performs digital control; and analog control means that performs fine adjustment for frequency matching by analog PLL operation after changing the frequency offset amount.