JP4647199B2 - PLL circuit - Google Patents

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit.

In recent years, the operation speed of LSIs has been increased, and accordingly, PLL circuits are often incorporated in LSIs. For clock generation of the PLL circuit, a CMOS transistor ring oscillator is used, and the frequency is adjusted by controlling the current value.
This type of PLL circuit is disclosed in Patent Document 1 and Patent Document 2 to be described later. As shown in FIG. 7, the charge pump 2 performs charge / discharge based on the phase difference signal from the phase comparison circuit 1. The electrostatic capacity signal is generated by this, and this electrostatic capacity signal is input to the low-pass filter 3, smoothed by the low-pass filter 3, input as a control signal to the voltage-controlled oscillator 5, and the oscillation frequency of the voltage-controlled oscillator 5 is It is controlled.
The voltage controlled oscillator 5 is provided with the VI conversion circuit 10 and the voltage controlled oscillation circuit 20 shown in FIG. 9, and the oscillation frequency of the voltage controlled oscillation circuit 20 is determined by the output signals PC and NC of the VI conversion circuit 10. Be controlled.
According to this type of conventional PLL circuit, the oscillation frequency of the oscillation signal Fo of the voltage controlled oscillator 5 has characteristics as shown in FIG. 10 with respect to the control voltage.
In this type of conventional PLL circuit, there is a relatively large variation in oscillation frequency due to the manufacturing process and temperature, and the frequency change with respect to the control bias is large. Therefore, when noise is superimposed on the control bias, the jitter of the PLL circuit increases.

With the aim of reducing this jitter, Patent Document 2 discloses, as a voltage control circuit, as shown in FIG. 8, a frequency variable inverter 17 for controlling the frequency, and a plurality of inverters 18 connected in series to the inverter 17. However, a ring oscillator connected to the multistage multiplexer 16 is used.
However, since the ring oscillator shown in FIG. 8 is provided with a buffer line for each different number of stages, the circuit scale becomes large and complicated, and the number of buffer stages is continuously adjusted. There is a problem that occurs.
JP 2000-216676 A JP 2000-232356 A

  The present invention has been made in view of the present situation of this type of PLL circuit as described above, and its purpose is to prevent malfunction due to externally mixed noise, to reduce the layout mounting area, and to achieve stable high accuracy. It is an object of the present invention to provide a downsized PLL circuit that performs the oscillation operation.

In order to achieve the above object, a PLL circuit according to claim 1 includes a phase comparator that performs phase comparison between a reference clock signal and a divided clock signal, and charging and discharging based on a phase difference signal from the phase comparator. A charge pump that creates a capacitance signal by performing, a low-pass filter that smoothes the capacitance signal and outputs an analog control signal, a voltage-current conversion circuit that converts the analog control signal into a voltage-current, and A voltage-controlled oscillator comprising a ring oscillator controlled based on an output from the voltage-current converter, and a frequency-dividing circuit for multiplying an oscillation signal output from the voltage-controlled oscillator and outputting the divided clock signal And the frequency comparator that outputs the digital control signal based on a comparison result of the frequency of the reference clock signal and the divided clock signal, And a frequency detecting circuit for performing wavenumber detection, the input terminal of the phase comparator, which is connected input terminal of the input terminal and the frequency detection circuit of the frequency comparator each other, the output terminal of the voltage controlled oscillator and input terminals In between, the frequency divider circuit is connected, and the output terminal of the frequency detection circuit is connected to the frequency comparator and the phase comparator, and the ring oscillator outputs an output signal from the voltage-current converter circuit A buffer for adjusting its own delay time and a plurality of differential buffers are connected in series, and the selection control of the number of differential buffer stages is performed based on a digital control signal from the frequency comparator. is composed from the digital control buffer unit and which is found the frequency comparison during frequency acquisition, the logic value of the output signal of the frequency detection circuit as "0" An enable, the phase comparator is disabled, the analog control signal is set to a predetermined voltage, the delay time of the buffer is adjusted based on the predetermined voltage, the digital control signal from the frequency comparator Is input to the voltage controlled oscillator, and the differential buffer at the position of the selected number of stages of the differential buffer is enabled, thereby setting the selection of the number of stages of the differential buffer. The oscillation signal is output from the voltage controlled oscillator that is voltage-controlled by the ring oscillator, and the divided clock signal is output by the divider circuit based on the oscillation signal, and the divided clock signal is output by the frequency detection circuit. When it is detected that the signal is within a predetermined frequency range set in advance with respect to the frequency of the reference clock signal, the frequency detection circuit The logic value of the output signal of the path is set to “1”, the frequency comparator is disabled, the phase comparator is enabled, and the voltage is controlled by the ring oscillator in which the selection of the number of differential buffer stages is set. When the oscillation signal is output from the voltage controlled oscillator and is detected not to be within the predetermined frequency range, the difference between the new digital control signal and the logic value of the output signal of the frequency detection circuit remains at “0”. The selection of the number of dynamic buffer stages is performed, and the selection of the number of buffer stages of the differential type is repeated until it is detected that it is within the predetermined frequency range .

Therefore , most of the delay control of the ring oscillator buffer is controlled digitally, and external noise is prevented from entering from the power supply terminal, ground terminal, substrate, etc., and jitter due to the influence of noise is prevented. In addition, by setting the analog control signal to the initial value, an operating point with a margin is set for the ring oscillator immediately after pulling in the frequency, and stable and highly accurate in response to subsequent temperature fluctuations and voltage fluctuations. The oscillation frequency is output.

According to a second aspect of the present invention, in the PLL circuit according to the first aspect, the differential buffer in the digital control buffer unit is an inverter type buffer, and the digital signal input to the selector connected to the inverter type buffer. The number of selector stages is selected based on the control signal.

According to the first aspect of the present invention, most of the delay control of the ring oscillator buffer is digitally controlled, and external noise is prevented from entering from the power supply terminal, the ground terminal, the substrate, and the like. Jitter generation due to the influence of noise is prevented, and by setting the analog control signal to the initial value, an operating point with a margin is set in the ring oscillator immediately after pulling in the frequency, and subsequent fluctuations in temperature and voltage Correspondingly, it is possible to output a highly accurate and stable oscillation frequency.

According to the second aspect of the present invention, it is possible to simplify the overall configuration and reduce the manufacturing cost.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a block diagram showing the configuration of the present embodiment, FIG. 2 is a circuit explanatory diagram showing the configuration of the ring oscillator of the voltage controlled oscillator of the same embodiment, and FIG. 3 is a circuit showing the configuration of the main part of FIG. 4 is a circuit diagram showing the configuration of the digital control type stage number selection buffer of FIG. 2, and FIG. 5 is a characteristic diagram showing the operation of this embodiment.

The present embodiment has a configuration as shown in FIG. 1, and a charge pump (CP) 2 that charges and discharges and outputs a capacitance signal is connected to a phase comparator (PFD) 1 that performs phase comparison. CP2 is connected to a first control terminal of a voltage controlled oscillator (VCO) 5 via a low pass filter (LPF) 3 that smoothes the capacitance signal.
A frequency comparator (FD) 6 that performs frequency comparison and a frequency detection circuit 7 that performs frequency detection are provided. The output terminal of the FD 6 is connected to the second control terminal of the VCO 5, and the first of the PFD 1 is connected. The input terminal, the first input terminal of the FD 6 and the first input terminal of the frequency detector 7 are connected to each other, and the reference clock signal Fr is input to the first input terminals connected to each other. Yes.
Further, the second input terminal of PFD1, the second input terminal of FD6, and the second input terminal of frequency detector 7 are connected to each other. Between these connected second input terminals and the output terminal of VCO5. Further, a frequency dividing circuit 8 that multiplies the oscillation signal Fo of the VCO 5 and outputs a divided clock signal Fv is connected, and the output terminal of the frequency detection circuit 7 is connected to the disable terminal of the FD 6 and the enable terminal of the PFD 1. ing.

  As shown in FIG. 2, the ring oscillator 13 of the present embodiment has a configuration in which a plurality of stages of differential buffers are connected in series, and a digital control buffer unit 12 for selecting the number of stages is provided. The digital control buffer unit 12 is provided with a plurality of buffers Bd in which enable / disable selection is digitally controlled, and two buffers Bd are connected in series corresponding to the number of stages. A stage number selection buffer Bdo is connected to the output node of the buffer Bd at the connection end, and the stage number selection of the ring oscillator 13 is performed by the stage number selection buffer Bdo provided in the digital control buffer section 12. It is configured to be.

By the way, as shown in FIG. 3, the VCO 5 receives an analog control signal Fa from the LPF 3, and a V-I conversion circuit 10 that V-I converts the analog control signal Fa, and the V-I conversion circuit 10. The ring oscillator 13 is connected to the above-described ring oscillator 13, and the analog-controlled buffer Ba is provided with a P-channel transistor PCTr and an N-channel transistor NCTr, and is based on an analog control signal Fa input from the LPF 3 to the VCO 5. Thus, the PCBa is controlled by the PC signal output from the VI conversion circuit 10 and the NCTr is controlled by the NC signal, so that the buffer Ba is analog-controlled and the buffer delay time is adjusted. Yes.
In addition, the buffer Bd of the digital control buffer unit 12 is configured so that, when enabled, the P-channel transistor PCTr is grounded and the N-channel transistor NCTr is fixed to the VCC potential when the digital control signal Fd output from the FD 6 is enabled. When the output signal is set and disabled, the logic value of the differential output signal is controlled to be set to “0”.
In this way, the buffer Bd is connected and arranged in a plurality of stages as shown in FIG. 2, and the output node of the buffer Bd corresponding to each stage has the number of stages provided with a differential input section as shown in FIG. The selection buffer Bdo is connected, and the line number of the stage number selection buffer Bdo is designated and selected by the digital control signal Fd from the FD 6 so that the optimum number of buffer stages is selected.

The operation of the present embodiment having such a configuration will be described.
According to the present embodiment, at the time of frequency pull-in, the logical value of the output signal PFDEN of the frequency detection circuit 7 is set to “0”, PFD1 is disabled, and FD6 is enabled. In this state, VCO5 The analog control value is set to a predetermined voltage, and the buffer Ba is analog-controlled by the PC signal and the NC signal output from the VI conversion circuit 10 based on the predetermined voltage, and the delay time is adjusted.
In this state, the digital control signal Fd is input from the FD 6 to the second control terminal of the VOC 5, the buffer Bd of the digital control buffer unit 12 is digitally controlled, and only the buffer Bd at the selected stage number position is enabled. Other buffers Bd are disabled. Then, the output signal of the enabled buffer Bd is input to the stage number selection buffer Bdo connected to the buffer Bd.

  In this way, the oscillation signal Fo is output from the voltage-controlled VCO 5 by the ring oscillator 13 in which the selection of the number of stages of the buffer is set. The oscillation signal Fo is divided by the frequency dividing circuit 8 to detect the frequency. The circuit 7 detects whether or not the frequency-divided clock signal Fv input from the frequency-dividing circuit 8 is within a predetermined frequency range set in advance with respect to the frequency of the reference clock signal Fr from the outside. When the frequency detection circuit 7 detects that the divided clock signal Fv is not within the predetermined frequency range, the logical value of the output signal PFDEN of the frequency detection circuit 7 maintains “0”, and a new digital control signal Fd The stage number selection operation by the digital control signal Fd is repeated until the frequency detection circuit 7 detects that the divided clock signal Fv is within the predetermined frequency range.

When the frequency detection circuit 7 detects that the divided clock signal Fv is within the predetermined frequency range, the logical value of the output signal PFDEN of the frequency detection circuit 7 becomes “1”, and the FD 6 is disabled. Thus, the number of stages of the ring oscillator 13 is fixedly set, the PFD 1 is enabled, the ring oscillator 13 whose number of stages is selected and fixed is driven by analog control of the buffer Ba, and has a frequency corresponding to the selected number of stages. Oscillates.
As shown in FIG. 5, the operation in this case is performed by selecting an optimum number of buffer stages for oscillating at a predetermined frequency corresponding to a predetermined VCO control voltage. In this case, the oscillation frequency can be adjusted with respect to subsequent temperature fluctuations and voltage fluctuations.

  Thus, according to the present embodiment, at the time of frequency pull-in, the logical value of the output signal PFDEN of the frequency detection circuit 7 is set to “0”, PFD1 is disabled, FD6 is enabled, and VCO5 The analog control value is set to a predetermined voltage, the buffer Bd at the selected stage number position of the digital control buffer unit 12 is enabled by the digital control signal Fd from the FD 6, and the oscillation signal Fo output from the VCO 5 is divided. The frequency detection circuit 7 detects whether or not the frequency-divided clock signal Fv is within a predetermined frequency range set in advance with respect to the frequency of the reference clock signal Fr. In this case, until the frequency detection circuit 7 detects that the divided clock signal Fv is within the predetermined frequency range, the logical value of the output signal PFDEN of the frequency detection circuit 7 remains “0”, and a new digital signal is generated. A stage number selection operation is performed by the control signal Fd.

When the frequency detection circuit 7 detects that the divided clock signal Fv is within the predetermined frequency range, the logical value of the output signal PFDEN of the frequency detection circuit 7 becomes “1”, and the FD 6 is disabled. Thus, the number of stages of the ring oscillator 13 is fixedly set, the PFD 1 is set to enable, and the VCO 5 is voltage-controlled based on the ring oscillator 13 with the number of stages selected and fixed, and the oscillation of the frequency corresponding to the selected number of stages is performed. .
In this manner, according to the present embodiment, most of the delay control of the buffer of the ring oscillator 13 is performed digitally, so that external noise is prevented from being mixed from the power supply terminal, the ground terminal, and the substrate. In addition to preventing jitter due to noise, the analog control signal is set to the initial value to set an operating point with a margin in the ring oscillator immediately after the frequency is pulled. In response to the fluctuation, it is possible to output a highly accurate and stable oscillation frequency.

[Second Embodiment]
A second embodiment of the present invention will be described with reference to FIG.
FIG. 6 is a circuit explanatory diagram showing the configuration of the ring oscillator of the present embodiment.

In this embodiment, as shown in FIG. 6, the ring oscillator 13A has a configuration in which a plurality of inverter-type buffers are connected in series, and the digital control buffer unit 12A includes an analog-controlled buffer. A plurality of buffers Bd1 whose selection of the number of stages is digitally controlled are arranged in Ba1, and each output node of these buffers Bd1 is connected to a selector 15 for selecting the number of stages, and the number of stages of the selector 15 is set. The digital control signal Fd from the FD 6 to be selected is input to the selector 15.
Since the configuration of the other parts of the present embodiment is the same as that of the first embodiment already described, duplicate description will not be given.

In this embodiment having such a configuration, the description will be made with reference to FIG. 1. The number of stages of the buffer Bd1 having a predetermined number of stages is selected by the digital control signal Fd from the frequency detection circuit 7 shown in FIG. The oscillation operation is voltage controlled.
The other operations in the present embodiment are the same as those in the first embodiment already described, and therefore will not be described repeatedly.
According to the present embodiment, in addition to the effects obtained in the first embodiment, an inverter type buffer is used, the configuration of the selector 15 is simplified, and the overall configuration can be simplified. It becomes possible.

It is a block diagram which shows the structure of the 1st Embodiment of this invention. It is a circuit explanatory drawing which shows the structure of the ring oscillator of the voltage controlled oscillator of the embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a main part of FIG. 2. FIG. 3 is a circuit diagram showing a configuration of a digital control type stage number selection buffer of FIG. 2. It is a characteristic view which shows the operation | movement of the embodiment. It is circuit explanatory drawing which shows the structure of the ring oscillator of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the conventional PLL circuit. FIG. 8 is a circuit diagram showing a configuration of a ring oscillator of the voltage controlled oscillator of FIG. 7. It is a circuit diagram which shows the structure of the principal part of FIG. FIG. 8 is a characteristic diagram illustrating an operation of the PLL circuit of FIG. 7.

Explanation of symbols

1 PRD
2 CP
3 LPF
5 VCO
7 Frequency detection circuit 8 Divider 13 Ring oscillator

Claims (2)

A phase comparator that compares the phase of the reference clock signal and the divided clock signal;
A charge pump that creates a capacitance signal by charging and discharging based on the phase difference signal from the phase comparator;
A low-pass filter that smoothes the capacitance signal and outputs an analog control signal;
A voltage-controlled oscillator comprising a voltage-current conversion circuit for converting the analog control signal into voltage-current, and a ring oscillator controlled based on an output from the voltage-current conversion circuit;
A frequency dividing circuit for multiplying an oscillation signal output by the voltage controlled oscillator and outputting the divided clock signal;
The frequency comparator that outputs the digital control signal based on a frequency comparison result between the reference clock signal and the divided clock signal;
A frequency detection circuit for performing frequency detection,
The input terminal of the phase comparator, the input terminal of the frequency comparator and the input terminal of the frequency detection circuit are connected to each other, and the frequency divider circuit is connected between these input terminals and the output terminal of the voltage controlled oscillator, And the output terminal of the frequency detection circuit is connected to the frequency comparator and the phase comparator,
The ring oscillator is controlled based on an output signal from the voltage-current conversion circuit, and a buffer for adjusting its own delay time and a differential buffer are connected in series in a plurality of stages, and a digital signal from the frequency comparator is provided. The digital control buffer unit is configured to select and control the number of differential buffer stages based on the control signal,
During frequency acquisition, enabling said frequency comparator as the logic value "0" of the output signal of said frequency detecting circuit, the phase comparator is disabled, setting the analog control signal at a predetermined voltage, the predetermined Adjusting the delay time of the buffer based on the voltage;
The digital control signal from the frequency comparator is input to the voltage controlled oscillator, and the differential type buffer at the selected number of stages among the differential type buffers is set to enable, so that the differential type The oscillation signal is output from the voltage-controlled oscillator that is voltage-controlled by the ring oscillator in which selection of the number of stages of the buffer is set, and the divided clock signal is output by the divider circuit based on the oscillation signal,
When the frequency detection circuit detects that the divided clock signal is within a predetermined frequency range set in advance with respect to the frequency of the reference clock signal, the logic value of the output signal of the frequency detection circuit is changed to “ 1 ”disables the frequency comparator, enables the phase comparator, and outputs the oscillation signal from the voltage controlled oscillator that is voltage controlled by the ring oscillator in which the selection of the number of differential buffer stages is set And
When it is detected that it is not within the predetermined frequency range, the logic value of the output signal of the frequency detection circuit is set to “0”, and the number of differential buffer stages is selected by a new digital control signal, A PLL circuit that repeats selection of the number of differential buffer stages until it is detected that the frequency is within the predetermined frequency range . The differential buffer in the digital control buffer unit is an inverter buffer, and the number of stages of the selector is selected based on the digital control signal input to the selector connected to the inverter buffer. The PLL circuit according to claim 1, wherein:

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