JPH09153799A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To oscillate one voltage controlled oscillator(VCO) over wide frequency range. SOLUTION: A frequency detection circuit 15 detects the frequency of horizontal synchronizing signal and generates a mode switching signal corresponding to the detected frequency. A VCO 13 consisting of a PLL circuit 16 has plural oscillation modes, for which the frequency of integer multiple of horizontal synchronizing signal is divided into plural frequency ranges, and oscillates the signals of respective frequency ranges corresponding to a control voltage outputted from a filter 12. The oscillation mode of this VCO 13 is switched corresponding to the mode switching signal outputted from the frequency detection circuit 15. Therefore, the frequencies of wide range can be oscillated by one VCO 13. Further, since the ranges of frequencies in respective oscillation modes of VCO 13 are narrow, oscillation gain can be suppressed low and the degradation of jitter characteristics can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having, for example, an oscillator circuit, and more particularly to a horizontal oscillator applied to a monitor or a television receiver capable of varying the frequency of a horizontal synchronizing signal in a wide range. Regarding the circuit.

[0002]

2. Description of the Related Art For example, a PLL (Phase
Locked Loop) circuit is used. This PLL circuit is provided with a voltage controlled oscillator (hereinafter referred to as VCO) that generates a clock signal that is n times (n is an integer) a horizontal synchronizing signal used in a normal television receiver.

Conventionally, this VCO has only been required to generate a single frequency. However, recently, a monitor called a multi-scan monitor, which has been developed, has a switchable scan speed. The frequency of the horizontal synchronizing signal supplied from the computer to this type of monitor is, for example, 20 kHz.
It varies in the range of up to 100 kHz. Therefore, the VCO applied to the horizontal oscillation circuit is required to be able to oscillate in a wide frequency range of the horizontal synchronizing signal.

[0004]

SUMMARY OF THE INVENTION One VC
When it is attempted to oscillate O in a wide frequency range, this VCO requires a high oscillation gain. When the gain is increased in this way, the frequency response speed increases, and the jitter characteristic deteriorates.

Therefore, it is conceivable to provide a plurality of VCOs having different oscillation frequency ranges and operate the plurality of VCOs by switching them according to the frequency of the horizontal synchronizing signal.
However, in this case, a plurality of VCOs are required, and in order to switch these VCOs, a frequency-voltage converter that generates a voltage according to the frequency of the horizontal synchronizing signal is required, so that the circuit scale becomes large. Occur.

The present invention is intended to solve the above problems, and an object of the present invention is to suppress the oscillation gain of the VCO to a low level and prevent the deterioration of the jitter characteristics, and to increase the circuit scale. It is intended to provide a horizontal oscillation circuit that can be prevented.

[0007]

In order to solve the above problems, the present invention detects a frequency of a horizontal synchronizing signal and generates a switching signal according to the detected frequency, and the horizontal synchronizing signal. A frequency that is an integral multiple of is divided into a plurality of frequency ranges, and has a plurality of oscillation modes that oscillate the signals of the respective divided frequency ranges according to the control voltage, and the oscillation modes are output from the frequency detection means. And a voltage controlled oscillator that is switched according to the switching signal.

Further, the present invention compares the phase of the horizontal synchronizing signal and the phase of the reference signal with a frequency detecting circuit which detects the frequency of the horizontal synchronizing signal and generates a switching signal according to the detected frequency. , A phase comparison circuit that outputs signals corresponding to these phase differences, a filter circuit that is supplied with the output signal of this phase comparison circuit and that generates a control voltage from this output signal, and a frequency that is an integral multiple of the horizontal synchronization signal Is divided into a plurality of frequency ranges, and has a plurality of oscillation modes for oscillating signals in the respective frequency ranges according to the control voltage supplied from the filter circuit, and the oscillation modes are output from the frequency detecting means. It comprises a voltage controlled oscillator that is switched according to a switching signal, and frequency dividing means that divides the output signal of the voltage controlled oscillator to generate the reference signal.

Further, the present invention compares the phase of the horizontal synchronizing signal and the phase of the reference signal with a frequency detecting circuit which detects the frequency of the horizontal synchronizing signal and generates a switching signal according to the detected frequency. , A phase comparison circuit that outputs signals corresponding to these phase differences, a filter circuit that is supplied with the output signal of the phase comparison circuit, and that generates a control voltage from the output signal, and a frequency that is an integral multiple of the horizontal synchronization signal Is divided into a plurality of frequency ranges, and has a plurality of oscillation modes for oscillating signals in the respective frequency ranges according to the control voltage supplied from the filter circuit, and the oscillation modes are output from the frequency detecting means. A voltage-controlled oscillator that is switched according to a switching signal, and frequency-dividing means that divides the output signal of the voltage-controlled oscillator to generate the reference signal,
A horizontal drive circuit that is supplied with the output signal of the voltage controlled oscillator and that generates a horizontal drive pulse signal, a capacitor that is connected to the horizontal drive circuit and that compensates for horizontal linearity, and a switch that is output from the frequency detection means. A deflection switching circuit that switches the capacitance of the horizontal drive circuit according to a signal, and a setting circuit that sets the operation sequence of the voltage controlled oscillator and the deflection switching circuit according to the switching signal output from the frequency detecting means. It has.

That is, according to the present invention, a signal having a wide frequency range can be oscillated by one voltage controlled oscillator. Moreover, since each oscillation mode of the voltage controlled oscillator has a narrow frequency range, it is possible to reduce the oscillation gain of the voltage controlled oscillator and reduce the jitter. Since the frequency detection circuit can be configured by a simple circuit, it is possible to suppress an increase in the overall circuit scale.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In FIG. 1, the PLL circuit 16
Is composed of a phase comparator 11, a loop filter 12 as a low-pass filter, a VCO 13, and a frequency divider 14. The first input terminal of the phase comparator 11 is supplied with, for example, a horizontal synchronizing signal f _H whose frequency changes in a wide range output from a computer (not shown), and the second input terminal thereof is provided with the frequency divider. 14 reference signal f _r substantially the same frequency as the horizontal synchronizing signal f _H to be output is supplied from. The phase comparator 11 detects a phase difference between the horizontal synchronizing signal f _H and the reference signal f _r. The signal corresponding to the detected phase difference is supplied to the loop filter 12, and the loop filter 12 outputs the control voltage V _L corresponding to the input signal. This control voltage V _L is supplied to the VCO 13. The VCO 13 generates a signal nf _H according to the control voltage V _L supplied from the loop filter 12. This signal nf _H has a frequency n times (n is an integer) the frequency of the horizontal synchronizing signal f _H. As will be described later, the VCO 13 has a plurality of oscillation modes in which a wide frequency range is divided into a plurality of ranges, the oscillation frequency range in each oscillation mode is set narrow, and the oscillation gain is lowered. This VCO1
The signal nf _H output from 3 is supplied to a horizontal drive circuit (not shown) and also to the frequency divider 14. The frequency divider 14 divides the period of the input signal to 1 / n, to generate the reference signal f _r.

On the other hand, the frequency detecting circuit 15 is supplied with the horizontal synchronizing signal f _H and the clock signal CL. As shown in FIG. 10, the frequency detection circuit 15 is composed of, for example, a counter 15a that counts the clock signal CL and a decoder 15b connected to the counter 15a. The counter 15a is 1 period of the horizontal synchronizing signal f _H input, i.e. by counting the clock signal CL to the period of 1H, detecting the frequency of the horizontal synchronization signal f _H. The decoder 15b switches the mode switching signal M for switching the oscillation mode of the VCO 13 according to the detected frequency.
It outputs Sn (n = 1 to 4). In the case of this embodiment, the decoder 15b sets, for example, any one of the mode switching signals MS1 to MS4 to, for example, a high level according to the detected frequency.

The mode switching signal MSn is appropriately set according to each embodiment described later. That is, the configuration of the decoder 15b can be changed according to each embodiment. Therefore, for example, at least one of the mode switching signals MS1 to MS4 can be set to a high level or a low level according to the detected frequency. This kind of decoder can be constructed by a known technique using a logic circuit.

FIG. 2 shows an example of the VCO 13. This VCO 13 is, for example, the ring oscillator 2
0 and selector 21. The ring oscillator 20 is composed of an odd number of inverter circuits 20 _{1 to} 20 _{n + 1} connected in series. The control voltage V _L output from the loop filter 12 is supplied to each of the inverter circuits 20 _{1 to} 20 _{n + 1} .

Further, the inverter circuits 20 _n-5 , 20
_The output terminals _n-3 , 20 _n-1 , and 20 _{n + 1} are connected to the selector 2
1 input terminal. The selector 21 is supplied with the mode switching signal MSn output from the frequency detecting circuit 15, and the selector 21 responds to the mode switching signal MSn by the inverter circuits 20 _n-5 , 20 _n.
One of the output signals output from _n-3 , 20 _n-1 , and 20 _{n + 1} is selected. That is, the selector 21 switches the number of stages of the inverter circuits forming the ring oscillator 20 according to the mode switching signal MSn to switch the oscillation mode. The output signal of the selector 21 is supplied to the output terminal of the inverter circuit 20 ₁ located at the head. Therefore, the VCO 13 has its oscillation mode switched in response to the mode switching signal MSn and outputs the signal nf _H.

FIG. 3 shows the operation of the VCO 13. This VCO 13 has mode switching signals MS1 to MS4.
The oscillation mode is switched according to. In each of the switched oscillation modes, the oscillation operation is performed at a predetermined frequency according to the control voltage V _L output from the loop filter 12, as indicated by the solid line.

FIG. 4 shows an example of an inverter circuit which constitutes the ring oscillator 20. Power supply V
A P-channel MOSFET (hereinafter referred to as PMO) between dd and ground.
Current paths of P1 and P2 (referred to as S) and N channel MOSFETs (hereinafter referred to as NMOS) N1 and N2 are connected in series. These PMOSP1, P2, NMOSN
Gates of 1 and N2 are commonly connected, and PMOSP2 and N
The connection point with MOSN1 is an output terminal. The PM
The PMOS P3 and P4 are connected in parallel to the OSP1, and the control voltage V _L output from the loop filter 12 is supplied to the gates of the PMOS P3 and P4.
The current flowing through the PMOSs P3 and P4 is the control voltage V _L.
It changes according to. Therefore, the current flowing through the PMOS P1 also changes according to the control voltage V _L. That is, this P
The dimension of the MOSP1 is switched according to the control voltage V _L, and the oscillation frequency of the ring oscillator 20 is changed according to the change of this dimension.

According to the above embodiment, the VCO 13 is a ring oscillator 20 in which a plurality of inverter circuits are connected in series.
In accordance with the frequency of the horizontal synchronizing signal f _H detected by the frequency detecting circuit 15, the number of stages of the inverter circuit forming the ring oscillator 20 is switched to switch the oscillation mode. Further, in each oscillation mode, the oscillation frequency is changed according to the control voltage V _L. Therefore, one VCO 13 can oscillate a signal having a wide frequency range. Moreover, each oscillation mode of the VCO 13 has a narrow frequency range as shown by the solid line in FIG. Therefore, as shown by the broken line in FIG. 3, the oscillation gain of the VCO 13 can be lowered and the jitter can be reduced as compared with the case where the frequency range is wide.

Further, the VCO 13 has a plurality of Vs as in the conventional case.
Since no CO is required and the frequency detection circuit can be configured by a simple circuit, the circuit scale is smaller than that of the conventional frequency voltage converter. Therefore, it is possible to suppress an increase in the overall circuit scale.

FIG. 5 shows another example of the inverter circuit which constitutes the ring oscillator 20, and FIG.
The same parts as those of the above are given the same reference numerals, and only different parts will be described. In this example, the NMOS N3 and N4 are the N
They are respectively connected in parallel to the MOSN2. Further, the control voltage V _L1 output from the output terminal of the loop filter 12 is supplied to the gates of the PMOS P3 and P4, and the input terminal of the loop filter 12 (the phase comparison circuit) is supplied to the gates of the NMOS N3 and N4. The control voltage V _L2 output from the output voltage of the device 11) is supplied.

FIG. 6 shows an example of the loop filter 12. The loop filter 12 is composed of a differential amplifier 31 and resistors 32, 33, 34 and 35. That is, the output terminal of the phase comparator 11 is connected to the non-inverting input terminal of the differential amplifier 31 via the resistor 32. A resistor 33 is connected between the non-inverting input terminal and the output terminal 33 of the differential amplifier 31. Resistors 34 and 35 are connected in series between the power supply Vdd and the ground. These resistors 3
The connection point of 4, 35 is connected to the inverting input terminal of the differential amplifier 31. The control voltage V _L1 is output from the output terminal of the differential amplifier 31, and the control voltage V _L2 is output from the output terminal of the phase comparator 11.

For example, when the phase of the horizontal synchronizing signal f _{H leads} the phase of the reference signal f _r , the phase comparator 11
Outputs a high level signal, when the phase of the horizontal synchronization signal f _H is delayed from the phase of the reference signal f _r, and outputs a low level signal. Further, when the phase of the phase reference signal f _r of the horizontal synchronization signal f _H is equal, a high impedance state.

The inverter circuit having the configuration shown in FIG. 5 switches the oscillation frequency of the VCO 13 by switching the dimensions of the PMOS and NMOS according to the control voltage V _L1 and the control voltage V _L2 of the loop filter 12. . With such a configuration, the range of oscillation frequency can be increased.

In the above embodiment, the control voltage V _L2
It is also possible to supply a fixed voltage to the gates of the NMOS N3 and N4 without using. In this case, noise can be reduced.

FIG. 7 shows another example of the inverter circuit which constitutes the ring oscillator 20, and FIG.
The same parts as those of the above are given the same reference numerals, and only different parts will be described. In this example, the PMOS P1 has a plurality of PMOs.
SP5, P6, P7 and P8 are connected. These P
The mode switching signal MS1 output from the frequency detection circuit 15 is applied to the gates of the MOSP5, P6, P7 and P8.
MS2, MS3, MS4 are supplied. Further, the control voltage V _L of the loop filter 12 is supplied to the gates of the NMOSs N3 and N4. In the case of this example, the frequency detection circuit 15 determines, according to the detected frequency,
At least one of the mode switching signals MS1 to MS4 is set to a high level, for example.

The dimension of the PMOS P1 is switched by changing the conduction number of the PMOS P5, P6, P7 and P8 by the mode switching signals MS1, MS2, MS3 and MS4. The oscillation mode of the VCO can be switched by switching the dimensions of the PMOS P1. Therefore, when the inverter circuit that constitutes the ring oscillator 20 is configured as described above, the selector 21 shown in FIG. 2 becomes unnecessary, so that the output signal of the final stage inverter circuit is input to the input terminal of the first inverter circuit. It may be configured to provide feedback.

FIG. 8 shows another example of the VCO 13. In the example shown in FIG. 2, the ring oscillator is composed of a plurality of inverter circuits, but in this example, an odd number of differential amplifiers 51 _{1 to} 51 _n , 51 connected in series are used.
It is composed of _{n + 1} and a selector 52. The control voltage V is applied to the differential amplifiers 51 _{1 to} 51 _n and 51 _{n + 1.
L1} and V _L2 are supplied.

The selector 52 selects the output signals of the differential amplifiers 51 _n and 51 _{n + 1} according to the mode switching signal MSn. Here, when the selector 52 selects the output signal of the odd-numbered differential amplifier, the non-inverting output signal and the inverting output signal of the differential amplifier are input to the non-inverting input terminal and the inverting input terminal of the differential amplifier 51 _1. Supply each. When selecting the output signal of the even-numbered differential amplifier, the inverted output signal and the non-inverted output signal of the differential amplifier are supplied to the non-inverted input terminal and the inverted input terminal of the differential amplifier 51 ₁ , respectively.

Even when the VCO shown in FIG. 8 is used, the same effect as that of the above-mentioned embodiment can be obtained. Further, each differential amplifier has a constant current source (not shown). Therefore, compared to the inverter circuit, there is less noise during switching and noise due to power supply fluctuation. Therefore, the jitter characteristic is superior to that of the ring oscillator using the inverter circuit.

FIG. 9 shows a second embodiment of the present invention, and the same parts as those in FIG. 1 are designated by the same reference numerals. In this embodiment, the timing for switching the oscillation mode of the VCO according to the frequency of the horizontal synchronizing signal and the timing for compensating the horizontal linearity of the horizontal drive circuit are changed.

In FIG. 9, the output terminal of the frequency detecting circuit 15 is connected to the VCO 13 via a first timer 61.
And the deflection switching circuit 63 is connected via the second timer 62. The output signal nf _{H of the} VCO 13 is supplied to the horizontal drive circuit 64. The deflection switching circuit 63 is connected to the horizontal drive circuit 64. The horizontal drive circuit 64 is provided with a capacitor Cp whose capacity can be switched. By changing the capacity of this capacitor, horizontal linearity can be compensated. The deflection switching circuit 63 switches the capacitance of the capacitor Cp provided in the horizontal drive circuit 64 according to the frequency of the horizontal synchronizing signal. The frequency detection circuit 1 excluding the deflection switching circuit 63 and the horizontal drive circuit 64
5, the PLL circuit 16, the first and second timers 61 and 62 are integrated.

The frequency detection circuit 15 includes the VCO 13
Output a mode switching signal MSn for controlling the control signal, a control signal MS2n for controlling the deflection switching circuit 63, and control signals TS1, TS2 for controlling the first and second timers 61, 62. The control signals TS1 and T
S2 is a complementary signal, and the first and second timers 6
One of the first and second operation modes 1 and 62 is set by the control signals TS1 and TS2, respectively. When the first operation mode is set, the first and second timers 61 and 62 immediately output the input signal, and when the second operation mode is set, the input signal is 100 to 200 ns.
Delay and output.

When the frequency of the horizontal synchronizing signal is switched from the low frequency state to the high frequency state, the first timer 61 is set to the first operation mode in accordance with the control signals TS1 and TS2, and the second timer 62 is set to the second operation mode. 2 operation mode is set. Therefore, first, the mode switching signal MSn is supplied to the VCO 13 via the first timer 61, and the oscillation frequency of the VCO 13 is increased. Thereafter, the control signal MS2n is supplied to the deflection switching circuit 63 via the second timer 62,
The deflection switching circuit 63 switches the capacitance of the capacitor Cp provided in the horizontal drive circuit 64.

On the other hand, when the frequency of the horizontal synchronizing signal is switched from high to low, the control signals TS1 and TS2
Accordingly, the first timer 61 is set to the second operation mode, and the second timer 62 is set to the first operation mode. Therefore, first, the control signal MS2n is supplied to the deflection switching circuit 63 via the second timer 62, and the deflection switching circuit 63 switches the capacitance of the capacitor Cp provided in the horizontal drive circuit 64. After this, the first
The mode switching signal MSn passes through the timer 61 of
13 and the oscillation frequency of the VCO 13 is reduced.

FIG. 11 shows the frequency detection circuit 15. The frequency detection circuit 15 is, for example, a counter 15
a, a first decoder 15b, a second decoder 15c, first and second memories 15d and 15e, and a comparator 15f. The counter 15a and the first decoder 15b are the same as in FIG. The second decoder 1
5c is connected to the output terminal of the counter 15a. The second decoder 15c generates the control signal MS2n for switching the capacity of the capacitor Cp provided in the horizontal drive circuit 64 according to the frequency of the horizontal synchronizing signal output from the counter 15a.

First and second memories 15d and 15e are sequentially connected to the output terminal of the first decoder 15b. The first memory 15d stores the current mode switching signal output from the first decoder 15b, and the second memory 15e stores the previous mode switching signal. The data stored in the first and second memories 15d and 15e are updated when the mode switching signal output from the first decoder 15b changes. The first and second memories 15d and 15e are connected to the input terminal of the comparator 15f. The comparator 15f compares the mode switching signal stored in the first memory 15d with the mode switching signal stored in the second memory 15e, and outputs the control signals TS1 and TS2 according to the comparison result. Output. That is, according to the comparison result, it can be known whether the frequency of the horizontal synchronizing signal is switched from the low state to the high state or from the high state to the low state. When the frequency of the horizontal synchronizing signal is switched from low to high, the comparator 15
f sets the control signal TS1 to a low level, for example, and sets the control signal TS2 to a high level. On the other hand, when the frequency of the horizontal sync signal is switched from high to low,
The comparator 15f sets the control signal TS1 to a high level,
The control signal TS2 is set to the low level.

FIG. 12 shows the structure of the first timer 61. Since the second timer 62 has the same configuration as the first timer 61, the description thereof will be omitted. Mode switching signal M
Sn (control signal MS2n in the case of the second timer) is supplied to the mismatch detector 61a. This mismatch detector 61
a is composed of, for example, a plurality of exclusive OR circuits, and outputs a signal when the mode switching signal MSn changes. The output signal of the mismatch detector 61a is supplied to, for example, the preset terminal PS of the preset down counter 61b.

The output terminal of the multiplexer (MPX) 61c is connected to the down counter 61b. The time data N is input to the input terminal of the multiplexer 61c.
1, N2 are supplied. The time data N1 is a numerical value that sets a delay time of, for example, 0 ns, and the time data N1
2 is a numerical value that sets a delay time of 100 to 200 ns, for example. The multiplexer 61c selects one of the time data N1 and N2 according to the control signal TS1 and supplies it to the down counter 61b. This down counter 61b
When the signal output from the mismatch detector 61a is supplied to the preset terminal PS, the multiplexer 61c
Set the time data output from.

The clock signal φ is supplied to the clock input terminal CK of the down counter 61b via the flip-flop circuit 61d. This down counter 61b
Down-counts the set time data according to the clock signal φ. The output signal of the down counter 61b is supplied to the all "0" detector 61e. The detector 61d outputs a high level signal D1 when the output signals of the down counter 61b are all "0". This signal is supplied to the flip-flop circuit 61d and the pulse generator 61f. The flip-flop circuit 61d is reset by this signal D1. Therefore, the supply of the clock signal φ to the down counter 61b is stopped. Further, the pulse generator 61f generates a pulse signal according to the signal D1 and supplies the pulse signal to the clock input terminal CK of the flip-flop circuit 61g. The data input terminal D of the flip-flop circuit 61g is supplied with the mode switching signal MSn. The flip-flop circuit 61g is a pulse generator 61f.
When the pulse signal is supplied from the
Output Sn.

In the above configuration, the down counter 61b
When the time data corresponding to the delay time of 0 ns is set to, the detector 61e immediately outputs the signal D1. Therefore, the flip-flop circuit 61g immediately outputs the mode switching signal MSn according to the pulse signal supplied from the pulse generator 61f. On the other hand, when the down counter 61b is set with time data of a numerical value corresponding to the delay time of 100 to 200 ns, the detector 61e outputs the signal D1 when the down counter 61b finishes counting this numerical value.
Is output. Therefore, the flip-flop circuit 61g
Is a mode switching signal M after 100 ns to 200 ns in accordance with the pulse signal supplied from the pulse generator 61f.
Output Sn.

According to this embodiment, the oscillation mode can be set digitally, and the first and second timers 61,
When the frequency of the horizontal synchronizing signal is switched by delaying the mode switching signal output from the frequency detection circuit 15 by 62 for a predetermined time, the switching timing of the oscillation frequency of the VCO 13 and the capacitor provided in the horizontal drive circuit 64. It is possible to set a time difference with the timing of switching the capacity of. Therefore, it is possible to reduce the load on the horizontal drive circuit at the transition when the frequency of the horizontal synchronizing signal is switched. Of course, various modifications can be made without departing from the scope of the present invention.

[0042]

As described in detail above, according to the present invention,
A single voltage controlled oscillator can oscillate a signal in a wide frequency range. Moreover, since each oscillation mode of the voltage controlled oscillator has a narrow frequency range, it is possible to reduce the oscillation gain of the voltage controlled oscillator and reduce the jitter. Also,
Since the frequency detection circuit can be configured with a simple circuit,
It is possible to suppress an increase in the overall circuit scale.

Further, when the frequency of the horizontal synchronizing signal detected by the frequency detecting circuit is switched from the low frequency state to the high frequency state, the setting circuit switches the oscillation frequency of the voltage controlled oscillator and then uses the deflection switching circuit to drive the horizontal drive signal. When the capacitance of the circuit is switched and the frequency of the horizontal synchronizing signal is switched from a high state to a low frequency, the deflection switching circuit switches the capacitance of the horizontal drive circuit and then switches the oscillation frequency of the voltage controlled oscillator. Therefore, it is possible to reduce the load on the horizontal drive circuit at the transition when the frequency of the horizontal synchronizing signal is switched.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram specifically showing the VCO shown in FIG.

FIG. 3 is a diagram for explaining the operation of FIG.

FIG. 4 is a circuit diagram showing an example of the ring oscillator shown in FIG.

5 is a circuit diagram showing another example of the ring oscillator shown in FIG.

6 is a circuit diagram showing an example of the loop filter shown in FIG.

FIG. 7 is a circuit diagram showing another example of the ring oscillator shown in FIG.

FIG. 8 is a circuit diagram showing another example of the VCO shown in FIG.

FIG. 9 is a configuration diagram showing a second embodiment of the present invention.

FIG. 10 is a configuration diagram showing an example of a frequency detection circuit.

FIG. 11 is a configuration diagram showing another example of the frequency detection circuit.

FIG. 12 is a configuration diagram showing an example of a timer.

[Explanation of symbols]

11 ... Phase comparator, 12 ... Loop filter, 13 ... VCO, 14 ... Divider, 15 ... Frequency detection circuit, 15a ... Counter, 15b ... Decoder (first decoder), 15c ... Second decoder, 15d, 15e ... first, second memory, 15f ... comparator, 16 ... PLL circuit, 20 ... ring oscillator, 20 ₁ to 20 _{n + 1} ... inverter circuit, 21 ... _{selectors, 51 1 ~51 n, 51 n} + ₁ ... Differential amplifier, 61, 62 ... First and second timers, 61a ... Mismatch detector, 61b ... Down counter, 61c ... Multiplexer, 61d, 61g ... Flip-flop circuit, 61e ... All "0" detector, 61f ... Pulse generator, 63 ... Deflection switching circuit, 64 ... Horizontal drive circuit.

Claims (9)

[Claims] 1. A frequency detecting means for detecting a frequency of a horizontal synchronizing signal and generating a switching signal according to the detected frequency, and a frequency which is an integral multiple of the horizontal synchronizing signal is divided into a plurality of frequency ranges for control. A voltage controlled oscillator having a plurality of oscillation modes for oscillating the signals of the respective divided frequency ranges according to the voltage, and the oscillation modes being switched according to a switching signal output from the frequency detecting means. A semiconductor integrated circuit characterized by the above. 2. A frequency detection circuit for detecting a frequency of a horizontal synchronizing signal and generating a switching signal according to the detected frequency, and comparing the phase of the horizontal synchronizing signal with the phase of a reference signal,
A phase comparison circuit that outputs signals corresponding to these phase differences, a filter circuit that is supplied with the output signal of this phase comparison circuit, and that generates a control voltage from this output signal, and a frequency that is an integral multiple of the horizontal synchronization signal It has a plurality of oscillation modes which are divided into a plurality of frequency ranges and oscillate a signal in each of the frequency ranges according to a control voltage supplied from the filter circuit, and the oscillation modes are output from the frequency detecting means. A semiconductor integrated circuit comprising: a voltage controlled oscillator that is switched according to a signal; and a frequency dividing unit that divides an output signal of the voltage controlled oscillator to generate the reference signal. 3. A frequency detection circuit for detecting the frequency of a horizontal synchronizing signal and generating a switching signal according to the detected frequency, and comparing the phase of the horizontal synchronizing signal with the phase of a reference signal,
A phase comparison circuit that outputs a signal corresponding to these phase differences, an output signal of the phase comparison circuit is supplied, a filter circuit that generates a control voltage from the output signal, and a frequency that is an integral multiple of the horizontal synchronization signal. It has a plurality of oscillation modes which are divided into a plurality of frequency ranges and oscillate a signal in each of the frequency ranges according to a control voltage supplied from the filter circuit, and the oscillation modes are output from the frequency detecting means. A voltage-controlled oscillator that is switched according to a signal, frequency-dividing means that divides an output signal of the voltage-controlled oscillator to generate the reference signal, and an output signal of the voltage-controlled oscillator is supplied to generate a horizontal drive pulse signal. A horizontal drive circuit to generate, a capacitor connected to this horizontal drive circuit for compensating the horizontal linearity, and an output from the frequency detecting means. Deflection switching circuit for switching the capacitance of the horizontal drive circuit according to a switching signal, and a setting circuit for setting the operation sequence of the voltage controlled oscillator and the deflection switching circuit according to the switching signal output from the frequency detecting means. And a semiconductor integrated circuit. 4. The switching circuit is connected between the frequency detection circuit and the voltage controlled oscillator, and the switching signal is output from the frequency detection circuit in response to a change in frequency detected by the frequency detection circuit. Is connected between the frequency detection circuit and the deflection switching circuit, and outputs the frequency detection circuit according to a change in the frequency detected by the frequency detection circuit. A second timer that delays and outputs the switching signal, and switches the oscillation frequency of the voltage controlled oscillator when the frequency of the horizontal synchronizing signal detected by the frequency detecting circuit is switched from a low state to a high state. After that, when the capacity of the horizontal drive circuit is switched by the deflection switching circuit and the frequency of the horizontal synchronizing signal is switched from high to low,
4. The semiconductor integrated circuit according to claim 3, wherein the oscillation frequency of the voltage controlled oscillator is switched after the capacitance of the horizontal drive circuit is switched by the deflection switching circuit. 5. A frequency detecting means for detecting a frequency of a horizontal synchronizing signal and generating a switching signal according to the detected frequency, and a PL for oscillating a signal according to the frequency of the horizontal synchronizing signal.
An L circuit and a plurality of oscillation modes provided in the PLL circuit, in which an integer multiple frequency of the horizontal synchronizing signal is divided into a plurality of frequency ranges, and a signal in each of the frequency ranges is oscillated according to a control voltage. And a voltage controlled oscillator whose oscillation mode is switched according to a switching signal output from the frequency detecting means. 6. The voltage controlled oscillator selects an odd number of inverter circuits connected in series and one of the output signals of these inverter circuits according to the switching signal and supplies the selected output signal to the leading inverter circuit. 7. The semiconductor integrated circuit according to claim 1, wherein the inverter circuit includes a transistor whose dimension is switched according to the control voltage. 7. The semiconductor integrated circuit according to claim 6, wherein each of the inverter circuits includes a transistor whose current amount can be switched according to the control voltage. 8. The voltage controlled oscillator comprises an odd number of inverter circuits connected in series, and each of the inverter circuits has a transistor whose dimension can be switched according to the switching signal. The semiconductor integrated circuit described in 1, 2, 3, and 5. 9. The voltage controlled oscillator comprises an odd number of differential amplifier circuits connected in series, and selection means for selecting one of the output signals of these differential amplifier circuits according to the switching signal. When the output signal of the odd-numbered differential amplifier circuit is selected by the selecting means, the non-inverted output signal and the inverted output signal of this differential amplifier circuit are used as the non-inverted input terminal and the inverted input terminal of the leading differential amplifier. When the output signal of the even-numbered differential amplifier is selected, the inverted output signal and the non-inverted output signal of the differential amplifier are supplied to the non-inverted input terminal and the inverted input terminal of the leading differential amplifier, respectively. 6. The semiconductor integrated circuit according to claim 1, 2, 3, or 5, wherein