JPH04186430A - Address forming system for control storage device - Google Patents

Abstract

PURPOSE:To rapidly execute processing within the range of addresses overlappedly held in each mounting unit of a control storage device by constituting the control storage device of plural mounting units and overlappedly holding a prescribed range of addresses in each mounting unit. CONSTITUTION:Each of semiconductor chips 1 to 3 to be plural mounting units is constituted of an address overlapping register 14 for overlappedly holding the prescribed range of addresses and a selector 15 for selecting address data. Data for one word, e.g. address data indicating the succeeding address in control data, are stored in the chip 1 and its partial addresses are overlappedly stored also in the chips 2, 3. In the case of forming addresses within overlapped b bits, the b bits of the overlapped addresses are read out from a RAM 12, selected by the selector 15 and then stored in the register 14. Since the succeeding address is formed in the chip 1 and said operation is executed in the same mounting unit, rapid operation can be executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an address generation method in a control storage device, and particularly in a small-scale information processing device, high-speed operation is possible by partially overlapping address data. This invention relates to a technique that is effective when applied to an address generation method for a control storage device.

[Prior Art] Generally, an information processing device includes at least a control storage device, and reads data (microinstructions) stored in the control storage device to control a device made up of the information processing device.

Further, there is a trend toward faster speeds in such information processing devices, and accordingly, there is a demand for faster speeds in control storage devices as well. For example, one conceivable way to increase the speed of processing is to increase the speed of semiconductor memory, but this is largely due to limitations in the capacity or economics of semiconductor memory.

Further, as described in Japanese Patent Publication No. 56-12903, a processing technique is disclosed in which a predetermined range of a semiconductor memory is made high speed and high speed and low speed are used together. However, even in this combined processing, there is a limit to the demand for higher speed.

As described above, there are various obstacles to increasing the speed of the control storage device, and one of the reasons is the address generation process.

In general, the generation of the address of the control storage device is specified by previously read data, and a loop process is performed in which the read data is stored in an address latch. In this case, the control memory device is generally made of a plurality of mounting boards or semiconductor chips.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, since the next address is generated by loop processing, the delay time of the loop (implementation delay) or the high speed of the read cycle of the control storage device is It may become a factor that hinders the

Furthermore, if the control memory device is made of a plurality of mounting boards or semiconductor chips, there is a large scope for mounting the structure, which naturally limits the reduction of the mounting delay.

Therefore, the problem with the conventional address generation method is that it cannot be well applied to information processing devices that require high speed. In particular, this is a big problem in small-scale information processing devices.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an address generation method for a control storage device that secures a storage range for control data and enables high-speed operation by duplicating address data in a predetermined range.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

That is, the address generation method for a control storage device of the present invention includes a control storage device that stores at least a control instruction,
An address generation method for a control storage device that generates the address of the next control instruction to be read based on the information in the control instruction read from the control storage device, and is configured by the control storage device or multiple implementation units. A predetermined range of addresses is held redundantly for each implementation unit.

In this case, when specifying an address beyond the overlapped range, the reading of the control command is stopped once and the address is transferred between mounting units to specify the address.

Furthermore, when specifying an address beyond the overlapped range, the address of the control instruction immediately before reading the specified address is specified.

[Operation] According to the above-described control storage device address generation method, by duplicating and holding a predetermined range of addresses for each of a plurality of control storage device mounting units, within each control storage device mounting unit, Processing within the address range that is held redundantly can be performed at high speed. This makes it possible to achieve overall speeding up of the control storage device.

In addition, when specifying an address exceeding a predetermined range that is held overlappingly, either stop reading the control command once and transfer the address between implementation units to specify the address, or read the specified address once. By specifying the address of the previous control instruction, sufficient processing speed can be obtained even between each implementation unit. This makes it possible to maintain the conventional processing speed even when generating addresses outside the predetermined range that are rarely specified.

[Embodiment] Fig. 1 is a block diagram showing a control storage device which is an embodiment of the address generation method of the control storage device of the present invention, and Fig. 2 is a block diagram showing one word of control data in the control storage device of this embodiment. FIGS. 3A to 3C are time charts showing operations in this embodiment.

First, the configuration of the control storage device of this embodiment will be explained with reference to FIG.

The control storage device of this embodiment includes three semiconductor chips 1, 2 . ,． For example, the semiconductor chip 1 includes an address register 11 that latches addresses excluding duplicates, a RAM 12 that stores a control program, a data register 13 that stores read data, and It consists of an address duplication register 14 that holds a predetermined range of addresses in duplicate, which is a feature of the invention, and a selector 15 that selects address data, and the semiconductor chip 2.3 has a similar structure.

In the control storage device configured as described above, one word of control data, for example address data indicating the next address of the control data as shown in FIG. 2, is stored in the semiconductor chip l. Some addresses are duplicated and also held in the semiconductor chip 2.3.

In this case, if the number of bits required to address the control memory capacity is C bits, then this is the bit width of the address data, and the number of bits that are held redundantly among C bits is b hint, The remaining bit is C bit.

Next, the operation of this embodiment will be explained based on FIG. 3.

First, when an address is generated in the b pit of the overlapped portion, the b bit of the overlapped address is read out from the RAM 12 and selected by the selector 15, as shown in FIG. 3(a).
After being selected, the address is stored in the address duplication register 14.

As a result, the next address is generated within the semiconductor chip 1, and this operation is performed within the same packaging unit, making high-speed operation possible. Further, this processing is similarly performed at high speed within the semiconductor chip 2.3 which is another packaging unit.

On the other hand, when addressing a range larger than the overlapping b bits, address data is sent from the data register 13 to each of the other semiconductor chips 2 and 3, the a bits are stored in the address register 11, and the b bits are is stored in the address duplication register 14 via the selector 15.

For example, as shown in Fig. 3 fb), there is a method in which reading is stopped once and addresses are transferred between semiconductor chips 1 to 3 to designate the address, that is, to generate the address for two cycles. Although it requires more time than processing within the semiconductor chips 1 to 3, it is particularly effective in input/output processing where the number of bits can be saved.

Furthermore, as shown in FIG. 3(C), the method of preparing a bit worth of addresses in the address register 11 from the previous read data enables faster processing than 2-cycle processing, so the instruction processing It is especially effective.

In this way, when the next address is generated outside the predetermined range, the data flow is changed to each semiconductor chip 1 to 3.
Although this increases the mounting delay and delays it compared to the processing speed within the semiconductor chips 1 to 3, this operation only occurs when the capacity for b bits is exceeded, and therefore the speed is reduced. The reduction is almost negligible.

Therefore, according to the control storage device of this embodiment, by providing the address duplication register 14 in addition to the conventional address register 11, it is possible to hold a predetermined range of addresses redundantly in each semiconductor chip 1 to 3. , processing within the address range can be performed at high speed.

Also, when specifying an address that exceeds the specified range,
Since the frequency of specification is low, it is possible to ignore it, so the conventional processing speed can be maintained.

Above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. Not even.

For example, with regard to the control storage device of this embodiment, the case where three semiconductor chips 1,2°3 are mounted as a plurality of mounting units has been described, but the present invention is not limited to the above embodiment. It is widely applicable, for example, to cases where two, four or more semiconductor chips are mounted, or when a mounting board or a mounting unit is used instead of a semiconductor chip.

Further, the number of overlapping bits in FIG. 2 is desirably set within a predetermined range in consideration of the required processing speed, data area, etc.

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly explained below.

(1) The control storage device is configured with multiple implementation units, and by overlappingly retaining a predetermined range of addresses for each of these implementation units, it is possible to maintain redundant addresses within each implementation unit of the control storage device. Since processing within the specified address range can be performed at high speed, the overall speed of the control storage device can be increased.

(2) When specifying an address exceeding a predetermined range that is held in duplicate, stop reading the control command once and transfer the address between implementation units to specify the address, or read the specified address. By specifying the address of the previous control instruction, sufficient processing speed can be obtained even between each implementation unit, so the conventional processing speed can be maintained even when generating addresses outside the predetermined range, which are rarely specified. I can do it.

(3) According to (1) and (2) above, the storage range of control data is secured by duplication of address data only within a predetermined range, and sufficient high-speed operation is possible, especially for small-scale information processing equipment. It is possible to obtain a control storage address generation scheme that is well applicable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a control storage device which is an embodiment of the address generation method of the control storage device of the present invention, and FIG. 2 shows one word of control data in the control storage device of this practical example. 3 (al to (C) are time charts showing the operation of this embodiment. 1 to 3...Semiconductor chip (mounting unit), 11...Address register, I2...・RAM, 13...Data register, 14...Address duplication register, 15...
·selector. Agent Patent Attorney Daiwa Tsutsui

Claims (1)

[Claims] 1. Control that includes a control storage device that stores at least a control instruction, and generates the address of the control instruction to be read next based on information in the control instruction read from the control storage device. An address generation method for a storage device, wherein the control storage device is constituted by a plurality of mounting units, and each mounting unit holds a predetermined range of addresses in duplicate. method. 2. When specifying an address beyond the overlapped range, the reading of the control command is stopped once, and the address is transferred between the mounting units to specify the address. 1. Address generation method of control storage device according to 1. 3. Address generation for the control storage device according to claim 1, characterized in that when specifying an address beyond the overlapped range, the address of a control instruction immediately before reading the specified address is specified. method.