JPH04138554A - Parallel type digital signal processor - Google Patents

Abstract

PURPOSE:To shorten a time required for data transfer and to simplify the control of a CPU by storing data in the same address as that of a digital signal processor(DSP) for sending data in a specific storage means in the case of transferring data between plural DSPs. CONSTITUTION:In the case of transferring data f a DSP 12n to a DSP 121, the arithmetic result D of the DSP 12n is supplied to a data bus 20 and stored in the identical addresses #4 of memories 141 to 14n in all the DSPs 121 to 12n. Since the same data are stored in the identical addresses of the memories in all the DSPs at the time of transferring the data, a data storage which is an essential element for a convensional device can be made unnecessary, an access speed can be improved because of the omission of the data storage and an effect equivalent to the formation of data cache memories in respective DSPs can be obtained. Thus, rapid data transfer is attained and control based upon the CPU is easily executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to multiple digital signal processing processors connected in parallel when executing a very long program or performing a huge amount of calculation. The present invention relates to a parallel digital signal processing device that can process data at high speed by sharing tasks.

[Conventional technology]

FIG. 3 is a block diagram of an example of a conventional parallel digital signal processing device. In the same figure, the central processing bag! (Hereinafter, also referred to as CPU.) 40 is a digital signal processing processor (hereinafter also referred to as DSP), which may consist of a single CPIJ or multiple CPUs.
) 42+ to 42 are the data bus 44 and the command bus 46
is connected in parallel with the CPU 40. Furthermore,
Connected to the data bus 44 is a data store 48 that temporarily stores data to be transferred.

DSP42+~42. has an internal decoder memory and an arithmetic circuit, and is connected to the CPU 40 through an instruction bus 46.
C, which decodes the instructions supplied from the C and performs arithmetic processing on the data sent through the data bus 44.
The word length of the instruction word issued from the PU 40 is equal to the sum of the word lengths of the instruction words supplied to each DSP, that is, the word length of the instruction for the DSP 42+ is n+,
Assuming that the word length of the instruction for the DSP 42 is n, the word length N of the instruction supplied from the CPU 40 is N-Σn.

By configuring the instructions supplied from the CPU 40 to all DSPs in a single word, high-speed processing becomes possible.

When transferring data from the CPU 40 to each DSP, it is done via the data store 48. For example, when transferring certain data from the CPU 40 to the DSP 42+, the CPU 4
0 provides its data onto data bus 44 for temporary storage in data store 48. Next, DSP 42. , accesses the data store 48 and transfers this data from the data store 48 to the DSP 42 . through the instruction bus. At this time, if necessary, use other DSPs.
However, it is also possible to construct a one-word instruction issued from the CPU 40 to perform different operations at the same time. CPU4
The same applies when data is transferred from DSP 0 to another DSP.

Data transfer between DSPs is also performed via the data store 48. For example, DSP 42. When another DSP 42z needs the data obtained by the arithmetic processing, the CPU 40 first sends the data to the DSP 42+ through the data bus 44 to the data store 48.
order it to be memorized. Thereafter, the DSP 42□ is commanded to access the data store 48 and read this data from the data store 48. In this way, data is transferred from the DSP 42+ to the DSP 42z.

[Problem to be solved by the invention]

In conventional parallel digital signal processing devices, data must be transferred via a data store, so the data store is an essential component of the device. Also, data is transferred from the CPU to the DS via this data store.
There is a problem in that it takes time until the data is transferred to P and between DSPs. Furthermore, when the CPU controls the DSP, it is also necessary to control the data store at the same time, so there is a problem that the control operation by the CPU becomes complicated.

The present invention has been made based on the above circumstances, and it is an object of the present invention to provide a parallel digital signal processing device that can shorten the time required for data transfer and simplify control by a CPU.

[Means to solve the problem]

To achieve the above object, the present invention connects a central processing unit and a plurality of digital signal processing processors each having internal storage means through a data bus and an instruction bus,
In a parallel digital signal processing device in which data is processed in parallel by the plurality of digital signal processing processors based on instructions from the central processing unit, when data is transferred from the central processing unit to a specific digital signal processing processor, all In all digital signal processing processors other than the digital signal processing processor that stores data at the same address of the storage means in the digital signal processing processor and sends the data when transferring data between digital signal processing processors. The data is stored in the storage means at the same address as the digital signal processing processor that sends the data.

[Effect]

According to the above configuration, the present invention provides a central processing unit <cPU).
When data is transferred from a digital signal processor (DSP) to a specific digital signal processor (DSP) that performs a desired operation, the data is stored at the same address in the storage means inside all the DSPs. Each DSP performs preset arithmetic processing on this same data, but the specific DS
By returning only the data processed by P to the CPU, a desired calculation result can be obtained. This allows CPU usage without using a data store.
Data can be transferred between the DSP and the DSP.

Also, when transferring data from one DSP to another, all DSPs other than the DSP sending the data
The data is stored in the same address as the DSP that sends the data in the storage means. Each DSP performs preset arithmetic processing on the same data, but by using data processed and obtained by the other DSPs, desired arithmetic results can be obtained.

This allows data to be transferred between DSPs without using a data store.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Figure 1 is a block diagram of a parallel digital signal processing device that is an embodiment of the present invention, and Figure 2 (a) is a block diagram of each DSP.
Figure (b) schematically showing the contents of the internal memory of
is a timing chart showing the internal state of the data bus and DSP.

In FIG. 1, CPU10 has m DSPI21 to 1
2. It is used to control arithmetic processing, data transfer between the CPU and DSP, and data transfer between DSPs, and may consist of a single CPU or multiple CPUs. DSP 121~
12. has internal memory (storage means) 141-1
4. , a decoder 16 that decodes instructions from the CPU.
~161, and arithmetic circuit 18. ~18. have.

These DSP121-12. are provided in parallel to CPU10, and are connected to CPU1. by data bus 20 and instruction bus 22. It is connected to O. Note that CPU10 and DSP12. ~12. is available as a single chip. This is similar to the conventional device in that the length of the instruction word issued from CPU10 is equal to the sum of the word lengths of the instruction words supplied to each DSP.

As an example, CPU10 to DSP12. The operation when transferring the initial data AlB and C to the computer will be explained. First, cpuio has a period t as shown in FIG. 2(b).
1, data A is supplied to the data bus 20. Then, as shown in Figure 2(a), this data is distributed to all DSs.
Memory 14 inside P. ~14. 0th period stored in the same address #0 of period 1. Data B is supplied to the data bus 20 at the same address #1 of all memories.
is memorized. Similarly, data C is stored at the same address #2 in all memories during period t.

When the data transfer is completed, each DSP performs calculations on the transferred data during period t#.

This calculation is performed by the calculation circuits 181 to 18° inside the DSP, but the contents of the calculation generally differ depending on each DSP.For example, in the DSP 121, the data stored at address #0 and the data stored at address #1 are The sum is calculated, and the DSP 12□ calculates the sum of the data stored in address #0 and the data stored in address #2.
..., the DSP 12m calculates the product of the data stored at address #0 and the data stored at address #1,
The contents of calculation are set in advance for each DSP. Therefore, the results obtained by these operations also differ depending on the DSP, and the respective operation results d, to d, are stored in the memory 14. ~14. is stored at address #3.

Next, for example, the DSP12. is DSP12. DSP when the calculation result of 12. From DSP12. We will explain the data transfer to. At this time also, Fig. 2(b)
During the period t, the calculation results of the DSP 12 are supplied to the data bus 20, and are sent to all the internal memories 14. ~14° at the same address #4. This allows the DSP 12. can utilize the calculation results of the DSPI 211. from another DSP
The same applies to the case of transferring data to the SP.

In this way, by storing the same data at the same address in the internal memory of all DSPs during data transfer, the data store, which was an essential component in conventional devices, is no longer required, and data transfer via the data store is no longer necessary. In addition, the access speed is increased by the fact that there is no data cache memory, and it is similar to providing a data cache memory isometrically inside each DSP. In addition, control of data transfer is greatly simplified, so the CPU
10, and the memory 141 to 14.10 inside the DSP can be reduced. By using multi-ports, data transfer between DSPs can be speeded up. Furthermore, as long as the CPU I/O knows what data is stored in which DSP, there is no need to return data to the CPU each time data is transferred.

The parallel digital signal processing circuit of this embodiment is, for example, D
By connecting the SP as a sub-processor for numerical calculations to the CPU to perform matrix data processing, it is possible to significantly reduce the time required to perform large amounts of calculations.

As described above, in this embodiment, data must be stored in the memory of the DSP that does not require the data during data transfer, so an additional storage area is used. However, the memories 141 to 14 inside the DSP. If the capacity of 256 bits is a general value, even if up to half of this is used for temporary storage during data transfer as described above, there is no need to worry about running out of storage space. First of all, it can perform quite complex calculations.

If the storage area is insufficient, the processing can be further divided and performed by the CPU10.

【Effect of the invention〕

As explained above, according to the present invention, there is no need for a data store for temporary storage, which was required in conventional devices.
Since the time required to go through the data store can be reduced, data transfer can be performed at high speed, and since there is no need to use a data store, it is easier for the CPU to control data transfer between memories. , C.P.
It is an object of the present invention to provide a parallel digital signal processing device that can reduce the burden on U, and therefore can process in a short time complex and huge amounts of calculations that conventionally took a long time to process. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a parallel digital signal processing device according to the present invention, FIG. 2(a) is a diagram showing the contents of the memory provided inside each DSP, and FIG. A flowchart showing the operational status of the data bus and the internal DSP;
FIG. 3 is a block diagram of an example of a conventional parallel digital signal processing device. 10...Central processing unit (CPU), 12+ -12
,...Digital signal processing processor (DSP)
), 14, ~14. ...Memory, 16, ~16. ...decoders 181-18. ...Arithmetic circuit, 20...Data bus, 22...Instruction bus. Figure 3

Claims (1)

[Scope of Claims] A central processing unit and a plurality of digital signal processing processors each having an internal storage means are connected by a data bus and an instruction bus, and the processing is performed by the plurality of digital signal processing processors based on instructions from the central processing unit. In a parallel digital signal processing device that performs parallel processing of data, when data is transferred from the central processing unit to a specific digital signal processing processor, the data is stored at the same address of the storage means in all digital signal processing processors. , when transferring data between digital signal processing processors, the storage means in all digital signal processing processors other than the digital signal processing processor sending the data are stored at the same address as the digital signal processing processor sending the data. A parallel digital signal processing device characterized by storing data.