JPH04127227A - Memory control system - Google Patents

Abstract

PURPOSE:To increase the processing speed of a memory control system by processing sequentially a storage means consisting of plural memory blocks for which the individual accesses are available through a 1st processing means and then processing successively the memory blocks processed by a 1st processing means at every block. CONSTITUTION:The 1st and 2nd devices 2 and 4 connected to the magnetic disks 1 and 3 respectively are connected to a RAM 6 via a bus switching circuit 5. The RAM 6 includes the memory blocks #1 - #4 connected with bus lines. Thus, the individual accesses are available to those blocks. The device 2 processes the memory blocks accessed by a 1st access means at every block. The device 4 processes the memory blocks receiving the successive accesses at every block. Thus, both devices 2 and 4 can process the memory blocks at one time and the processing speed is increased in a memory control system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control system having a storage device consisting of a plurality of individually accessible memory blocks.

〔overview〕

In the present invention, the first processing means sequentially processes the memory blocks that are accessed in a predetermined order block by block in the storage means consisting of a plurality of individually accessible memory blocks, and the second processing means sequentially processes the memory blocks accessed in a predetermined order. The memory blocks that have been processed by the first processing means are sequentially processed block by block.

[Conventional technology]

Conventionally, as shown in FIG. 5, in addition to the CPU 10, a DMA
A (Direct Memory Access) controller 20 is provided, and under the control of this DMA controller 20, data is transferred directly between the magnetic disk 40 and the RAM 30b without going through the CPU 10.
0 implements a data processing device that speeds up data processing by executing processing for data transfer, for example, processing for data in the RAM 30a.

That is, in this data processing device, the CPU 10
All you need to do is specify the data to be transmitted and instruct the MA controller 20 to read/write the data to the RAM 30b.
Data transfer by the A controller 20 is performed in parallel. Note that the disk control device 50 in FIG.
Access control to the magnetic disk 40 is performed under the control of the controller 20.

[Problem to be solved by the invention]

However, conventionally, for example, when a specified file on the magnetic disk 40 is expanded to the RAM 30b and records are updated on the RAM 30b, until all records of the specified file on the magnetic disk 40 are expanded to the RAM 30b,
CPU10 was unable to execute record update processing on RAM 30b.

This is due to the fact that all records of the specified file are always considered to be processed by the CPU 10, as in the case of a file search, for example.

However, for example, data update processing can be performed directly on read records without reading all records to the RAM 30b, such as adding a predetermined numerical value sequentially to the numerical data of a predetermined item of all records. In many cases, this can be done.

An object of the present invention is to enable a second device to access a storage device even while a first device is continuously accessing the storage device.

[Means to solve the problem]

The means of this invention are as follows.

Storage means (corresponding to the RAM 6 in the embodiment) consisting of a plurality of memory blocks that can be accessed individually; and first and second processing means (the first device 2 and the second device in the embodiment) that individually perform operation processing. 4), and a first access means (corresponding to 4) that sequentially accesses each of the memory blocks in a predetermined order under the control of the first processing means.
This corresponds to the processing step A in the bus switching circuit 5 and the first device 2 in the embodiment. ), and a second access means (the bus switching circuit 5 of the embodiment and the second Processing steps B and B in device 4
Corresponds to 2. ).

[For production]

The operation of the means of this invention is as follows.

When each memory block of the storage means is accessed in a predetermined order by the first access means, the first processing means
The memory block accessed by the first access means is processed block by block.

On the other hand, the second access means accesses the memory block that has been accessed by the first access means, and accordingly, the second processing means processes the sequentially accessed memory blocks block by block. Execute.

Therefore, each memory block of the storage means can be accessed individually by the first processing means and the second processing means, and parallel processing by the first processing means and the second processing means is possible. You can measure the overall speed of processing.

〔Example〕

Hereinafter, one embodiment will be described with reference to FIGS. 1 to 4.

FIG. 1 is a block diagram of a memory control system according to an embodiment of the present invention.

This memory control system includes a first device 2 connected to a magnetic disk 1 for storing transaction/yon files, etc., and a second device 2 connected to a magnetic disk 3 for storing mask files, etc. 4, and this device 2.4 is connected via a bus switching circuit 5 to a RAM 6 including a plurality of memory blocks. The devices 2.4 are also commonly connected to a pointer memory 7 that stores various pointers. here,
The first device 2 accesses one memory block in RAMe specified by the first pointer P4 of the pointer memory 7, and updates the data in the corresponding memory block with the data of the transaction file stored on the disk 1. It has the function to The second device 4 also has a function of accessing one memory block in RAMe specified by the second pointer P2 of the pointer memory 7, reading data from the accessed memory block, and transferring it to the disk 3. ing.

As can be seen from FIG. 1, the RAM 6 includes four memory blocks #1, #2, #3, and #4, and each memory block has a path line (control path line, data bus line). ) are connected,
They can be accessed individually. In other words, each memory block can function as an independent memory, but the addresses of each memory block are continuous, and the address areas in each memory block are sequentially arranged starting from memory block #1 (00000 to 3). F F F F) address, (40000~7FFFF) address, (80000~
BFFFF) address and (COOOO~FFFFF) address. Therefore, each memory block can store continuous data spanning the same number of memory blocks, and each memory block can be regarded as one memory.

When the first device 2 specifies a memory block corresponding to the first pointer P, the bus switching circuit 5 switches and connects the path line of the specified memory block to the path line of the first device 2. The second device 4 points to the second pointer P.
When a memory block corresponding to No. 2 is specified, the path line of this specified memory block and the path line of the second device 4 are switched and connected.

FIG. 2 shows a detailed block diagram of the bus switching circuit 5. As shown in FIG.

Pass lines from each memory block #1 to #4 are connected to selectors 51 to 54 provided corresponding to each memory block.
A pass line from the first device 2 and a pass line from the second device 4 are connected to the other side of the selectors 51 to 54 in a switchable manner. The memory block designation signal P from the first device 2 is input to the decoder 55, which decodes the value of the designation signal P1 and outputs the acknowledge signals p, , s-z p ,
Outputs any one of the four acknowledge signals. On the other hand, the memory block designation signal P2 from the second device 4
is input to the decoder 56, which decodes the value of the designated signal P2 and outputs the acknowledge signal P21.
-P24 is output. When the selector 51 receives the acknowledge signals P and □ from the decoder 55, it connects the pass line from the memory block designation to the pass line from the first device 2, and
Memory access to memory block #1 is enabled from the first device 2. In addition, the selector 51 is connected to a decoder 56.
When the acknowledge signal P2+ from the memory block #1 is input, the pass line from the memory block #1 is connected to the pass line from the second device 4, thereby enabling memory access from the second device 4 to the memory block #1.

The other selectors 52 to 54 also function in exactly the same way as the selector 51.

Next, an example of the operation will be explained.

As an example, the contents of the mask file stored across each memory block of the RAM 6 are updated by a transaction file in the disk 1 connected to the first device 2, and the contents of the master file in the updated RAMe are updated. An example in which the data is transferred and stored on the disk 3 connected to the second device 4 will be explained.

FIG. 3 is a flowchart showing the processing of the first device 2 in the above operation.

Here, it is assumed that the values of the first pointer P and the second pointer P2 are both set to 1" in the pointer memory 7, and in this state, the first device 2 starts the processing according to FIG. First, specify the memory block corresponding to the first pointer P1 (step A).That is, read the value of the first pointer P□ from the pointer memory 7, and input this value to the decoder 55 of the bus switching circuit 5. Then, the decoder 55 outputs the value of the first pointer P, in this case “
1” is decoded to generate an acknowledge signal p.

is supplied to the selector 51. Therefore, selector 51
connects the pass line from memory block #1 to the pass line from first device 2. Next, the process proceeds to step A2, where all data in the designated memory block is updated. That is, the first device 2 accesses memory block #1 connected to the bus, and accesses this memory block #1.
The data in the transaction file #1 is sequentially read out, the data is updated based on the data in the transaction file on the disk 1, and the updated data is written again to the memory block #1. When all data in the specified memory block has been updated in this way,
Proceeding to step A3, check whether the first pointer P1 is the end pointer, that is, the value "" that specifies the final memory block #4.
4''. If No, the process proceeds to step A4, where the first pointer P1 of the pointer memory 7 is incremented, that is, the operation (P□+1→P,) is performed, and the incremented pointer P1 is incremented. Write the first pointer P1 to the pointer memory 7. After step A4, step A1
Return to In this case, the 1st pointer P is at Ste Knob A4.
, is incremented to "2", and in step A, the second memory processor.

#2 is now specified. Thereafter, similar processing is repeated, and when it is determined in step A3 that the pointer is the pointer specifying either the first pointer P1 or the final memory block #4, all processing ends.

That is, the first device 2 sequentially accesses memory block #1 to memory block #4 and updates the data using the transaction file stored on the disk 1.

FIG. 4 is a flowchart showing the processing of the second device 4. First, in step B1, it is determined whether the second pointer P2 in the pointer memory 7 is smaller than the first pointer P1. This step B is repeated until the second pointer P2 becomes smaller than the first pointer P, that is, until the data of the memory block is updated in the first device 2 and the first pointer P is incremented. If it is determined that the second pointer P2 is smaller than the first pointer P1, the process proceeds to step B2, and the memory block corresponding to the second pointer P2 is specified. That is,
The value of the second pointer P2 is read from the pointer memory 7, and this value is input to the decoder 56 of the bus switching circuit 5.

Then, the decoder 56 decodes the value of the second pointer P2, in this case "1", and supplies an acknowledge signal P2+ to the selector 51. Therefore, the selector 51 connects the pass line from memory block #1 to the NOHAS line from the second device 4. Next, the process advances to step B3, where the designated memory block is accessed, and all data in this memory block is sequentially read out and transferred to the disk 3.

When the data transfer in the designated memory block is completed in this way, the process proceeds to step B4, where it is determined whether or not the second pointer P2 is the end pointer, that is, whether it is the value "4" that designates the final memory block #4. If NO, the process proceeds to step B5, where the second pointer P2 in the pointer memory 7 is incremented.

That is, when the second device 4 specifies a memory block, it checks whether the data of the specified memory block has been updated by the first device 2, and sequentially accesses the updated memory blocks to check the data contents. Transfer to disk 3.

In this way, when the first device 2 updates the data in the RAM 6 and the second device transfers the updated data, the first device 2 and the second device 4 can access each memory block individually. Therefore, the RAM by the first device 2
Even before all the data in e has been updated, when looking at the RAM 8 block by block, if there is a memory block that has already been updated, the second device 4 can access this memory block. . That is, simultaneous processing by the first device 2 and the second device 4 is possible, and processing speed can be increased.

〔Effect of the invention〕

According to this invention, access and processing to the storage device can be performed in parallel by the first processing means and the second processing means, making it possible to speed up the processing.

Furthermore, when each memory block is processed by the second processing means, the condition is that the memory block has already been processed by the first processing means, so that the processing of the first processing means is not completed. Processing of the memory block by the second processing means can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment to which this invention is applied;
Figure 2 is a detailed block diagram of the bus switching circuit, and Figure 3 is a detailed block diagram of the bus switching circuit.
FIG. 4 is a flowchart showing the processing of the device, FIG. 4 is a flowchart showing the processing of the second device, and FIG. 5 is a diagram for explaining the prior art. 2......First device, 4......
Second device, 5... Bus switching circuit, 6...
......RAM, 7...Pointer memory, 51-54...Selector, 55
．． 56...Decoder. Patent applicant Casio Computer Co., Ltd. Figure 2 Figure 3 Figure 4 145@

Claims (1)

[Scope of Claims] A memory control system having storage means consisting of a plurality of individually accessible memory blocks, comprising: first and second processing means that individually perform operation processing; and a first processing means under the control of the first processing means. a first access means that sequentially accesses each of the memory blocks in a predetermined order; and a first access means that sequentially accesses the memory blocks that have been accessed by the first access means under the control of the second processing means. A memory control system comprising: a second access means for accessing the memory;