JPH0418641A - Error processing system - Google Patents

Abstract

PURPOSE:To easily and efficiently execute an error processing by providing an instruction order register to store the order of instructions on an instruction train under execution by an instruction execution part, and a processing stop means to stop the processing only of the instruction execution part generating error. CONSTITUTION:An instruction processing part 4 is equipped with the instruction order register. When the error is generated in an instruction execution part 1, as the processing stop means, a clock control circuit 40 stops the processing only of the instruction execution part 1. Then, other instruction execution parts 0 and 2 wait for the error processing until completing the instruction execution. Next, when the instruction execution is completed, the contents of the instruction order register are cleared, and all the instruction execution parts 0-2 are turned to an instruction execution standby state. With this state as a condition, the error processing is started by a service processor 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error handling method in a data processing device that can simultaneously execute multiple instructions.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of a conventional data processing device. In FIG. 4, 0 to 2 are instruction execution units that execute instructions, 4 is an instruction processing unit that performs processing for executing instructions in instruction execution units O to 2, and 5 is instruction processing unit 4 and instruction execution unit 0. 2, 6 is a service processor that controls error processing, etc., 7 is an error launch circuit that holds error reports of instruction execution units O to 2, and 8 is a clock for instruction execution units 0 to 2. 9 is an AND gate for stopping, 9 is an OR gate for collecting error reports, 10 is a clock input line, 12 is an error report line to the service processor 6, 14
~16 are instruction execution completion report lines from the instruction execution unit θ~2 to the instruction processing unit 4, 17 to 19 are error report lines from the instruction execution units 0 to 2, and 20 is a clock supply to the instruction execution unit O~2. Lines 34-36 are instruction start signal lines from the instruction processing section 4 to the instruction execution sections 0-2.

FIG. 5 is a block diagram showing the configuration of the instruction processing section 4 in FIG. 4. In FIG. 5, 23 is an instruction buffer, 24
25 is an instruction decoder, 25 is an instruction queue that holds the decoded result until the start of instruction execution, and 26 is an instruction execution unit which receives the instruction execution completion report lines 14 to 16 from the instruction execution units O to 2 and selects the next instruction to be executed. 27 is an instruction start control unit that receives the result of the execution order determination circuit 26 and sends an instruction start signal to the instruction execution unit that is to execute the instruction; This is a ready signal line that reports the completion of instruction execution preparation.

Next, the operation of this conventional example will be explained. Instruction processing unit 1
The instruction decoder 24 processes the instructions in the instruction buffer 23, generates data necessary for instruction execution in the instruction execution units 0 to 2, and stores the data in the instruction queue 25. The instruction processing unit 4 also performs advance fetching of operand data necessary for instruction execution.

The instruction queue 25 waits for the completion of the operand fetch, excites the ready signal 33, and sends data for instruction execution to the deku bus 5. At this time, the poor hitting order determining circuit 26 outputs the command execution completion report line 14 of the command execution units 0 to 2.
The instruction execution unit to which the instruction execution is to be assigned is selected from the states 16 to 16, and the result is reported to the instruction start control unit 27. The instruction start control unit 27 sends an instruction start signal to one instruction execution unit that is to execute the instruction based on the ready signal on the ready signal line 33 from the instruction queue 25 and the result of the instruction order determining circuit 26. The instruction execution unit that receives this instruction start signal takes in the data on the data bus 5 and starts executing the instruction.

Now, consider a case where an error occurs in the instruction execution unit 1. In this case, the instruction execution unit 1 activates the error report line 18 and sets the error latch circuit 7. Since the error latch circuit 7 is set, a clock stop signal is applied to the AND gate 8 by the OR gate 1-9, and the clock on the clock supply line 20 is stopped. As a result, all instruction execution units O-2 are stopped. The clock stop signal from OR gate 9 is sent to error report line 1 to service processor 6.
2, and the service processor 6 starts error processing.

[Problem to be solved by the invention]

Conventional data processing devices are configured as described above, so when an error occurs, instruction execution in all instruction execution sections must be interrupted, resulting in the problem of wasting processing unrelated to the error. In addition, since an instruction address that is not directly related to the error is reported to the software, the instruction that caused the error cannot be identified, making the recovery process complicated.

This invention was made to solve the above-mentioned problems, and it is possible to correctly complete instruction processing that is not directly related to the error, retry only the instruction that caused the error, and prevent the occurrence of the error from occurring. It is an object of the present invention to obtain an error processing method that can complete instruction processing up to a point in time and facilitate and improve the efficiency of error processing on software.

[Means to solve the problem]

The error processing method according to the present invention includes each instruction execution unit 0 to 2.
an instruction order register 28 that stores the execution order of the instructions being executed in the instruction sequence; and a processing stop means (clock control circuit 40) that independently stops processing only the instruction execution section when an error occurs in the instruction execution section. ), when an error occurs in a certain instruction execution section, the processing of only the instruction execution section is stopped by the processing stop means, and the error processing is waited until the other instruction execution sections complete execution of the instruction being executed, When the instruction execution is completed, the instruction order register 2 is
This is characterized in that the service processor 6 starts error processing under the condition that the contents of 8 are cleared and all instruction execution units 0 to 2 are in the instruction execution waiting state.

(Operation) For example, when an error occurs in the instruction execution unit 1, the processing stop means (clock control circuit 40) stops processing only that instruction execution unit 1.The other instruction execution units 0.2 complete instruction execution. The error processing is started by the service processor 6 under the condition that the contents of the instruction order register 28 are cleared and all instruction execution units 0 to 2 are in the instruction execution waiting state. Ru.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a data processing device employing an error processing method according to an embodiment of the present invention.

In FIG. 1, components corresponding to those shown in FIG. 4 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 1, 8a, 8b.

8c is an AND gate for independently stopping the clock signal supplied to each instruction execution unit 0, 1.2, and 40 is an ANDN.
A clock control circuit 11 as a processing stop means having O gates 3b, 13c and an error latch circuit 7 reports error information of each instruction execution unit O to 2 held in the error launch circuit 7 to the instruction processing unit 4. An error report line 13 is an all-instruction completion report line from the instruction processing unit 4 to the service processor 6.

FIG. 2 is a block diagram showing the configuration of the instruction processing section 4 in FIG. 1. In FIG. 2, components corresponding to those shown in FIG. 5 are given the same reference numerals, and their explanations will be omitted. In FIG. 2, reference numeral 28 denotes an instruction order register that stores the order of instructions being executed by the instruction execution units 0 to 2 on the instruction string;
9 is an OR gate that summarizes the contents of the error report line 11;
30 is a ready inhibit signal line for inhibiting ready control of the instruction queue 25 by the output of the OR gate 29;
32 is a NOR gate that generates a completion condition for instruction execution in all instruction execution units O-2 from the busy state of the instruction order register 28; 32 is a busy signal 37- of the instruction order register 28;
This is an AND gate for inhibiting the instruction execution part in which an error has occurred among the 39 instructions.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 to 3. FIG. 3 is a timing chart showing a case where the instruction execution unit 0 (EXO) executes the first instruction and the instruction execution unit 1 (EXI) executes the second instruction. When the instruction processing unit 4 completes preparation of the instruction to be executed in the instruction queue (Q) 25, the ready signal RDY on the ready signal line 33 becomes logic "1". At this point, both the instruction execution unit O and the instruction execution unit 1 are executing the previous instruction, so neither the first instruction nor the second instruction is executed immediately, and the ready signal RDY changes to logic “1”. ” remains. Thereafter, when the instruction execution of the instruction execution unit 0 is completed and the signal E of the instruction execution completion report line 14 becomes logic “1”, the execution order determining circuit 26 selects the instruction execution unit 0, and the instruction start control unit 27 selects the instruction execution unit 0. Instruction start signal line 34 to instruction execution unit 0
is excited. This situation is illustrated by the movement of the signal S on the instruction start signal line 34 to the instruction execution unit 0 in FIG.

As a result, the instruction execution unit 0 starts executing the instruction again, lowers the signal E on the instruction execution completion report line 14 to logic "0", and sets the ready signal RDY to logic "0". Also,
At this timing, the instruction execution section 0 of the instruction order register 28
The corresponding value changes from m to 1, indicating that the instruction execution unit O is executing the first instruction in the instruction sequence.

Subsequently, the instruction execution section 1 completes the instruction execution and sets the signal E of the instruction execution completion report line 15 to logic "1", but at this point, the instruction queue 25 of the instruction processing section 4 is not ready with the instruction. , the instruction execution unit 1 enters a wait state while keeping the instruction execution completion report line 15 activated. At this time, instruction order register 2
The portion corresponding to the instruction execution unit 1 of 8 is reset from n to 0.

Then, at clock timing C8, ready signal RDY
When becomes logic "1", the instruction execution unit 1 starts executing the instruction, 2 is set in the corresponding part of the instruction execution unit 1 in the instruction order register 28, and the second instruction in the instruction sequence is executed. Show that there is. At this point, the instruction execution unit 0 is executing the first instruction and the instruction execution unit 1 is executing the second instruction in parallel.

Next, a case where an error occurs in the instruction execution unit 1 in this state will be described. Clock timing C14 in Figure 3
When the instruction execution section 1 detects an error and sets the error signal ER of the error report line 18 to logic "1," the error latch circuit 7 is set, and the clock supply line to the instruction execution section 1 is set by the AND game 8b. The clock signal on 21 is stopped. Further, by resetting the ready signal RDY from the instruction queue 25 using the ready inhibition signal vA30, the instruction execution unit 1 is inhibited from starting execution of the next instruction. Even in this state, the clock signal to the instruction execution section O does not stop, and the instruction execution section 0 waits for completion of instruction execution. When the instruction execution unit 0 completes instruction execution at clock timing C19 in FIG. to go into.

Further, the corresponding portion of the instruction execution unit 0 in the instruction order register 28 is also reset to O. At this point, the corresponding part of the instruction execution unit 1 in the instruction order register 28 is 2, but the busy signal is changed to logic "0" by the AND gate 32 and the error report line 11 from the error launch circuit 7. Become. Therefore, all busy signals from instruction order register 28 will be a logic ``0'' and NOR gate 31 will cause the full instruction completion report line 13 to be energized to a logic ``1''. This excited signal and the signal on the error report line 12 cause the service processor 6 to start error processing.

According to the above embodiment, the instruction order register 28 stops new registration when an error occurs in any instruction execution unit, suppresses the bus signal corresponding to the instruction execution unit, and controls other normal instruction execution units. Each time execution of an instruction is completed, a busy signal corresponding to the instruction execution unit is reset. As a result, the service processor 6 detects the completion of instruction execution in all instruction execution units O-2, and starts error handling.

〔Effect of the invention〕

As described above, according to the present invention, when an error occurs in a certain instruction execution unit, only that instruction execution unit is stopped,
Error processing waits until other instruction execution units complete execution of the instruction being executed, and when the execution of that instruction is completed, the contents of the instruction order register are cleared and error processing is performed under the condition that all instruction execution units are in the instruction execution waiting state. As a result, the instruction in which the error occurred can be easily identified, and the execution of normal instructions is not wasted, making it easier and more efficient to handle errors in software. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of a data processing device that employs an error recovery processing method according to an embodiment of the present invention, FIG. 2 is a block diagram of the configuration of the instruction processing section in FIG. 1, and FIG. FIG. 4 is a block diagram showing the structure of a conventional data processing device, and FIG. 5 is a block diagram showing the structure of the instruction processing section in FIG. 4. 0-2...Instruction execution unit, 4...Instruction processing unit, 6...
- Service processor, 28... instruction order register,
40... Clock control circuit (processing stop means).

Claims (1)

[Claims] In a data processing device that has multiple instruction execution units and can simultaneously execute multiple instructions that can be executed regardless of the order of execution on consecutive instruction sequences, the instructions on the instruction sequence that each instruction execution unit is executing an instruction order register that stores the execution order;
A processing stop means for independently stopping processing of only the instruction execution section when an error occurs in a certain instruction execution section is provided, and when an error occurs in a certain instruction execution section, the processing of only the instruction execution section is stopped by the processing stop means. , the error handling waits until the other instruction execution units complete the execution of the instruction being executed, and when the execution of that instruction is completed, the contents of the above instruction order register are cleared and all instruction execution units are in the instruction execution waiting state. An error handling method characterized in that a service processor starts error handling.