JPH04178006A - Amplifier circuit - Google Patents

Amplifier circuit

Info

Publication number
JPH04178006A
JPH04178006A JP2306927A JP30692790A JPH04178006A JP H04178006 A JPH04178006 A JP H04178006A JP 2306927 A JP2306927 A JP 2306927A JP 30692790 A JP30692790 A JP 30692790A JP H04178006 A JPH04178006 A JP H04178006A
Authority
JP
Japan
Prior art keywords
circuit
input
output
output terminal
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2306927A
Other languages
Japanese (ja)
Inventor
Kazuhiko Inoue
和彦 井上
Yoshiyuki Tamura
田村 慶幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP2306927A priority Critical patent/JPH04178006A/en
Publication of JPH04178006A publication Critical patent/JPH04178006A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To reduce fluctuation of a DC voltage at an output terminal by providing a dummy circuit operated when the amplifier circuit of multi-channel input/ single output is in operation. CONSTITUTION:A dummy circuit 9 is provided with a fixed level source 11, an input terminal 12 and an input circuit 10. When all input circuits 1 are not in operation, the added dummy circuit 9 is in an operating state and an output of the dummy circuit 9 is outputted to an output terminal 6. When any of the input circuits 1 is in operation, the dummy circuit 9 is inoperative by a changeover circuit 2' and an output of the input circuits 1 in the operating state is outputted to the output terminal 6. As a result, even when fluctuation of each input circuit itself is large, when the input circuits 1 are of the same circuit constitution, the input offset voltage is at an equal level and output fluctuation is much reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は増幅回路に間し、特に多チャンル入カー単出力
で2入力回路の動作・非動作を切り換える増幅回路に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier circuit, and more particularly to an amplifier circuit that switches between operation and non-operation of a two-input circuit with a multi-channel input and a single output.

〔従来の技術〕[Conventional technology]

第3図において、従来の増幅回路は、n個の信号源8が
それぞれ入力される入力端子5と、各入力端子5を入力
とするn個の入力回路1と、入力切換回路2と、出力回
路3と、切換回路4と、固定電位7と、出力端6とを備
えている。
In FIG. 3, the conventional amplifier circuit includes input terminals 5 to which n signal sources 8 are respectively input, n input circuits 1 to which each input terminal 5 is input, an input switching circuit 2, and an output. It includes a circuit 3, a switching circuit 4, a fixed potential 7, and an output end 6.

従来のこの種の増幅回路は、複数の入力回路1と入力切
換回路2と出力回路3と切換回路4とで構成されていた
。ここで、入力回路1が動作している時は複数ある入力
回路1のうちの1つが選択され、出力端6より信号が出
力される。入力回路1が動作しない時、出力端6の直流
電圧(以下DCT、圧と記す)が変動しないよう出力端
6を固定電位7に切り換える様な回nl梢成となってい
た。
A conventional amplifier circuit of this type is composed of a plurality of input circuits 1, an input switching circuit 2, an output circuit 3, and a switching circuit 4. Here, when the input circuit 1 is operating, one of the plurality of input circuits 1 is selected and a signal is output from the output terminal 6. When the input circuit 1 does not operate, the output terminal 6 is switched to a fixed potential 7 so that the direct current voltage (hereinafter referred to as DCT) at the output terminal 6 does not fluctuate.

第3図の増幅回路の動作を、第4図に示す、第4図は、
従来の出力端6における電圧の変化を示したタイミング
図である。
The operation of the amplifier circuit in FIG. 3 is shown in FIG. 4.
FIG. 6 is a timing diagram showing changes in voltage at the conventional output terminal 6;

第3図において、切換回路2によって出力端6が固定電
位7から出力回路3の出力に切換えられた場合、即ち、
入力回路1は非動作状態から動作状態に変化した場合、
出力端6のDC電圧変化は固定電位7から入力回路1の
出力まで変化することになる。この為、出力端6でのD
C電圧変動は入力回路1の電圧変動すなわち、入力口M
lの入力オフセット電圧で決まり、入力回路1の入力オ
フセット電圧が大きいと出力端6の電圧変動も大きくな
ってしまう。
In FIG. 3, when the output terminal 6 is switched from the fixed potential 7 to the output of the output circuit 3 by the switching circuit 2, that is,
When the input circuit 1 changes from a non-operating state to an operating state,
The DC voltage change at the output end 6 changes from the fixed potential 7 to the output of the input circuit 1. For this reason, D at output terminal 6
C voltage fluctuation is the voltage fluctuation of input circuit 1, that is, input port M
It is determined by the input offset voltage of l, and if the input offset voltage of the input circuit 1 is large, the voltage fluctuation at the output terminal 6 will also be large.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前述した従来の増幅回路は、入力回路lのすべてが動作
していない状態にある時、出力端DC電圧が変動しない
様、出力端6を固定;位7に切り換える様な回路構成と
なっているので、入力回路1の入力に入力オフセット電
圧がある場合、固定;位7と入力回路1の出力端電位に
差が生じ、グリッチ(切換時のひげ)として5次段回路
入力に信号が伝えられ、次段の応答が遅くなるとか、次
段の誤動作の原因になるという欠点がある。
The conventional amplifier circuit described above has a circuit configuration in which when all of the input circuits 1 are not operating, the output terminal 6 is fixed and switched to 7 so that the output terminal DC voltage does not fluctuate. Therefore, if there is an input offset voltage at the input of input circuit 1, a difference will occur between the output terminal potential of fixed position 7 and input circuit 1, and the signal will be transmitted to the input of the fifth stage circuit as a glitch (whisker at the time of switching). However, there are disadvantages in that the response of the next stage becomes slow or it causes malfunction of the next stage.

本発明の目的は、前記欠点を解決し、切換時にグリッチ
が生じないようにした増幅回路を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to provide an amplifier circuit in which glitches do not occur during switching.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の増幅回路の構成は、外部信号がそれぞれ入力さ
れる複数の第1の信号入力回路を設け、これら第1の信
号入力回路の出力のうち一つを選択出力する切換回路を
設け、前記切換回路の出力を入力とする出力回路を設け
た増幅回路において、入力が固定電位に接続されかつ前
記第1の信号入力回路と同様な回路を有する第2の信号
入力回路が前記第1の信号入力回路の非動作期間中に前
記出力回路に入力されるように接続されていることを特
徴とする。
The configuration of the amplifier circuit of the present invention includes a plurality of first signal input circuits into which external signals are respectively input, a switching circuit for selectively outputting one of the outputs of these first signal input circuits, and In the amplifier circuit provided with an output circuit that receives the output of the switching circuit as an input, a second signal input circuit whose input is connected to a fixed potential and has a circuit similar to the first signal input circuit receives the first signal. It is characterized in that the signal is connected to be input to the output circuit during a non-operation period of the input circuit.

〔実施例〕〔Example〕

次に本発明について図面を多照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の増幅回路のブロック図、第
2図は第1図の出力端におけるDC電圧の変化を示した
タイミング図である。第1図において、本実施例は、破
線で囲んだ第2の信号入力回路(ダミー回路)9と、1
点鎖線で囲んだ切換口!+2  とが、追加されている
。また、従来必要とされた固定電位7.切換回路4が除
去されている。その他の部分は、第3図と同様である。
FIG. 1 is a block diagram of an amplifier circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart showing changes in DC voltage at the output terminal of FIG. In FIG. 1, in this embodiment, a second signal input circuit (dummy circuit) 9 surrounded by a broken line,
Switching port surrounded by dotted chain line! +2 has been added. Furthermore, the fixed potential 7. The switching circuit 4 has been removed. Other parts are the same as in FIG. 3.

第1図のダミー回N9は、固定;位11と、入力端12
と、入力回路10とを有する。第1図において、すべて
の入力回路lが動作していない時、追加されたダミー回
路9が動作状態となり、8カ端6には追加されたダミー
回路9の出力が出力される0次に、複数ある入力口N1
のいずれかが動作状態の時、追加されたダミー回路9は
非動作状態となる為、動作状態にある入力回路1の出力
が出力端6に出力される。この結果、入力回路1がどの
状態においても出力端6に出力されるのは入力口!?i
1.又はダミー回n90体の出力である為、入力回路1
単体での変動は大きくても7.各入力回路1で同一回路
構成となっていれば、入力オフセット電圧が同等レベル
となる為、出力の変動はかなり低減できる。
The dummy circuit N9 in FIG. 1 is fixed; digit 11 and input terminal 12.
and an input circuit 10. In FIG. 1, when all the input circuits l are not operating, the added dummy circuit 9 is in the operating state, and the output of the added dummy circuit 9 is output to the 8 terminal 6. Multiple input ports N1
When any one of the input circuits 1 and 2 is in an active state, the added dummy circuit 9 is in a non-active state, so that the output of the input circuit 1 in an active state is outputted to the output terminal 6. As a result, no matter what state the input circuit 1 is in, the output terminal 6 is the input port! ? i
1. Or, since it is the output of dummy times n90 bodies, input circuit 1
The fluctuation for a single unit is at most 7. If each input circuit 1 has the same circuit configuration, the input offset voltages will be at the same level, so that output fluctuations can be considerably reduced.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、多チヤンネル入力・単出
力の増幅回路において、すべての入力回路が動作してい
ない時に動作するようなダミー回路を設ける事により、
出力端DC電圧の変動を低減できるという効果がある。
As explained above, the present invention provides a dummy circuit that operates when all input circuits are not operating in a multi-channel input/single output amplifier circuit.
This has the effect of reducing fluctuations in the output terminal DC voltage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の増幅回路のブロック図、第
2図は第1図の出力端における電圧の変けるDC電圧の
変動を示すタイミング図である。 1.10・−・入力回路、2・・・入力切換回路、3・
・・出力回路、4・・・切換回路、5,12・・・入力
端子、6・・・出力端、7,11・・・固定電位、8・
・・信号順、9・・・第2の信号入力回路(ダミー回路
)。
FIG. 1 is a block diagram of an amplifier circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart showing fluctuations in the DC voltage as the voltage at the output terminal of FIG. 1 changes. 1.10--input circuit, 2--input switching circuit, 3-
... Output circuit, 4... Switching circuit, 5, 12... Input terminal, 6... Output terminal, 7, 11... Fixed potential, 8...
...Signal order, 9...Second signal input circuit (dummy circuit).

Claims (1)

【特許請求の範囲】[Claims] 外部信号がそれぞれ入力される複数の第1の信号入力回
路を設け、これら第1の信号入力回路の出力のうち一つ
を選択出力する切換回路を設け、前記切換回路の出力を
入力とする出力回路を設けた増幅回路において、入力が
固定電位に接続されかつ前記第1の信号入力回路と同様
な回路を有する第2の信号入力回路が前記第1の信号入
力回路の非動作期間中に前記出力回路に入力されるよう
に接続されていることを特徴とする増幅回路。
A plurality of first signal input circuits to which external signals are respectively input are provided, a switching circuit is provided for selectively outputting one of the outputs of the first signal input circuits, and an output whose input is the output of the switching circuit. In the amplification circuit provided with the circuit, a second signal input circuit having an input connected to a fixed potential and having a circuit similar to the first signal input circuit operates as described above during the non-operation period of the first signal input circuit. An amplifier circuit characterized in that the amplifier circuit is connected to be inputted to an output circuit.
JP2306927A 1990-11-13 1990-11-13 Amplifier circuit Pending JPH04178006A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2306927A JPH04178006A (en) 1990-11-13 1990-11-13 Amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2306927A JPH04178006A (en) 1990-11-13 1990-11-13 Amplifier circuit

Publications (1)

Publication Number Publication Date
JPH04178006A true JPH04178006A (en) 1992-06-25

Family

ID=17962955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2306927A Pending JPH04178006A (en) 1990-11-13 1990-11-13 Amplifier circuit

Country Status (1)

Country Link
JP (1) JPH04178006A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5719649B2 (en) * 1975-08-25 1982-04-23

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5719649B2 (en) * 1975-08-25 1982-04-23

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