JPH04172731A - Error correction system - Google Patents

Abstract

PURPOSE:To prevent mis-synchronization of word synchronization without addition of a special circuit to a sender side by providing a scramble circuit which adds a scramble pattern to an output of a coding circuit and sends the result to a receiver side as a reception signal to a sender side for mis-synchronization prevention countermeasure. CONSTITUTION:A coding circuit 1 implements error correction coding to an input signal 101 by using a block code. A scramble circuit 2 adds a scramble pattern to a code word from the coding circuit 1 and sends the result to a radio line 10. A receiver side buffer register 3 latches a reception signal 201 subject to error correction coding and sent via the radio line 10 till a syndrome pattern is obtained. A syndrome pattern correction circuit 5 corrects an output of a division circuit 4 and outputs the result so as to restore the effect of the addition of the scramble pattern by the scramble pattern circuit 2 onto the syndrome pattern. When word synchronization is correct and no error is caused in the radio line 10, an output of the syndrome pattern correction circuit 5 goes all to 0.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to an error correction system in a digital wireless communication system. In particular, it relates to a word synchronization method for error correction type professional codes.

〔overview〕

In an error correction system, the present invention connects a scrambling circuit inserted after the encoding circuit on the transmitting side as a measure to prevent error synchronization, and on the receiving side uses a unique syndrome and SE tan correction circuit to determine the syndrome pattern and perform word processing. By establishing synchronization and restoring the effects of the scrambling pattern, it is possible to prevent incorrect word synchronization without adding a special circuit to the transmitting side.

[Conventional technology]

FIG. 2 is a block diagram of a conventional error correction method.

Conventionally, error correction methods for digital wireless communication systems have been
Error correction was performed using a program code with the configuration shown in the figure. In other words, in Fig. 2, when a block code is used for error correction, since the block code is a cyclic code, there is a considerable possibility that the word synchronization will be erroneously synchronized on the receiving side, and in order to prevent this, On the transmitting side, after the input signal is encoded by the encoding circuit 1, the bits at a predetermined position in each word are inverted and sent out by the bit inverting circuit 9, and the receiving side receives the signal based on the position of the inverted bit. Word synchronization was established by correcting the syndrome pattern obtained from the signal.

Furthermore, when performing scrambling as shown in Figure 2,
If scrambling is applied after encoding, word synchronization cannot be achieved on the receiving side, so there is a restriction that the scrambling circuit 2 must be connected before the encoding circuit 1 on the transmitting side.

[Problem to be solved by the invention]

However, with this type of error correction system, in order to prevent incorrect word synchronization, a bit inverting circuit must be added to invert bits at predetermined positions on the transmitting side, which increases the circuit scale. there were.

The present invention solves the above-mentioned drawbacks, and aims to provide an error correction method that can prevent erroneous word synchronization without adding a special circuit to the transmitting side.

[Means to solve the problem]

Further, the present invention includes an encoding circuit on the transmitting side that encodes an input signal using a block code and outputs a code word, and a buffer register on the receiving side that temporarily holds an input received signal. A division circuit that divides the received signal into blocks of the length of the code word based on a timing signal, divides each block by a generating polynomial, and outputs the remainder as a syndrome pattern, and correction for the output syndrome pattern. a syndrome pattern correction circuit that applies the timing signal to the division circuit, corrects the applied timing signal based on the output of the syndrome pattern correction circuit, and outputs an error correction control signal when word synchronization is established. a detection circuit; a decoding circuit that reads and decodes the contents of the buffer register based on the output error correction control signal and the output of the syndrome pattern correction circuit; and a descrambler for the output of the decoding circuit. In the error correction method, the transmitting side includes a scrambling circuit that adds a scrambling pattern to the output of the encoding circuit as a measure to prevent erroneous synchronization, and transmits the scrambled pattern to the receiving side as the received signal. , the syndrome pattern correction circuit includes means for correcting the added scramble pattern.

Further, in the present invention, the synchronization detection circuit includes means for determining that word synchronization has been established when the probability that all the syndrome patterns output from the syndrome pattern correction circuit are "0" is equal to or higher than a predetermined threshold. be able to.

[Effect]

The scrambling circuit on the transmitting side adds a scramble button to the output of the encoding circuit as a measure to prevent erroneous synchronization, and transmits it to the receiving side as the received signal. The syndrome pattern correction circuit corrects the scramble pattern added by the scramble circuit.

Further, the synchronization detection circuit determines that word synchronization has been established when the probability that all the syndrome patterns output from the syndrome pattern correction circuit are "0" is equal to or higher than a prescribed threshold value.

As described above, erroneous word synchronization can be prevented without adding a special circuit to the transmitting side.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of an error correction system according to an embodiment of the present invention. In FIG. 1, the error correction method includes an encoding circuit 1 on the transmitting side that encodes an input signal 101 for error correction using a block code and outputs a code word, and on the receiving side temporarily holds an input received signal 201. a buffer register 3,
Received signal 201 based on input timing signal 202
a division circuit 4 which divides each block into blocks having the length of the code word, divides each block by a generating polynomial, and outputs the remainder as a syndrome pattern; and a syndrome pattern correction circuit 5 which corrects the output syndrome pattern.
and a synchronous voltage detection circuit which applies the timing signal 202 to the divider circuit 4, corrects the applied timing signal 202 based on the output of the syndrome pattern correction circuit 5, and outputs an error correction control signal 203 when word synchronization is established. 6, a decoding circuit 7 which reads and decodes the contents of the buffer register 3 based on the syndrome pattern 204 as the output of the error correction control signal 203 and the syndrome pattern correction circuit 5; A descramble circuit 8 is provided for descrambling the data.

The present invention is characterized in that the transmitting side includes a scrambling circuit 2 that adds a scrambling pattern to the output of the encoding circuit 1 and transmits it to the receiving side as a received signal 201 as a measure to prevent synchronization errors. The correction circuit 5 includes means for correcting the added scramble button.

The synchronization detection circuit 6 also includes a syndrome pattern correction circuit 5.
includes means for determining that word synchronization has been established when the probability that all outputs of are "0" is greater than or equal to a predetermined threshold.

The operation of the error correction method having such a configuration will be explained.

In FIG. 1, an encoding circuit 1 performs error correction encoding on an input signal 101 using a block code.

The scrambling circuit 2 adds a scrambling pattern to the code word from the encoding circuit 1 and sends it to the radio line 10 .

The buffer register 3 on the receiving side holds the received signal 201 that has been error correction encoded and transmitted via the wireless line 10 until a syndrome pattern is obtained. Division circuit 4
inputs the received signal 201, blocks the received signal 201 to the length of a code word using the timing signal 202 from the synchronization detection circuit 6, divides each block by the generator polynomial, and outputs the remainder.

Here, if the timing of blocking is correctly word-synchronized, each block matches the code word, and no scrambling pattern is added by the scrambling circuit 2 and no error occurs on the wireless line 10, the dividing circuit 4 All outputs are "0".

However, due to the addition of a scramble pattern by the scramble circuit 2, even if the word synchronization is correct and no errors occur on the wireless line 10, the outputs of the divider circuit 4 may not all be "0". .

The syndrome pattern correction circuit 5 includes the scramble circuit 2
The output of the division circuit 4 is corrected and outputted so as to restore the influence on the syndrome pattern caused by the addition of the scramble pattern. If the word synchronization is correct and no error occurs on the wireless line 10, all outputs of the syndrome pattern correction circuit 5 will be "0".

Now, consider a case where word synchronization is not properly achieved. First, if there is no addition of a syndrome pattern by the scrambling circuit 2 on the transmitting side and no correction of the syndrome pattern by the syndrome pattern correction circuit 5, there is a high possibility that the syndrome pattern will be all "0" due to the characteristics of the cyclic code. .

However, when the scramble circuit 2 adds a scramble button and the syndrome pattern correction circuit 5 corrects the syndrome pattern, there is a very high possibility that the syndrome pattern after correction by the syndrome pattern correction circuit 5 will be all "0". small.

The synchronization detection circuit 6 corrects the blocking timing signal 202 of the division circuit 4 as word synchronization is incorrect when the probability that the outputs of the syndrome pattern correction circuit 5 are all "0" is less than a specified threshold value. When it is determined that word synchronization has been achieved when the threshold value is exceeded, an error correction control signal 203 is output to the decoding circuit 7.

The decoding circuit 7 performs error correction on the received signal 201 held in the buffer register 3 using the syndrome pattern 204 from the syndrome pattern correction circuit 5 and the error correction control signal 203 from the synchronization detection circuit 6.

The descrambling circuit 8 adds the same scramble button added to the code word by the transmitting side scramble circuit 2 to the signal from the decoding circuit 7, and performs disk scrambling on the signal.

〔Effect of the invention〕

As described above, the present invention has an excellent effect of preventing erroneous word synchronization without adding a special circuit to the transmitting side.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an error correction system according to an embodiment of the present invention. FIG. 2 is a block diagram of the error correction method of the present invention. l... Encoding circuit, 2... Scramble circuit, 3.
... Buffer register, 4... Division circuit, 5... Syndrome pattern correction circuit, 6... Synchronization detection circuit, 7
... Composite circuit, 8 ... Descramble circuit, 9
m-bit inversion circuit, 10... wireless line, 101...
Input signal, 201... Received signal, 202... Timing signal, 203... Error correction control signal, 204...
・Syndrome pattern.

Claims (1)

[Scope of Claims] 1. A transmitting side is provided with an encoding circuit that encodes an input signal using a block code for error correction and outputs a code word, and a receiving side is provided with a buffer register that temporarily holds an input received signal; a division circuit that divides the received signal into blocks of the length of the code word based on an input timing signal, divides each block by a generating polynomial, and outputs the remainder as a syndrome pattern; A syndrome pattern correction circuit performs correction, and the timing signal is applied to the division circuit, and the applied timing signal is corrected based on the output of the syndrome pattern correction circuit, and an error correction control signal is output when word synchronization is established. A synchronization detection circuit, a decoding circuit that reads and decodes the contents of the buffer register based on the output error correction control signal and the output of the syndrome pattern correction circuit, and a descrambling circuit for the output of the decoding circuit. In the error correction method, the transmitting side includes a scrambling circuit that adds a scrambling pattern to the output of the encoding circuit and transmits it as the received signal to the receiving side as a measure to prevent erroneous synchronization. An error correction method, wherein the syndrome pattern correction circuit includes means for correcting the added scramble pattern. 2. The error correction according to claim 1, wherein the synchronization detection circuit includes means for determining that word synchronization has been established when the probability that the outputs of the syndrome pattern correction circuit are all "0" is greater than or equal to a predetermined threshold. method.