GB2133954A - Receiver for a digital data communication system - Google Patents

Abstract

In the data communication system, the data is transferred block by block using an error-correcting code. The receiver contains a bit-synchronizing circuit (3) and decoding and error- correcting circuits (6, 4, 7). The regenerated bit stream appearing at the output of the bit-synchronizing circuit (3) is fed to a delay circuit (10, 11) consisting of at least two stages. The bit streams at the input of the delay circuit, after the first stage (10), and at the output of the delay circuit are each fed to one of the decoding and error- correcting circuits (6, 4, 7). A selection circuit (12) following the decoding and error-correcting circuits transfers a selected error-corrected bit stream to its output (A). Error correction thus remains possible, although major changes in signal transmit time may occur. <IMAGE>

Description

SPECIFICATION Receiver for a digital data communication system This invention relates to a receiver for a digital data communication system of the kind in which the data is transferred as blocks using an errorcorrecting code, the receiver comprising a bitsynchronizing circuit foliowed by a first decoding and error-correcting circuit.

DE-OS 31 04 762 discloses a binary data transmission system which uses an errorcorrecting code. The receiver therefor includes a bit-synchronizing circuit and a decoding and errorcorrecting circuit, of which only the latter is shown. The data received by such a receiver must not contain any errors caused by bit slips on the transmission path, because otherwise decoding and error-correction would be impossible. Bit slips are caused when a mobile transmitter and/or receiver enters an area where communication is possible only by an indirect path, and where major changes in signal transit time occur.

An object of the invention is to provide a receiver of the above kind which is capable of detecting bit slips and of processing data received with a bit slip.

According to the invention in its broadest aspect, a receiver of the kind referred to is characterized in that the regenerated bit stream present as blocks at the output of the bitsynchronizing circuit is also fed to an at least twostage delay circuit the first delay stage and the second delay stage are followed by a second decoding and error-correcting circuit and a third decoding and error-correcting circuit respectively, and a selection circuit is provided which transfers that bit stream which was error-correctable to an output for further processing.

An embodiment of the invention will now be described by way of example which reference to the accompanying drawings, in which: Figure 1 is a block diagram of a portion of the receiver with a parallel evaluation facility; Figure 2 is a block diagram of a portion of a receiver with a serial evaluation facility; Figure 3 is a block diagram of a selection circuit and Figure 4 is a block diagram of a portion of a bitsynchronizing circuit.

Figures 1 and 2 show a receiver for a digital data communication system without the radiofrequency section. The latter provides a bit stream DI, in the form of blocks to a terminal E.

In Figure 1, the bit stream Dl is fed from the terminal E to a bit-synchronizing circuit 3. This circuit 3 is supplied with a clock signal T from a clock generator 1 , which is controlled by a quartz crystal unit 2; the clock signal T is also applied to other subcircuits. The circuit 3 regenerates the bit stream and derives a signal S1, S2 for adjusting the clock generator 1. The regenerated bit stream is fed to a delay circuit consisting of two stages 10, 1 1. Each of the stages 10 and 11 of the delay circuit delays the bit stream by one bit and may be implemented with a D flip-flop.

The bit streams at the input of the delay circuit, after the first stave 1 0, and at the output of the second stage 11 are fed to decipherers 8, 5, and 9, respectively. Each of the decipherers may be implemented with an EXOR gate and is also fed with a sequence of cipher bits PN. The outputs of the decipherers 8, 5, and 9 are connected to decoding and error-correcting circuits 6, 4 and 7, respectively. In the decoding and error-correcting circuits 6, 4 and 7, the words contained in the bit stream are decoded and, if necessary and possible, corrected.

In the absence of a bit slip, the bit stream at the output of the first stage 10 of the delay circuit is in the normal phase position, so that it can be deciphered with the cipher bits PN and correctly processed in the decoding and error-correcting circuit 4. The phase of the bit stream at the output of the circuit 3 lags, and the phase of the bit stream of the output of the second stage 11 of the delay circuit leads, the normal phase. In the absence of a bit slip in the received bit stream, the decipherers 8 and 9 deliver a bit stream with a bit error rate of 50%, which cannot be correctly decoded in the following circuits 6 and 7.

If a bit slip occurs due to the reception of an indirect signal instead of a direct signal, the bit stream lags the previously received bit strea, so it can be deciphered only by the decipherer 8. The decipherers 5 and 9 provide an erroneous bit stream which cannot be corrected in the following circuits 4 and 7.

If a bit slip occurs due to the reception of a direct signal instead of an indirect signal, the bit stream lags the previously received bit stream, so it can be deciphered only by the decipherer 9. The decipherers 5 and 8 provide an erroneous bit stream which cannot be corrected in the following circuits 4 and 6.

The bit streams at the outputs of the decoding and error-correcting circuits 4, 6, and 7 are designated AO, Al N and A1V, respectively. Each of these circuits also delivers a signal M6, M6N and M6V, which indicates whether the bit stream AO, Al N and Al V is the bit stream to be further processed. The signals M6, M6N and M6V are also referred to as "quality signals". The signal M6 is delivered if two or several correctable errors were present in the bit stream, while the signals M6N and M6V are delivered only if a maximum of one correctable error was present. This means that the decoding and error-correcting circuit 4 is preferred to avoid conflicts in deciding which of the bit streams AO, Al N and Al V is to be further processed.

The corrected bit streams AO, A1V and Al N and the signals M6, M6N, and M6V are fed to a selection circuit 12, which, in response to the signal M6, M6N or M6V, transfers the bit stream AO, Al N or Al V, respectively, to an output A for further processing. The signal M6, M6N or M6V is transferred to an output A', where it is designated M. The bit stream at the output A is designated DO.

At the end of each processed block, the decoding and error-correcting circuits 4, 6 and 7 send enable signals F, BSN, and BSV, respectively, to the circuit 3 when delivering the signals M6, M6N, and M6V, respectively. The action of the enable signals will be explained below.

Figure 2 is a block diagram showing the same portion of the receiver for a digital data communication system as in Figure 1. Therefore, like reference characters are used to designate like parts, and only the parts differing from~ Figure 1 will be described.

The bit streams from the input and the output of the first stage 10 and from the output of the second stage 11 of the delay circuit are fed to a switch 13, which transfers them successively to the decipherer 5. The latter and the following decoding and error-correcting circuit 4' operate so fast that they can process three blocks of the bit stream during one block period. Thus, one decipherer 5 and one decoding and errorcorrecting circuit 4' are sufficient to process successively all three bit streams from the delay circuit. The three bit streams A' delivered by the decoding and error-correcting circuit 4', together with the respective signals M' associated with them, are fed to the selection circuit 12', which transfers only that bit stream to the output A whose signal M' permits this.

Figure 3 shows the selection circuit 12 of Figure 1 in a block diagram. The outputs of three AND gates 16, 17 and 18 are combined by an OR gate 14, whose output provides the bit stream DO.

By means of an OR gate 15, the signals M6, M6N, and M6V are gated to the output A'. The interconnection of the inputs of the AND gates 1 6, 1 7, and 1 8 is chosen so as to prevent the simultaneous transfer of two bit streams.

The bit stream AO is applied to one input of the AND gate 17, whose second input is presented with the signal M6, which is also applied to inverting inputs of the AND gates 1 6 and 1 8 and to a first input of the OR gate 15.

The bit stream Al N is applied to one input of the AND gate 18, whose second input is presented with the signal M6N, which is also applied to a second inverting input of the AND gate 16 and to a second input of the OR gate 1 5.

The bit stream A1V is applied to one input of the AND gate 16, whose second input is presented with the signal M6V, which is also applied to a third input of the OR gate 1 5.

Figure 4 is a block diagram showing that portion of the circuit 3 of Figure 1 which contains the synchronizing circuitry and the circuitry for deriving the adjusting signals S1 and S2. The bit stream Dl from the terminal E is fed to a regenerating circuit (not shown) which delivers it to the first delay stage 10 and the decipherer 8, and to a synchronizing circuit 1 9. The latter measures the phase of the bit stream block by block and transfers the result to a decoder 20, whose eight outputs provide a signal which is a measure of the average phase of the respective block quantized into 1/8 bits.If the phase of the bit stream lags the phase of the clock signal provided by the clock generator 1, an OR gate 21 connected to the upper four outputs delivers a signal to the delay circuit 23; if the phase of the bit stream leads the phase of the clock signal, an OR gate 22 connected to the lower three outputs delivers a signal to a delay circuit 24. These two delay circuits are shift registers. If a signal appears at the fourth output of the decoder 20 from the bottom, this means that the phase of the bit stream agrees with the phase of the clock signal from the clock generator 1, so that the latter need not be readjusted.

The delay circuits 23 and 24 delay the signals from the outputs of the OR gates 21 and 22 by one block length until the decoding and errorcorrecting circuit 4 delivers the enable signal F.

The enable signal F is applied to two AND gates 25 and 26, which have their second inputs connected to the outputs of the delay circuits 23 and 24, respectively. Via a following OR gate 27 or 28, the adjusting signal S2 or S1 is delivered to the clock generator 1 in order to adjust the latter so that its phase agrees with the average phase of the bit stream again.

If the received bit stream leads or lags the clock signal provided by the clock generator 1 by one bit, the circuit 3 receives no enable signal F from the decoding and error-correcting circuit 4 but the enable signal BSV or BSN from the decoding and error-correcting circuit 7 or 6. This enable signal is applied as an adjusting signal S2 or S1 through the OR gate 27 or 28 to the clock generator 1 and adjusts the latter until the decoding and errorcorrecting circuit 4 can operate correctly again.

The clock signal has thus been "recentered", and the receiver can handle phase leads and lags again.

Claims (10)

1. A receiver for a digital data communication system of the kind in which the data is transferred as blocks using an error-correcting code, the receiver comprising a bit-synchronizing circuit followed by a first decoding and error-correcting circuit, characterized in that the regenerated bit stream present as blocks at the output of the bitsynchronizing circuit (3) is also fed to an at least two-stage delay circuit (10, 11), that the first delay stage (10) and the second delay stage (11) are followed by a second decoding and errorcorrecting circuit (4) and a third decoding and error-correcting circuit (7), respectively, and that a selection circuit (12) is provided which transfers that bit stream which was error-correctable to an output (A) for further processing.

2. A receiver as claimed in claim 1, characterized in that the bit streams at the input, after the first stage (10), and at the output of the delay circuit are fed simultaneously to one decoding and error-correcting circuit each (6, 4, 7) which is followed by the selection circuit (12).

3. A receiver as claimed in claim 1, characterized in that the bit streams at the input, after the first stage (10), and at the outnilt nf thP delay circuit are fed successively and block by block to a single decoding and error-correcting circuit (4') followed by the selection circuit (12').

4. A receiver as claimed in claim 2 or 3, characterized in that each stage (10, 11) of the delay circuit delays the bit stream by one bit.

5. A receiver as claimed in claim 4, characterized in that each stage (10, 11) of the delay circuit is a D flip-flop.

6. A receiver as claimed in claim 1, characterized in that the selection circuit (12) transfers the bit stream having an average delay in the presence of two or several correctable errors, and the bit streams having the shortest and longest delays only in the presence of a single correctable error.

7. A receiver as claimed in claim 6, characterized in that the selection circuit (12) includes an interlock circuit which prevents the simultaneous transfer of two bit streams.

8. A receiver as claimed in claim 1, characterized in that the bit-synchronizing circuit (3) contains a circuit for adjusting a clock generator (1) which provides an adjusting signal (S1, S2) on receipt of an enable signal (F, BSN, BSV) from the decoding and error-correcting circuit (4, 6, 7).

9. A receiver as claimed in claim 8, characterized in that the enable signals (BSV, BSN) from the decoding and error-correcting circuit for the bit stream with the shortest delay (6) and from the decoding and error-correcting circuit (7) for the bit stream with the longest delay are used to adjust the clock generator (1).

10. A receiver for a digital data communication system substantially as described with reference to the accompanying drawings.