JPH04171943A - Misfet and manufacture thereof - Google Patents

Abstract

PURPOSE:To make the relative positions of a gate electrode and a contact hole constant, by arranging a laminate having a plurality of apertures on which side walls insulating films are formed, on the active region of a first conductivity type semiconductor substrate, arranging second conductivity type regions in which outer wirings are formed, under the apertures, and forming a gate electrode by using the part except aperture forming regions. CONSTITUTION:In an active region 33 of a first conductivity type semiconductor substrate 31, a laminate 39 is arranged, in which a gate insulating film 35 and gate electrode forming material 37 are formed in this order, and two apertures exposing parts of the active region 33 in rectangular types are formed. Insulating films 49 are formed on the side walls of the aperture 41a, 41b. Second conductivity type regions 51 turning to a source-drain region are formed in semiconductor substrate parts under the apertures. Outer wiring 53 is connected with the second conductivity type regions 51, via the apertures 41a, 41b. A gate electrode is formed by using the part of the gate electrode forming material 37 except the parts for forming the apertures 41a and 41b.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a MISFET and a method for manufacturing the same.

(Prior art) Field effect transistor using metal-insulating film-semiconductor (
MISFET) is an indispensable device for constructing semiconductor devices, and is therefore being studied from various aspects.

For example, literature ■ ("Ultrahigh-speed MOS devices", edited by Susumu Ka'yama, published by Baifukan (February 10, 1986)) Niha, MIS
FET type T: Al MOS FET (7) The manufacturing method and physics are described in detail, especially in the literature ■
On pages 120 to 123 of , a method for manufacturing a MOSFET using an NMO3FET as an example is described in detail.

This manufacturing method is currently the mainstream method for manufacturing MOSFETs. Hereinafter, the process of forming a contact hole for connection between the source/train region and the outside 111 in this manufacturing method will be described in particular.

FIGS. 5(A) to 5(D)) are diagrams for explaining the process, and are process diagrams showing the state of the sample in the main steps in the contact hole forming process using cross-sectional views taken along the gate length direction. It is.

An element isolation insulating film 13 is formed on a semiconductor substrate 11, and a gate insulating film 15, a gate electrode 17, and a source/train region 19 are formed in an active region surrounded by the element isolation insulating film 1113 by a conventionally known method. (5th
Figure (A)).

Next, an interlayer insulating film 21 is formed on the entire surface of this sample by a suitable method (FIG. 5(B)).

Next, a resist button 23 having a window 23a exposing a predetermined portion thereof (a portion corresponding to a predetermined portion of the source train region 19) is formed on this interlayer insulating film 21 by a known phosphorography technique ( Figure 5(C)).

Next, using this resist pattern 23 as a mask, a contact hole 25 is formed in the interlayer insulating film 21 by a known etching technique.
is formed (Fig. 5(D)).

In this contact hole 25, an external wiring (not shown) for connecting the source/drain region to the outside by 1Fr is formed.

MOSFET when contact hole is formed normally
A cross-sectional view and a plan view seen from above the substrate are shown in FIG. Note that 27 in FIG. 6 is an active area.

(Problem to be solved by the invention!) However, in the conventional manufacturing method, the formation of the gate electrode 17 and the formation of the contact hole 25 were performed in separate steps. If the relative position of the photomask for hole formation deviates from the designed position due to the alignment performance of the exposure device, for example, the contact hole 25 and gate electrode 17 may overlap as shown in FIG. There was a problem that the contact hole and gate electrode dark path M were formed even if the two did not overlap.
There was a problem that (×1 in FIG. 7) varied.

When a contact hole is formed in the state shown in FIG. 7, the gate electrode 17 and the source/drain region 19 are connected by external wiring (not shown), and the
ISFET ceases to operate as a transistor. This problem of mask alignment becomes more serious as MISFETs become more miniaturized. Furthermore, due to variations in the distance X between the contact hole and the gate electrode, a resistance component R occurs in the source/train region between the gate electrode 17 and the contact hole 25 (refer to FIG. 8, this is referred to as the diffusion layer resistance). This causes variations in device characteristics.

In addition, in order to reduce the influence of the mask misalignment mentioned above,
In the conventional method, the gate electrode 17 and the contact hole 2
Since it is not possible to narrow the gap between the resistance value and the resistance value of the diffusion layer to a small value, there is a limit to how much the resistance value of the diffusion layer can be reduced. If the diffusion layer resistance is large, the operating speed of the transistor will be reduced, so improvement is desired.

This application has been filed in view of these points, and therefore, the object of the first invention of this application is to provide a structure in which the relative positions of the gate electrode and the contact hole are less likely to shift than in the past, and the resistance of the diffusion layer is lower than in the past. MISFET with
Our goal is to provide the following. Furthermore, a second object of the invention of this application is to provide a method suitable for manufacturing the MISFET of the first invention.

(Means for solving Problem Ii) In order to achieve this objective, MI of the first invention of this application is
According to the SFET, at least two laminates are provided on the active region of the first conductivity type semiconductor substrate, including at least a gate insulating film and a gate electrode forming material in this order, and exposing a part of the active region.
A stacked body having two openings is provided, an absolute S*IFr is provided on the sidewalls of these openings, a second conductivity type region is provided in the above-mentioned semiconductor substrate portion under the opening, and the above-mentioned opening An external wiring lI is applied to the second conductivity type region through the portion.
! A gate electrode is formed in a portion of the gate electrode forming material other than the opening forming region.

Further, according to the method for manufacturing a MISFET of the second invention of this application, a step of forming a laminate including a gate insulating film and a gate electrode forming material in this order on the entire surface of the active region of the semiconductor substrate of the first conductivity type; , forming at least two openings in the laminate to expose a portion of the aforementioned gate insulating film; and introducing a second conductivity type impurity into the sample in which the openings have been formed to form a portion of the semiconductor substrate under the aforementioned openings. The method is characterized in that it includes the steps of: forming a second conductivity type region; and forming an aperture g* on the side wall of the opening before or after forming the second conductivity type region.

In carrying out these first and second inventions, when the opening is an opening formed by removing a part of the laminate so that the entire side wall is composed of the above-mentioned laminate, Also,
An opening formed by removing a part of the laminate, that is, a laminate, up to a part of the edge of the laminate so that a part of the side wall is composed of an insulating film for element isolation and the other part is composed of the laminate. This includes any case where the opening is formed by removal.

Furthermore, in the manufacturing method of the second invention, the opening formed in the stack is deep enough to expose a part of the gate insulating film; However, even if the opening is deep enough to expose the surface of the active region, an oxide layer will be formed on the surface of the active region during heat treatment in a later step, and the external wiring II In any case, it is necessary to remove this oxide layer when forming the oxide layer, so in the second invention, the gate layer is left from the beginning and removed when external wiring is formed.

(Function) According to the configuration of the first invention, the gate electrode region and the functhole region are specified according to the positions of at least two openings provided in the laminate including the gate electrode StS and the gate electrode forming material. For example, if two openings are provided, one of the openings will specify the area.
The train contact region is specified by the other opening, and the portion of the gate electrode forming material between these two openings becomes a substantive gate electrode. Therefore, the relative positions of the gate electrode and the contact hole can be kept constant.

Furthermore, according to the configuration of this particular invention, the distance between the gate electrode and the contact hole is defined by the absolute thickness provided on the side wall of the opening. This absolute! The /Ia film can be formed with good controllability by thermally oxidizing the polysilicon when the gate electrode forming material is, for example, polysilicon, and can be formed with good controllability even when the film is formed by another film forming method. The distance between the source train 1M region and the gate electrode can be kept constant and at the necessary minimum. Therefore, the diffusion layer resistance and its variation can be reduced compared to the conventional method.

Further, according to the MISFET manufacturing method of the second invention of this application, a gate electrode and a contact hole are simultaneously formed by a photolithography process using a single mask having a button for forming an opening. Therefore, the process of mask alignment between the gate electrode photomask and the contact hole photomask, which has been conventionally performed, can be eliminated, and the problems that occur when mask alignment is performed do not occur.

In addition, in this manufacturing method, even if the positions of the contact hole and the gate electrode relative to the active region may deviate from the designed positions, the contact hole n distance and the distance between the contact hole and the gate electrode will be Since it is secured on the photomask, it can be kept constant.

Furthermore, the formation of constant St* on the side walls of the opening can be easily and easily controlled by oxidizing the gate electrode forming material or by separately forming an insulating film. Therefore, the distance between the contact hole and the gate electrode can be minimized.

(Example) Hereinafter, with reference to the drawings, the MISFE of the first invention of this application will be explained.
An embodiment of T and an embodiment of the MISFET manufacturing method of the second invention will be described respectively.

Note that each plane used in the following description schematically shows the dimensions, shapes, and arrangement relationships of each component to the extent that the present invention can be understood.

Figure 1 (A) is a cross-sectional view schematically showing the MISFET of the example, and Figure 1 (8) is ml! The positional relationship between the gate insulator 11135 and the gate electrode forming material 37% in this order in the MISFET shown in FIG. 1 (A) and the opening 41 provided in the stack 39 is shown from above the substrate. FIG.

In the MISFET of this embodiment, the active region 33 of the first conductivity type semiconductor substrate 31 is a laminate 39 including a gate insulating film 35 and a gate electrode forming material 37 in this order, and a part of the active region tiJ33 is formed into a rectangular shape. A laminate 39 having two openings (indicated by 41a and 41b in the figure) exposed in the shape of
This is provided.

Here, the two openings 41a and 41b are arranged in order of a predetermined distance Fl.
They are arranged so that they are parallel to each other and parallel to each other. Roughly speaking, since both the openings 41a and 41b are provided inside the laminate formation region, their side walls are entirely made of the laminate forming material, that is, an opening surrounded by the laminate forming material. ing.

Further, the active region 33 is surrounded and defined by the element isolation barrier 181143 and the channel stop layer 45.

Further, an interlayer 111147 is provided on the stacked body 39, and the openings 41a and 41b are provided from the surface of the interlayer insulating film 47 to the surface of the active region 33.

In the MISFET of this example, the opening 41a,
An insulating film 491Fr is provided on the side wall of each of the openings 41a and 41b, and a second conductivity type region 51 serving as a source train region is provided in the semiconductor substrate portion under each of the openings 41a and 4Ib. External wiring 53 is connected to the opening 41a or 41b. Then, the openings 41a and 41b of the gate electrode forming material 37 described above
A gate electrode is formed in a portion other than the formation region.

In this structure, both openings 41a of the gate electrode forming material 37 are sandwiched between the two openings 41a and 41b.
, 4Ib (see figure 1 (A) and (B)) can be considered as the effective gate length. This distance is the distance between the two openings 41a and 41b, and the distance between the openings 41a and 41b.
The thickness of the insulating film 49 provided on the side walls of 1a and 41b and the second
It is mainly determined by the diffusion depth of the conductivity type region 51.

<Modification> Incidentally, the MOFET according to the present invention may of course be provided with an LDD structure.

Further, in the MISFET of the first invention, openings may be provided in the laminate 39, for example, as explained below in FIGS. 2(A) to 2(F). B)
FIG. 3 is a plan view showing a modified MISFET in a position similar to that shown in FIG.

FIG. 2(A) is a diagram showing a MISFET in which the stacked body 39 is provided with two openings 61a and 61b having mutually shaped openings. In this case, the effect that the shape of the contact hole can be made into any shape and the degree of freedom in designing the contact hole is increased can be obtained.

FIG. 2 CB) is a diagram showing a MISFET in which a laminate 39 is provided with three or more openings. In this case, the laminate 3
9 is provided with five openings shown as 63a to 63e.

Of course, these openings can have any shape. Since three or more openings can be arbitrarily distributed and used as source contacts and drain contacts, effects such as increased freedom in wiring design can be expected.

Each of the MISFETs explained using FIG. 1, FIG. 2 (A), and (B) is one in which the side wall of the opening is made of the material forming the laminate. However, at least one of these openings may have a part of its side wall made of a material other than the material forming the laminate.
An example of this will be explained.

FIG. 2(C) shows that the first opening 65a provided in the laminate is formed inside the area of the laminate 39, so it is an opening surrounded by the material constituting the laminate; Opening 65b
This is an example in which three of the four sides are surrounded by element isolation insulation 111143 and one side is an opening surrounded by the constituent material of the laminate 39.

FIG. 2 CD) shows a first opening 67a provided in the laminate;
67b, one of the four sides is
11143 and is an opening surrounded on three sides by the constituent material of the laminate 39.

FIG. 2(E) shows a first opening 69a provided in the laminate;
69b is an example in which three of the four sides are surrounded by the element isolation insulating film 43 and one side is an opening surrounded by the constituent material of the stacked body 39.

Note that in Atsushi 2 (C) to (E), the shape of the opening is quadrilateral and the number of openings is two, but the shape and number are not limited to this.

Next, an example of the method for manufacturing a MISFET, which is the second invention of this application, will be explained using the example of manufacturing an N-channel MISFET described using FIG.
explain. In addition, for this explanation, Figures 3 (A) to (G
Please refer to the process diagram shown in ). These figures show the state of the MISFET at the main steps in the process using a cross-sectional view at the position corresponding to Figure 1 (A) and a plan view added as appropriate to facilitate understanding. .

First, a p+ channel stop layer 45, an isolation film for element isolation (field oxide film) 43, and a gate isolation film 181135 are formed on a P type silicon substrate 31 by, for example, the method described in Document ①.
are formed sequentially. As a result, the active region 33 is specified (FIG. 3(A)).

Next, N+ polysilicon, which is made of polysilicon and has an N type impurity such as phosphorus diffused therein, is formed as a gate electrode forming material 37 over the entire surface of the sample by a known method (FIG. 3(B)).

Next, using a known method, the gate electrode forming material 37! is removed so that the gate electrode forming material 37 remains only on the active region 33! Work/check back. As a result, it is possible to easily form a laminate including the gate electrode 1135 and the gate electrode forming material 37 in this order over the entire surface of the active region 33 (1:3 figure (C)).
).

Next, by a known method, a layer of 1llll was applied on this sample.
A window 71a is formed to expose the surface of the area where the opening is to be formed, roughly above the interlayer gap 11147!
A resist pattern 71 having the following structure is formed (FIG. 3(D))
.

Next, layer 181147, gate electrode forming material 37,
The portions of the resist button 71 exposed through the windows 71a are removed by known etching means to create openings 41a, 41b!
(Fig. 3(E)).

Next, arsenic, for example, is introduced into this sample as an N-type impurity, and the openings 41a, 41 of the P-type silicon substrate 31 are
According to this method, an N-type impurity region (source train region) 51 is formed in each of the lower portions (FIG. 3(F)). can be formed.

Next, by thermally oxidizing this sample, the connecting part 41a,
41b! The surrounding gate electrode forming material (N-type polysilicon) 37 is partially oxidized to form an insulating film 49 on the sidewalls of each of the openings 41a and 41b (FIG. 3(G)). The source train region 5 is formed when external wiring is later embedded in the openings 41a and 41b, respectively.
1 and the gate electrode forming material 37 from being short-circuited.

Further, according to the process order of this embodiment, the activation of the source train region 51 and the diffusion of impurities are simultaneously performed by the heat generated during the formation of the insulating film 49. Note that if it is desired to form the source train region 51 shallowly, it is preferable to form the source train region after the thermal oxidation Iv* for forming the general tightening 11149 is completed.

Next, the oxide film on the surface of the source train region 51 is removed, and then an external wiring 153 made of, for example, aluminum is buried in the openings 41a and 41b by a known method to obtain the MISFET 1v of the example shown in FIG. .

According to the manufacturing method of the second invention, the openings 41a, 41
The contact hole region and the gate electrode region can be almost determined only by forming the contact hole region and the gate electrode region. For this reason, for example, active area 3
For example, the alignment of the opening forming mask with respect to 3.
As shown in the figure, even if the two openings 41a and 41b
l'! The distance x2CM4 (see Figure 4) and the distance between the gate electrode and the two openings do not change, so it is possible to provide a MISFET with less variation in characteristics.

Furthermore, according to the manufacturing method of the second invention, FIG.
By changing the removal area of the ridge portion of the laminate shown in FIG. 2, it is possible to easily form a modified MISFET as explained using FIGS. 2A' to 2E. In these cases as well, the same effects as in the embodiment described with reference to FIG. 3 can be obtained.

Note that the manufacturing method of the second invention is not limited to the above-mentioned embodiment, and can be modified, for example, as follows.

For example, in the British embodiment, since the gate electrode forming material 37 was polysilicon which is oxidized by heat, the edge film was formed on the side chamber of the opening by thermally oxidizing the gate electrode forming material. However, if the gate electrode forming material is a material that cannot be thermally oxidized, oxide III is formed on the sample in which the opening has already been formed by, for example, the CVD method, and this oxide film is removed by anisotropic etching to form an oxide film only on the side walls of the opening. Note that the method using a CVDM film and anisotropic etching can of course be used even when the gate electrode forming material is a material that can be thermally oxidized.

In addition, before forming an insulating film on the side wall of the opening, a second conductivity type impurity is introduced into the substrate portion under the opening at a low concentration, an insulating film is then formed on the side wall, and then a high concentration impurity is introduced into the substrate portion under the opening. A low concentration train structure (LDD structure) may be formed by implanting second conductivity type impurities at a high concentration.

(Effects of the Invention) As is clear from the above description, according to the MISFET of the first invention of this application, the distance between the gate electrode and the contact hole is determined by the thickness of the insulating film provided in the side chamber of the opening. . If the gate electrode forming material is, for example, polysilicon, this insulating film can be formed with good controllability by thermally oxidizing this polysilicon, and even if the film is formed by another film forming method, it can be formed with good controllability. sauce·
The distance between the train region and the gate electrode can be kept constant and at the minimum required distance. Therefore, since the diffusion layer resistance and its variation can be reduced compared to the conventional method, a MISFET that operates at high speed and a MISFET with less variation in characteristics can be expected.

Further, according to the MISFET manufacturing method of the second invention of this application, a gate electrode and a contact hole can be formed simultaneously by a photolithography process using a single mask having a button for forming an opening. Therefore, the conventional process of mask alignment between the gate electrode photomask and the contact hole photomask can be eliminated, and the number of process steps can be reduced.

Roughly speaking, in the manufacturing method of the present invention, even if the positions of the contact holes and the gate electrode relative to the active region may deviate from the designed positions, the distance between the contact holes and the distance between the contact hole and the gate electrode are kept within the above-mentioned distance. Since it is secured on the photomask, it can be kept constant. Therefore, variations in transisister characteristics can be reduced compared to the conventional art.

In general, the shape and number of openings can be any shape and number depending on the design, which is advantageous in terms of circuit design.

[Brief explanation of drawings]

FIGS. 1(A) and (B) are a cross-sectional view and a plan view of the MISFET according to the embodiment; FIGS. 2(A) to (E) are diagrams for explaining the first invention in detail; FIG. (A) to (G) are process diagrams for explaining an example of the manufacturing method, Figure 4 is a diagram for explaining the manufacturing method, and Figures 5 (A) to
(D) is a process diagram for explaining the prior art; FIG. 6 is a cross-sectional view and a plan view of main parts of the conventional MISFET; FIGS. 7 and 8 are diagrams for explaining the problems of the prior art. It is. 31 - Atsushi 1 conductivity type semiconductor substrate 33 - Active region, 35 - Gate insulating film 37
-Gate electrode forming material, 39-・Laminated body 41a, 41b・
- Opening 43... Insulating film for element isolation 45 - Channel stop layer 47 - Interlayer insulating film 49 - Insulating film 51 provided on the side wall of the opening - Second
Conductivity type region, 53-・External wiring 61a, 61b, 63
a ~ 63e, 65a, 65b, 67a, 67b, 69
a, 69b--opening 71 of modified example...resist button, 71a--window. Patent Applicant: Oki Electric Industry Co., Ltd. 31...First conductive type semiconductor substrate 33--U region 35...Gate insulating layer 37...Gate electrode forming material 39--Laminated body 41a, 41b. ...Opening portion 43--I for isolation between elements! Tectonic membrane 45--Channel stop layer 47-11 P! Edge film 49=-Insulating layer 51 provided on the side wall of the frontage part...Second conductivity type region 53-...External wiring 41a 41b-5=Cross-sectional view and plan view of MISFET of British example FIG. 1 3e 69a δ9b 3ζ Whistle Figure 2 for detailed explanation of the first invention - Figure 2 for detailed explanation of the invention Figure 41a 41b for detailed explanation of the first invention Figure 4 for explanation of the manufacturing method Figure 3: Process diagram for explaining an example of the manufacturing method Figure 3: Process diagram for explaining an example of the manufacturing method Figure 3: Process diagram for explaining an example of the manufacturing method Process diagram provided (Figure 3 CG) Process diagram used to explain the conventional technology Figure 5 Process diagram used to explain the conventional technology Figure 5 (1)) Whistle diagram used to explain the problems of the conventional technology Figure 6: Main part sectional view and plan view

Claims (9)

[Claims] (1) A laminate comprising a gate insulating film and a gate electrode forming material in this order on an active region of a first conductivity type semiconductor substrate, the laminate having at least two openings exposing a part of the active region. an insulating film is provided on the side walls of these openings, a second conductivity type region is provided in the semiconductor substrate portion below the opening, and the second conductivity type region is provided through the opening. an external wiring is provided in the MIS, and a gate electrode is formed in a portion of the gate electrode forming material other than the opening forming region.
FET. (2) The MISFET according to claim 1, wherein at least one of the openings is provided by removing a part of the laminate so that the entire side wall thereof is composed of the laminate. MISFET. (3) In the MISFET according to claim 1, at least one of the openings is formed of the laminate such that a part of the sidewall thereof is made of the element isolation insulating film and the other part is made of the laminate. A MISFET characterized in that it is provided by removing a part of the . (4) forming a laminate including a gate insulating film and a gate electrode forming material in this order over the entire active region of a semiconductor substrate of a first conductivity type, and exposing a part of the gate insulating film to the laminate; forming at least two openings, and introducing a second conductivity type impurity into the sample in which the openings have been formed to form a second conductivity type region in a portion of the semiconductor substrate under the openings; M characterized in that it includes a step of forming an insulating film on the side wall of the opening before or after forming the mold region.
ISFET manufacturing method. (5) The MISFET manufacturing method according to claim 4, wherein the gate electrode forming material is polysilicon, and the polysilicon is thermally oxidized to form the insulating film on the sidewall of the opening. manufacturing method. (6) In the MISFET manufacturing method according to claim 4, the formation of the laminate includes forming a gate insulating film and a gate electrode forming material in this order over the entire surface of the semiconductor substrate, and using the gate electrode forming material as a device. A method for manufacturing a MISFET, characterized in that the method is performed by etching back until it is flush with the upper surface of an isolation insulating film. (7) In the MISFET manufacturing method according to claim 4, after forming the laminate, an interlayer insulating film is formed on the entire surface of the substrate on which the laminate has been formed, and then the opening is formed on the interlayer insulating film. A method for manufacturing a MISFET characterized by the following. (8) In the MISFET manufacturing method according to claim 4 or 7, at least one of the openings is formed by removing a part of the laminate so that the entire side wall thereof is composed of the laminate. A method for manufacturing a MISFET, characterized by: (9) In the method for manufacturing a MISFET according to claim 4 or 7, at least one of the openings has a side wall partially composed of an element isolation insulating film and the other part composed of the laminate. A method for manufacturing a MISFET, characterized in that a part of the laminate is removed so as to form a MISFET.