JPH0417190A - Semiconductor device - Google Patents

Abstract

PURPOSE:To attain stable operation by providing a phase compensation circuit comprising a resistor and a capacitor of series connection to an output terminal of a differential amplifier circuit of a drive circuit being a component of a voltage limiter. CONSTITUTION:A phase compensation circuit consists of not only a capacitor but also a resistor. When a capacitor and a resistor connected in series therewith is used for phase compensation, recovery phase characteristics 81, 82 as shown in figure take place, and the delay in the phase of a differential amplifier circuit AMP is recovered at a cut-off frequency fc where the gain of the gain- frequency characteristic of the entire drive circuit without feedback is the unity. In consequence, a stable operation is assured attaining 45 deg. phase margin. Thus, a stable internal voltage is received even in the presence of external power voltage fluctuation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a voltage for lowering an external power supply voltage (hereinafter abbreviated as power supply voltage) within a chip and applying a low voltage to minute transistors within the chip. The present invention relates to a limiter, and relates to a voltage limiter that can obtain a stable internal power supply voltage (hereinafter abbreviated as internal voltage). [Prior Art] In recent years, as semiconductor integrated circuits have become more highly integrated, a decrease in breakdown voltage due to miniaturization of semiconductor elements has become a problem. This problem can be solved by lowering the power supply voltage of the semiconductor device, but this will result in incompatibility with other devices in terms of voltage. Therefore, a method has been proposed in which the power supply voltage applied from the outside is set to, for example, the conventionally widely used 5V, and an internal voltage lower than that (for example, 3.3V) is generated by the semiconductor device. Japanese Patent Publication No. 11363
61 describes an example in which this method is applied to a DRAM (dynamic random access memo) and an example of a circuit (voltage limiter) for generating an internal voltage from a power supply voltage. Figure 4 shows the above conventional example. A drive circuit diagram of a voltage limiter published in 2008 is shown.In the figure, VR is a reference voltage lower than the power supply voltage Vcc.The drive circuit generates an internal voltage V+, which has the same voltage value as VR and has a large drive capacity. It is a circuit that
Differential amplifier circuit A consisting of MOS transistors Q1 to Q5
, output MO8h transistor Q6 and MO for current extraction.
It is constituted by a buffer circuit B consisting of an S transistor Q7. Of the two input terminals of differential amplifier circuit A, Vn is connected to one, and VL, which is the internal voltage within the chip, is fed back to the other, so this circuit maintains the internal voltage ■L.
operates so as to follow the reference voltage Vn. The driving ability of the voltage limiter is determined by the channel width of output MOS transistor Q6. Therefore, if the channel width of Q6 is designed to match the current consumption of the load, the internal voltage VL can be supplied to the load circuit. [Problem to be Solved by the Invention 1] In the prior art as shown above, stability of the operation of the voltage limiter is not considered. This will be explained below using FIGS. 4 and 5. Figure 4 shows a two-legged voltage limiter and a DRAM as an example of a load circuit for this.The internal circuit in the chip has a capacitance of 650 pF and a current of 50 mA constantly flows.
It is equivalently expressed as +. FIG. 5 shows the gain and phase frequency characteristics of the circuit shown in FIG. 4. The solid line in the figure represents the gain and phase-frequency characteristics of the entire drive circuit when no feedback is applied (open loop). The characteristics shown by the broken line and the dot-dashed line are the gain of the differential amplifier circuit A and the buffer circuit B shown in FIG. 4, respectively.
This is a phase-frequency characteristic, and the sum of the frequency characteristics of the differential amplifier circuit A and the buffer circuit B becomes the gain and phase frequency characteristic of the entire drive circuit. Here, at a frequency (cutoff frequency) at which the gain is 1 (OdB), a value indicating how much margin there is for a phase delay of 180° is the phase margin. In this example, the difference in the gain-frequency characteristic bands of differential amplifier circuit A and buffer circuit B is only about one order of magnitude, so even if the phase margin is positive, the margin is small (10°).
Operation becomes unstable (if the phase margin is negative, the feedback amplifier will oscillate). Generally, in order to operate stably, a phase margin of 45° or more is required. The voltage limiter's mission is to supply a stable internal voltage to the internal circuits, so it must not oscillate or become unstable. As a countermeasure to this problem, as shown in Figure 3,
There is a method of inserting a capacitor Co in parallel to the load circuit to lower the band of the gain-frequency characteristic of the buffer circuit B to perform phase compensation. However, this compensation capacitance Co is approximately 10,000 pF.
and a large capacity is required. The frequency characteristics at this time are shown in FIG. As can be seen from the figure, the band of the gain-frequency characteristic of buffer circuit B is lowered by about -0 orders of magnitude compared to before phase compensation, and the band of the gain-frequency characteristic of differential amplifier circuit A and buffer circuit B is lower than that before phase compensation. The difference can be as small as two fingers. With this phase compensation, a phase margin of 45° can be secured. On the other hand, as shown in FIG. 2, a method may be considered in which a capacitor Cp is inserted into the output terminal of the differential amplifier circuit A to perform phase compensation. However, in a voltage limiter like the one mentioned above whose load is the internal circuit inside the RAM chip, it is still about 10,000 pF.
compensation capacity is required. Figure 7 shows the gain at this time,
Shows phase-frequency characteristics. However, it has been found that the phase compensation method shown in FIG. 2 not only requires a large CF but also has difficulty in stabilizing the internal voltage within the chip against fluctuations in the power supply voltage. This is shown in FIG. Figure 9 shows the internal voltage V for the high frequency power supply voltage fluctuation of the circuit in Figure 2.
It shows the variation of L. As can be seen from the figure, the internal voltage v within the chip output from the voltage limiter fluctuates greatly in response to fluctuations in the high-frequency power supply voltage. This is presumed to be because the band of the gain-frequency characteristic of the differential amplifier circuit A has become too low in FIG. 7, and the differential amplifier circuit A is no longer able to follow high-frequency power supply voltage fluctuations. In this way, in order to guarantee stable operation, it is sufficient to secure a phase margin of 45 degrees or more through phase compensation, but since this requires a very large capacitance value of 10,000 pF or more, Putting this capacity into
This is not practical in terms of layout area. An object of the present invention is to solve the above problems and provide a voltage limiter with stable operation. Means for Solving the Problems 1 In order to solve the above problems, in the present invention, a phase compensation circuit consisting of a resistor and a capacitor connected in series is installed at the output terminal of the differential amplifier circuit of the drive circuit constituting the voltage limiter. [Function] By connecting a phase compensation capacitor and a resistor in series with the output terminal of the differential amplifier circuit of the drive circuit that constitutes the voltage limiter, the compensation capacitance can be made extremely small, and even when fluctuations in the power supply voltage occur, the compensation capacitance can be made extremely small. It was discovered that a stable internal voltage could be supplied. This makes it possible to integrate the phase compensation circuit in the voltage limiter into a single conductor device. [Example] FIG. 1 shows an example of the present invention. The drive circuit that constitutes the voltage limiter includes a differential amplifier circuit AMP consisting of MOS transistors Q^ to QE, and an output MO81 to transistor QF.
(Channel width/Channel length=3000/1.2) and a buffer circuit BF consisting of Mo5t for current extraction to transistor Qa. Vcc' is the power supply voltage, Φ
1' is a signal that controls the operation mode of the drive circuit. V
n' is a reference voltage for obtaining the internal voltage VL'' (same voltage value as V R'). Taking a DRAM as an example of the load circuit of the drive circuit, the internal voltage V L '
The circuit inside the DRAM chip whose power source is C+,'
(650 pF) and current source IL' (50 mA). Rc and Cc are phase compensation resistors (30
0Ω) and capacitance (20pF). A feature of the present invention is that the phase compensation circuit is configured by adding not only a capacitor but also a resistor. FIG. 8 shows the gain and phase frequency characteristics of the circuit shown in FIG. The solid line in the figure represents the gain and phase-frequency characteristics of the entire drive circuit when no feedback is applied. The characteristics shown by the broken line and the dot-dashed line are the gain and phase-frequency characteristics of the differential amplifier circuit AMP and buffer circuit BF shown in FIG. 1, respectively. As shown in Figure 8, if we include a capacitor and a resistor connected in series with it as shown in Figure 1 as phase compensation, we get
A recovery phenomenon around the phase as shown at 81.82 in Fig. 8 occurs, and the differential It is possible to recover the phase delay of the amplifier circuit AMP, thereby providing a phase margin of 45° and ensuring stable operation. The value of the compensation capacitance at this time can be reduced by about three orders of magnitude compared to the case of compensation using only capacitance as shown in FIG. 2, so the layout area of the phase compensation circuit can be made extremely small. Figure 10 shows the internal voltage V with respect to high frequency power supply voltage fluctuations.
It shows the fluctuation of L'. As can be seen from the figure, almost no voltage fluctuation occurs in the internal voltage V L ' even with high-frequency power supply voltage fluctuations. This is because, in the embodiment according to the present invention shown in FIG. 1, as shown in FIG. 8, there is no need to lower the band of the gain-frequency characteristic of the differential amplifier circuit AMP. This can be considered to be because the differential amplifier circuit AMP is able to follow the same. As described above, when phase compensation is performed on the output side of the differential amplifier circuit AMP, the phase compensation capacitance can be reduced by about three orders of magnitude by adding a resistor in series with the phase compensation capacitor. Furthermore, even if there are high-frequency power supply voltage fluctuations, a stable internal voltage can be supplied. In addition, in the above embodiment, the values of Rc and Cc are not necessarily arbitrary. That is, the train conductance of the PMOS transistor Q^ of the differential amplifier circuit AMP is gds^, the train conductance of the NMO8I-transistor Qc is gdsc, and the output PMOS of the buffer circuit is
The train conductance of transistor Q is g as
F and rasA1/g dsΔ, rd, respectively
Sc= 1/gdscs 1-dSF= 1/
Defined as gdsF, ras^ and r dsc are the pole frequency of the differential amplifier circuit determined by the resistor connected in parallel and the gate capacitance Ca of the output PMOS transistor QF of the buffer circuit (in the gain-frequency characteristics of the differential amplifier circuit,
The frequency at which the gain decreases by -3 dB with respect to the value at low frequencies) is expressed as fP (fP1'; 1/(2π(rasAr
asc/ (rds8+ to rdsc) ) C
c) ), the pole frequency of the buffer circuit determined by rd8F and load capacitance CI,' is fP, (fP,
L:1/ (2πr, +sFc%)), the zero point frequency generated by inserting Rc and Cc is expressed as fz, (fz, = 1
/ (2πRcCc)), and if fC is the frequency at which the gain of the entire drive circuit without feedback is 1 (OdB), first, as explained in Figs. 9 and 10, the power supply voltages (Vcc, Vcc ) It is desirable to set fP2<fP□ from the viewpoint of stability against fluctuations in (condition I). Also, as can be seen by comparing Figures 5 and 8. By inserting Rc and Cc, the apparent pole frequency fP1' of the differential amplifier circuit AMP moves to the vicinity of fP2. Here, fP
When 1'<fP2, the band of the differential amplifier circuit AMP decreases and the operating speed becomes slower than that of the buffer circuit BF, which causes a problem in stability against fluctuations in the power supply voltage. Therefore, it is desirable that fP2<fP□' (condition ■). On the other hand, as shown in FIG. 8, the zero point frequency fz. is the inflection point of the gain-frequency characteristic of the differential amplifier circuit AMP after phase compensation, and f Pl, '< f Zl, so Rc, C input to the output terminal of the differential amplifier circuit AMP
The zero point frequency fz due to c becomes fP2<fz□ (condition ■'). Furthermore, since the recovery phenomenon around the phase shown in Figure 8 occurs near fzl, if fC<fzl, phase compensation will be performed at a frequency where the gain of the entire drive circuit is 1 (OdB) or less, which is ineffective. . Therefore, fz□<
It is desirable to set f c (condition ■). Taking the above conditions together, it can be seen that the relationship between the respective frequencies is approximately fP2<fz□<fc. The gain at the zero point frequency fZ of the characteristics of the differential amplifier circuit shown in FIG. 8 is determined by the parallel resistances of rds^, rdsc, and Rc, and increases or decreases as the value of Re increases or decreases. On the other hand, the apparent pole frequency fP□″ of the differential amplifier is ra
Determined by the parallel resistance of s^ and r asC and Cc + Ca (f
P,' valve 1/ (2π(rdsAr, +sc/ (r
as^+rasc))(C,c+ca))) becomes lower as Cc increases. Now, when deciding on an appropriate fz, if Rc is made too small, Cc will become large, and fP,'<
fP2, and the above condition (2) cannot be satisfied. Therefore, it is desirable that Rc be set to a value that allows fP□' to be larger than fP as much as possible. In the embodiment of the present invention shown in FIG. 1, the polar frequency fP2 of the buffer circuit is determined as (rdsF E 1
/ g dsF, then fP, valve 1/(2πr d
sFCL' )) is determined by the drain conductance g asF of the PMO3 transistor QF and the load capacitance CL' (NMO8I-transistor Qc in Fig. 1).
(The impedance of the PMOS transistor QF is sufficiently higher than that of the PMOS transistor QF), but is generally given by the product of the output impedance X2 of the buffer circuit and the load capacitance CL'. Here, the capacitance used in the phase compensation circuit shown in FIG. 1 will be explained. These capacitors need to have fairly large capacitance and low voltage dependence. FIG. 11(a) shows one method for realizing this using a normal CMOS process. In the figure, 1 is a P-type semiconductor substrate, 2 is an N
3 is a type well, 3 is an N+ diffusion layer, 4 is SiO2 for isolation, 5 is a gate insulating film, and 6 is a gate electrode. The capacitor is formed between the gate electrode 6 and the substrate surface with the gate insulating film 5 in between, like a normal MO8 capacitor. Since a thin gate insulating film is used as the capacitive insulating film, a large capacitance can be obtained with a relatively small area. However, the difference from the MO8 capacitor is that the threshold voltage is negative because there is an N well under the gate electrode. This will be explained using FIG. 11(b). The horizontal axis is the voltage applied to the capacitance (positive on the gate electrode side), and the vertical axis is the capacitance. The threshold voltage (flat band voltage) is the applied voltage when the capacitance changes significantly■. However, V,
<O. Therefore, as long as a voltage is applied in one direction so that the gate electrode side is positive, the capacitance is almost constant. If a bidirectional voltage can be applied, two capacitors shown in FIG. 11(a) may be used and connected in parallel in opposite directions as shown in FIG. 11(c). The steps necessary to create the capacity of this example are well formation,
The steps of forming isolashimin region, forming gate insulating film, forming gate electrode, forming diffusion layer, and wiring,
These are all steps included in a normal CMOS process. Therefore, if the semiconductor device is manufactured using a CMOS process, there is no need to add any special steps to create this capacitance. Further, depending on the semiconductor device to which the present invention is applied, a stacked capacitor may be used. For example, a DRAM uses a stacked capacitor as a storage capacitor of a memory cell formed on the surface of a semiconductor substrate. In such a case, a laminated capacitor may be used as a phase compensation capacitor. Regarding DRAM using stacked capacitance, see IE Journal of Solid
State Circuits, SC Volume 15, No. 4, No. 66
Pages 1 to 666, August 1980 (IEEE J
internal ofSolid 5tate C
1rcuits. Vol, 5C-22, No, 3. pp, 661-666
, Aug, 1980). [Effects of the Invention] As explained above, according to the present invention, the value of the phase compensation capacitance can be made extremely small. Furthermore, a stable internal voltage can be supplied even if there are external power supply voltage fluctuations.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figures 2 and 3 are circuit diagrams showing one embodiment of the present invention.
4 is a drive circuit diagram for explaining the conventional example, FIG. 5 is a gain characteristic diagram and a phase-frequency characteristic diagram of the circuit shown in FIG. 4, and FIG. 6 is a circuit diagram of a conventional phase compensation method. The figure shows the gain characteristic diagram and phase-frequency characteristic diagram of the circuit shown in Figure 3, Figure 7 shows the gain characteristic diagram and phase-frequency characteristic diagram of the circuit shown in Figure 2, and Figure 8 shows the diagram of the circuit shown in Figure 1. FIG. 9 is a diagram showing the gain characteristic diagram and phase-frequency characteristic diagram of the circuit according to the embodiment of the present invention, FIG. FIG. 11 is a cross-sectional schematic diagram of the phase compensation capacitor shown in FIG. 1 realized by a normal CMOS process, and the above ( Toaki (9 ゛ ん 9 θ 幇 1 character ('ap>rt invitation (qa) ri threatening mouth Y (9″p) 5) i [1! (A>Tom (A) 1

Claims (1)

[Claims] 1. A differential amplifier circuit that amplifies the voltage difference between one input of the reference voltage and the other input, and an internal power supply voltage controlled by the output of this differential amplifier circuit. In a semiconductor device having a built-in drive circuit consisting of a buffer circuit that outputs an internal power supply voltage and feeds back this internal power supply voltage as the other input of the differential amplifier circuit, the output terminal of the differential amplifier circuit is connected from a series connection of a resistor and a capacitor. A semiconductor device characterized in that a circuit is added thereto. 2. In the semiconductor device according to claim 1,
If the pole frequency determined by the output impedance of the buffer circuit described above is f_P_2, the zero point frequency of the circuit consisting of a series connection of a resistor and a capacitor is f_Z_1, and the frequency at which the gain of the entire drive circuit is 1 is f_C, f_P_2<f_Z.
A semiconductor device characterized in that _1<f_C.