CN113917970A - Output buffer circuit, voltage-stabilizing active bias circuit and active bias circuit - Google Patents
Output buffer circuit, voltage-stabilizing active bias circuit and active bias circuit Download PDFInfo
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- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The application discloses an output buffer circuit, a voltage-stabilizing active bias circuit and an active bias circuit, wherein the voltage-stabilizing active bias circuit comprises an output buffer circuit, a temperature compensation circuit connected with the output buffer circuit and a series feedback circuit connected with the output buffer circuit, has the advantages of simple structure, small size, small static power consumption, adjustable output bias voltage, strong portability and the like, and improves the practicability of a voltage-stabilizing active bias circuit module; the active bias circuit comprises an output buffer circuit and a voltage-stabilizing active bias module connected with the output buffer circuit, wherein the voltage-stabilizing active bias module integrates the functions of temperature suppression and power supply fluctuation, the circuit structure is simpler, more adjustable free parameters are provided, and the GaAs PHEMT radio frequency amplifier can be easily integrated.
Description
Technical Field
The application belongs to the technical field of microelectronics, semiconductors and communication, and relates to a voltage-stabilizing active bias circuit based on a GaAs PHEMT process.
Background
The active bias circuit is generally used in a radio frequency/microwave amplifier, mainly provides stable direct current bias for the amplifier, and effectively reduces the influence of the amplifier along with temperature and process parameter fluctuation, so that the research on the high-performance bias circuit has great application prospect and practical significance.
The common device process types of amplifiers commonly used in amplifiers at present are GaAs PHEMT, SiGe HBT and CMOS. SiGe HBTs and CMOS are typically used for cost and process compatibility reasons that are inferior to GaAs PHEMT in terms of noise performance and high frequency gain, while amplifiers are typically implemented using GaAs PHEMT technology for better performance. In order to realize process compatibility, the process of the active bias circuit needs to be realized based on GaAs PHEMT.
The active bias circuit is an important component of the amplifier, mainly affects the static working point of a main amplifying tube in the amplifier, and directly determines the performance index of the amplifier. The active bias circuit is required to work stably, the output bias voltage Vb is not interfered by various factors such as environmental temperature change, device process parameter deviation, power supply voltage fluctuation number and the like, and the traditional current mirror active bias circuit can well compensate the change of the threshold voltage of the amplifying tube along with the temperature, weaken the interference of the environmental temperature change and eliminate the device process deviation. However, the conventional current mirror active bias circuit is greatly influenced by power supply fluctuation, and application scenarios of the conventional current mirror active bias circuit are limited. Therefore, the development of a voltage-stabilizing active bias circuit which does not change with the ambient temperature and has device process parameter deviation is an urgent technical problem to be solved.
Disclosure of Invention
In order to solve the technical problem, the technical scheme adopted by the application is as follows:
the first aspect of the embodiment of the present application provides an output buffer circuit, where the buffer circuit includes transistors M4 and M5, resistors R4 and M4 adopt GaAs E-PHEMT technology, and M5 adopts GaAs D-PHEMT technology;
the source electrode of the transistor M5 is connected with a power supply end, and the grid electrode of the transistor M1 is connected with the drain electrode of the transistor M5;
the grid electrode and the drain electrode of the transistor M4 are connected and then connected with the drain electrode of the transistor M5;
the upper end of the resistor R4 is connected with the source of the transistor M4, and the lower end is grounded.
A second aspect of the embodiments of the present application provides a voltage-stabilizing active bias circuit, including the above-mentioned output buffer circuit, a temperature compensation circuit connected to the output buffer circuit, and a series feedback circuit connected to the output buffer circuit; the upper ends of the series feedback structure, the temperature compensation circuit and the output buffer circuit are all connected with the power supply end of the power supply, and the lower ends are grounded; the power supply end of the power supply is connected with decoupling capacitors C1 and C2 in parallel, and the drain electrode of the transistor M5 of the output buffer circuit draws a bias voltage Vb through a resistor R5.
Further, in the embodiments provided in the present application, the series feedback structure includes transistors M1 and M2, and resistors R1 and R2, M1 and M2 adopt GaAs E-PHEMT technology;
the resistors R1 and R2 are connected in series and then connected with the drain of the transistor M1, wherein the upper end of the resistor R1 is connected with the power supply end of a power supply, and the lower end of the resistor R1 is connected with the grid of the transistor M1;
the drain of the transistor M1 is connected with the gate of the transistor M5 in the output buffer circuit;
the gate and the drain of the transistor M2 are connected to the source of the transistor M1, and the source of the transistor M2 is grounded.
Further, in the embodiment provided by the present application, a single diode or a plurality of diodes are connected in series in parallel at the source of the transistor M1 instead of the transistor M2.
Further, in the embodiments provided in the present application, the temperature compensation circuit includes a transistor M3, resistors R3 and M3 using GaAs E-PHEMT technology;
the upper end of the resistor R3 is connected with the power supply end of a power supply, and the lower end of the resistor R3 is connected with the drain electrode of the transistor M3;
the gate and the drain of the transistor M3 are connected to the drain of the transistor M5 in the output buffer circuit, and the source of the transistor M3 is grounded.
Further, in the embodiment provided in the present application, a plurality of diodes or a plurality of diodes are connected in series to the drain of the transistor M5 instead of the transistor M4.
A third aspect of the embodiments of the present application provides an active bias circuit, including the above-mentioned output buffer circuit, and a voltage-stabilizing active bias module connected to the output buffer circuit;
the upper ends of the voltage-stabilizing active bias module and the output buffer circuit are both connected with the power supply end of the power supply, and the lower ends are grounded;
the power supply end of the power supply is connected with decoupling capacitors C1 and C2 in parallel, and the drain electrode of the transistor M5 of the output buffer circuit draws a bias voltage Vb through a resistor R5.
Further, in the embodiments provided herein, the voltage stabilizing active bias module includes transistors M1, M2, M3 and resistors R1, R2, R3;
the resistors R1 and R2 are connected in series and then connected with the drain of the transistor M1, wherein the upper end of the resistor R1 is connected with the power supply end;
the grid electrode and the drain electrode of the transistor M2 are connected and then connected with the source electrode of the transistor M1, and the source electrode of the transistor M2 is grounded;
the upper end of the resistor R3 is connected with the grid of the transistor M1, and the lower end is grounded;
the drain of the transistor M3 is connected with the power supply end, the source of the transistor M3 is connected with the gate of the transistor M1, and the gate of the transistor M3 is connected with the serial connection position of the resistors R1 and R2.
Further, in the embodiment provided by the present application, a single diode or a plurality of diodes are connected in series in parallel at the source of the transistor M1 instead of the transistor M2.
Further, in the embodiment provided in the present application, a plurality of diodes or a plurality of diodes are connected in series to the drain of the transistor M4 instead of the transistor M5.
According to the voltage-stabilizing active bias circuit, a drain node of a transistor M1 outputs a static voltage which does not fluctuate along with a power supply Vcc through a series feedback circuit connected by a single tube, the flatness of the output bias voltage Vb which does not change along with the power supply can be changed by an adjusting resistor R2, a resistor R1 is used for compensating drain currents of transistors M1 and M2 which change along with the temperature, and the grid and the drain of a transistor M2 are connected to raise the static voltage of the drain node of a transistor M1; on the other hand, the source voltage of the transistor M1 is embedded in a fixed voltage value, the resistor R3 is connected with the transistor M3 in a diode connection mode in series, the resistor R3 is a temperature compensation resistor and used for compensating the change of the threshold voltage of the transistor M3 at high and low temperatures, the grid electrode of the transistor M3 is led out through the resistor R5 and connected with the grid electrode of the amplifying tube, the two transistors form a current mirror active bias circuit structure, the buffer output circuit outputs through the drain electrode of the transistor M5, the resistor R4 is connected with the transistor M4 in a diode connection mode in series, the size of the bias output voltage Vb is controlled by adjusting the value of the resistor R4, and the amplitude of the output voltage Vb can be improved through the connection mode of the transistor M4.
The mode of combining the series feedback structure and the temperature compensation circuit is adopted to inhibit the fluctuation of the power supply voltage and the influence of the change of the environmental temperature, and simultaneously, the method is also beneficial to adjusting and improving the compensation degree of the change of the environmental temperature and the flatness of the output voltage along with the fluctuation of the power supply voltage, and greatly improves the stability of the amplifier along with the change of the environment. The structure of the voltage stabilizing circuit and the temperature compensation circuit can be independently adjusted, and the freedom of adjusting the performance index of the bias circuit is greatly improved. The voltage-stabilizing active bias circuit has the advantages of simple structure, small size, small static power consumption, adjustable output bias voltage, strong portability and the like, and improves the practicability of the voltage-stabilizing active bias circuit module.
The application provides an active bias circuit, the fluctuation function of restraining temperature variation and mains voltage is realized through steady voltage active bias module, temperature compensation effect is realized through resistance R1, the compensation effect under the different temperatures can be changed to the size of adjusting resistance R1 resistance, the static voltage that M5 pipe is used for raising at M1's source is connected to the form of M2 diode connection, the undulant degree along with power supply of output bias voltage Vb can be adjusted to the size of resistance R2, M1 forms the form of feedback connection with M3, the bias voltage Vb of stable output, transistor M1's feedback degree can be realized to resistance R3. The output bias voltage Vb is realized by adjusting the size of the transistor M4 and the resistor R4.
The voltage-stabilizing active bias module and the output buffer circuit are adopted to inhibit the influence of temperature and voltage source fluctuation, the output buffer circuit can independently adjust the size of output bias voltage and is not controlled by the voltage-stabilizing active bias circuit module, the voltage-stabilizing active bias module integrates the functions of inhibiting temperature and power supply fluctuation, the circuit structure is simpler, more adjustable free parameters are provided, and the integration of the GaAs PHEMT radio frequency amplifier can be easily realized.
Additional advantages, objects, and features of the application will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a voltage-stabilizing active bias circuit according to the present application;
FIG. 2 is a simulation result of variation of a bias voltage Vb output by a stabilized active bias circuit with Vcc under a three-temperature condition;
FIG. 3 is a schematic diagram of an active bias circuit of the present application;
fig. 4 is a simulation result of variation of the output bias voltage Vb of the active bias circuit with Vcc under a three-temperature condition.
Detailed Description
The present application will now be described in further detail with reference to the accompanying drawings, whereby one skilled in the art can, with reference to the description, make an implementation.
It will be understood that terms such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
The terms "upper end" and "lower end" in the description and claims of the embodiments of the present invention are used for convenience in understanding the technical solutions, and are explained based on the drawings of the specification, rather than being used for describing a specific direction of an object.
The technical solution of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.
The first aspect of the embodiment of the present application provides an output buffer circuit, where the buffer circuit includes transistors M4 and M5, resistors R4 and M4 adopt GaAs E-PHEMT technology, and M5 adopts GaAs D-PHEMT technology; the source electrode of the transistor M5 is connected with a power supply end, and the grid electrode of the transistor M1 is connected with the drain electrode of the transistor M5; the grid electrode and the drain electrode of the transistor M4 are connected and then connected with the drain electrode of the transistor M5; the upper end of the resistor R4 is connected with the source of the transistor M4, and the lower end is grounded.
In a second aspect of the embodiments of the present application, as shown in fig. 1, a voltage-stabilizing active bias circuit is provided, which includes the above-mentioned output buffer circuit, a temperature compensation circuit connected to the output buffer circuit, and a series feedback circuit connected to the output buffer circuit; the upper ends of the series feedback structure, the temperature compensation circuit and the output buffer circuit are all connected with the power supply end of the power supply, and the lower ends are grounded; the power supply end of the power supply is connected with decoupling capacitors C1 and C2 in parallel, and the drain electrode of the transistor M5 of the output buffer circuit draws a bias voltage Vb through a resistor R5.
Further, in the embodiments provided in the present application, the series feedback structure includes transistors M1 and M2, and resistors R1 and R2, M1 and M2 adopt GaAs E-PHEMT technology; the resistors R1 and R2 are connected in series and then connected with the drain of the transistor M1, wherein the upper end of the resistor R1 is connected with the power supply end of a power supply, and the lower end of the resistor R1 is connected with the grid of the transistor M1; the drain of the transistor M1 is connected with the gate of the transistor M5 in the output buffer circuit; the gate and the drain of the transistor M2 are connected to the source of the transistor M1, and the source of the transistor M2 is grounded.
Further, in the embodiment provided by the present application, a single diode or a plurality of diodes are connected in series in parallel at the source of the transistor M1 instead of the transistor M2.
Further, in the embodiments provided in the present application, the temperature compensation circuit includes a transistor M3, resistors R3 and M3 using GaAs E-PHEMT technology; the upper end of the resistor R3 is connected with the power supply end of a power supply, and the lower end of the resistor R3 is connected with the drain electrode of the transistor M3; the gate and the drain of the transistor M3 are connected to the drain of the transistor M5 in the output buffer circuit, and the source of the transistor M3 is grounded.
Further, in the embodiment provided in the present application, a plurality of diodes or a plurality of diodes are connected in series to the drain of the transistor M5 instead of the transistor M4.
Specifically, decoupling capacitor C1, C2 filtering power clutter prevent the influence of power stray fluctuation to steady voltage active bias circuit module in the series feedback structure: the power supply of the power supply terminal forms a ground loop through the resistors R1 and R2, the diode-connected transistor M2 and the diode-connected transistor M1, and the transistors M1 and M2 are both in a diode-connected form and therefore are in a saturated state. The output voltage of the drain node of the transistor M1 provides a gate voltage for the transistor M5, the value of the resistor R1 is adjusted, and the die sizes of the transistors M1 and M2 can control the gate voltage of the transistor M5, and further control the saturation degree of the transistor M5.
When Vcc is increased, if the grid voltage of M1 is not changed, the voltage V of A pointARising; actually raise VDCVoltage V at point BBWith the increase of the voltage of the grid electrode of M1, the current passing through M1 is increased due to the connection of the B point and the grid electrode of M1, VA can be reduced by adjusting the values of the resistors R1 and R2 appropriately, the output bias voltage Vb can be reduced accordingly, and meanwhile, the increase of the bias current of M1 caused by the increase of Vcc is effectively restrained due to the reduction of Vb which is led out to provide the bias voltage for the grid electrode of the amplifying tube.
When the ambient temperature decreases, the current on the branches of the transistors M1 and M2 increases, which results in the voltage on the resistors R1 and R2 increasing, and the gate voltage V of the transistor M5 increasingAThe output bias voltage Vb is reduced, and the upward offset of the current of the main amplifier tube caused by the temperature reduction is restrained, so that the fluctuation of the quiescent bias current of the amplifier along with the temperature is restrained.
Specifically, in the temperature compensation circuit, a power supply at a power supply end forms a ground circuit through a resistor R3 and a transistor M3 connected in a diode mode, the drain voltage of the transistor M1 is led out and connected to the grid of a main amplifying tube to provide a proper bias voltage, the sizes of the tube cores of the resistors R3 and M3 are adjusted, the size of the led-out voltage can be adjusted, the leading-out end of the transistor M3 and the main amplifying tube form a traditional current mirror circuit, when the temperature rises, the current flowing through a branch circuit increases, the voltage drop of the resistor R3 increases, the leading-out voltage of the transistor M3 is reduced, the bias Vb voltage output by the voltage stabilization active bias module decreases, and the increase of the leakage current of the amplifying tube is weakened.
Specifically, in the output buffer circuit, a power supply forms a branch circuit through a transistor M5, a diode-connected transistor M4 and a resistor R4, the gate voltage of the transistor M5 is provided by a series feedback structure, the output voltage Vb of the voltage-stabilizing active bias circuit module circuit is led out from the drain of the transistor M5, and the transistor M4 and an amplifying tube form a current mirror circuit, so that the change of the drain current of the amplifying tube can be compensated.
The working principle is as follows:
series feedback architecture primarily suppresses VAThe point voltage changes along with the change of a power supply Vcc, and meanwhile, the fluctuation of the current of an amplifying tube along with the temperature can be compensated;
the temperature compensation circuit and an amplifying tube in the amplifier form a classical current mirror circuit which is used for compensating the change of the threshold voltage of the amplifying tube along with the temperature so as to stabilize the current in the amplifier, the voltage led out by the temperature compensation circuit is connected with a series feedback structure and the output voltage of an output buffer circuit in parallel, and the combined action mechanism of the three structures controls the bias voltage Vb of the voltage stabilization active bias circuit module;
the output voltage of the output buffer circuit is led out from the drain electrode of the M5, the resistor R4 and the transistor M4 can adjust the output bias voltage Vb, and the resistor R5 is used for isolating the output voltage of the voltage-stabilizing active bias module from the radio-frequency signal and preventing the influence of the crosstalk of the radio-frequency signal on the bias voltage.
The embodiment of the application provides a simulation result curve of a voltage-stabilizing active bias circuit, as shown in fig. 2, the scanning voltage range set by Vcc is 0-8V, and it can be seen from the simulation result curve that when the Vcc variation range is 2-8V, the output voltage Vb of the voltage-stabilizing active bias circuit is stable along with the variation trend of the power supply voltage, the output voltage Vb of the voltage-stabilizing active bias circuit is reduced along with the rise of the temperature, the current difference caused by the threshold voltage of an amplifier along with the variation of the temperature is compensated, and the purpose of stabilizing the static working voltage is achieved.
In a third aspect of the embodiments of the present application, as shown in fig. 2, an active bias circuit is provided, which includes the above-mentioned output buffer circuit, and a voltage-stabilizing active bias module connected to the output buffer circuit;
the upper ends of the voltage-stabilizing active bias module and the output buffer circuit are both connected with the power supply end of the power supply, and the lower ends are grounded;
the power supply end of the power supply is connected with decoupling capacitors C1 and C2 in parallel, and the drain electrode of the transistor M5 of the output buffer circuit draws a bias voltage Vb through a resistor R5.
Further, in the embodiments provided herein, the voltage stabilizing active bias module includes transistors M1, M2, M3 and resistors R1, R2, R3;
the resistors R1 and R2 are connected in series and then connected with the drain of the transistor M1, wherein the upper end of the resistor R1 is connected with the power supply end;
the grid electrode and the drain electrode of the transistor M2 are connected and then connected with the source electrode of the transistor M1, and the source electrode of the transistor M2 is grounded;
the upper end of the resistor R3 is connected with the grid of the transistor M1, and the lower end is grounded;
the drain of the transistor M3 is connected with the power supply end, the source of the transistor M3 is connected with the gate of the transistor M1, and the gate of the transistor M3 is connected with the serial connection position of the resistors R1 and R2.
Further, in the embodiment provided by the present application, a single diode or a plurality of diodes are connected in series in parallel at the source of the transistor M1 instead of the transistor M2.
Further, in the embodiment provided in the present application, a plurality of diodes or a plurality of diodes are connected in series to the drain of the transistor M4 instead of the transistor M5.
Specifically, decoupling capacitors C1 and C2 filter power noise waves and prevent power supply stray from influencing a voltage stabilizing active bias circuit module, in the voltage stabilizing active bias module, when a bias circuit normally works, a power supply forms a ground loop through a resistor R1 and a R2 transistor M1 and M2, in the other branch, the power supply forms a ground loop through a transistor M3 and a resistor R3, and a transistor M1 branch and a transistor M3 branch form a feedback structure.
When the ambient temperature rises, the current of the branch where the transistor M1 is located increases, the voltage drop of the resistor R1 increases, the gate voltage of the transistor M3 decreases, and the current of the branch where the transistor M3 is located is weakened, at this time, the voltage drop of the resistor R3 decreases, which may result in the weakening of the turn-on degree of the transistor M1, and the current flowing through the branch of the transistor M1 decreases due to the adjustment of the feedback structure, so that the gate voltage of the transistor M3 is compensated.
Specifically, in the output buffer circuit, a power supply forms a ground loop through a transistor M4 and a resistor M5R 4, the resistor R4 adjusts the magnitude of the output bias voltage, and the transistor M5 and an amplifying tube in the amplifier form a current mirror circuit to compensate the current difference caused by the change of the threshold voltage of the amplifying tube along with the temperature.
According to the simulation result curve of the active bias circuit in the embodiment of the application, as shown in fig. 4, the scanning voltage range set by Vcc is 0-12V, and it can be seen from the simulation result curve that when the Vcc variation range is 4-14V, the output voltage Vb of the active bias circuit changes steadily along with the fluctuation of the power supply voltage, and the output voltage Vb of the active bias circuit does not change along with the temperature, so that a stable bias voltage source with the output bias voltage Vb not fluctuating along with the temperature and the power supply is achieved.
Although the embodiments of the present application have been disclosed above, they are not limited to the applications listed in the description and the embodiments. It can be applied in all kinds of fields suitable for the present application. Additional modifications will readily occur to those skilled in the art. Therefore, the application is not limited to the specific details and illustrations shown and described herein, without departing from the general concept defined by the claims and their equivalents.
Claims (10)
1. An output buffer circuit is characterized by comprising transistors M4 and M5, a resistor R4;
the source electrode of the transistor M5 is connected with a power supply end, and the grid electrode of the transistor M1 is connected with the drain electrode of the transistor M5;
the grid electrode and the drain electrode of the transistor M4 are connected and then connected with the drain electrode of the transistor M5;
the upper end of the resistor R4 is connected with the source of the transistor M4, and the lower end is grounded.
2. A voltage-stabilizing active bias circuit comprising the output buffer circuit of claim 1, a temperature compensation circuit connected to the output buffer circuit, a series feedback circuit connected to the output buffer circuit;
the upper ends of the series feedback structure, the temperature compensation circuit and the output buffer circuit are all connected with the power supply end of the power supply, and the lower ends are grounded;
the power supply end is connected with decoupling capacitors C1 and C2 in parallel, and the drain electrode of the transistor M5 of the output buffer circuit draws bias voltage through a resistor R5.
3. The regulated active bias circuit of claim 2, wherein said series feedback structure comprises transistors M1, M2, resistors R1, R2;
the resistors R1 and R2 are connected in series and then connected with the drain of the transistor M1, wherein the upper end of the resistor R1 is connected with the power supply end of a power supply, and the lower end of the resistor R1 is connected with the grid of the transistor M1;
the drain of the transistor M1 is connected with the gate of the transistor M5 in the output buffer circuit;
the gate and the drain of the transistor M2 are connected to the source of the transistor M1, and the source of the transistor M2 is grounded.
4. A regulated active bias circuit according to claim 3, wherein said transistor M2 is replaced by a diode or diodes connected in series in parallel at the source of said transistor M1.
5. The voltage-stabilizing active bias circuit of claim 2, wherein the temperature compensation circuit includes a transistor M3, a resistor R3;
the upper end of the resistor R3 is connected with the power supply end of a power supply, and the lower end of the resistor R3 is connected with the drain electrode of the transistor M3;
the gate and the drain of the transistor M3 are connected to the drain of the transistor M5 in the output buffer circuit, and the source of the transistor M3 is grounded.
6. The active bias circuit for voltage regulation according to claim 2, wherein the transistor M4 is replaced by a plurality of transistors in the form of diodes or a plurality of diodes connected in series to the drain of the transistor M5.
7. An active bias circuit, comprising the output buffer circuit of claim 1, a voltage-stabilizing active bias module connected to the output buffer circuit;
the upper ends of the voltage-stabilizing active bias module and the output buffer circuit are both connected with the power supply end of the power supply, and the lower ends are grounded;
the power supply end is connected with decoupling capacitors C1 and C2 in parallel, and the drain electrode of the transistor M5 of the output buffer circuit draws bias voltage through a resistor R5.
8. The voltage-stabilizing active bias circuit as claimed in claim 7, wherein the voltage-stabilizing active bias module includes transistors M1, M2, M3 and resistors R1, R2, R3;
the resistors R1 and R2 are connected in series and then connected with the drain of the transistor M1, wherein the upper end of the resistor R1 is connected with the power supply end;
the grid electrode and the drain electrode of the transistor M2 are connected and then connected with the source electrode of the transistor M1, and the source electrode of the transistor M2 is grounded;
the upper end of the resistor R3 is connected with the grid of the transistor M1, and the lower end is grounded;
the drain of the transistor M3 is connected with the power supply end, the source of the transistor M3 is connected with the gate of the transistor M1, and the gate of the transistor M3 is connected with the serial connection position of the resistors R1 and R2.
9. An active bias circuit as claimed in claim 8, in which the transistor M2 is replaced by a diode or diodes connected in series in parallel at the source of the transistor M1.
10. An active bias circuit as claimed in claim 7, wherein the transistor M5 is replaced by a transistor in the form of a plurality of diodes or a plurality of diodes connected in series at the drain of the transistor M4.
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CN202111123526.5A CN113917970A (en) | 2021-09-24 | 2021-09-24 | Output buffer circuit, voltage-stabilizing active bias circuit and active bias circuit |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0417190A (en) * | 1990-05-11 | 1992-01-21 | Hitachi Ltd | Semiconductor device |
US20110291742A1 (en) * | 2010-05-27 | 2011-12-01 | Chua-Chin Wang | Output buffer with process and temperature compensation |
CN110190824A (en) * | 2019-05-30 | 2019-08-30 | 广东工业大学 | A kind of active biased network and a kind of radio-frequency power amplifier |
CN110611488A (en) * | 2019-08-05 | 2019-12-24 | 浙江铖昌科技有限公司 | Temperature compensation active bias circuit |
-
2021
- 2021-09-24 CN CN202111123526.5A patent/CN113917970A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0417190A (en) * | 1990-05-11 | 1992-01-21 | Hitachi Ltd | Semiconductor device |
US20110291742A1 (en) * | 2010-05-27 | 2011-12-01 | Chua-Chin Wang | Output buffer with process and temperature compensation |
CN110190824A (en) * | 2019-05-30 | 2019-08-30 | 广东工业大学 | A kind of active biased network and a kind of radio-frequency power amplifier |
CN110611488A (en) * | 2019-08-05 | 2019-12-24 | 浙江铖昌科技有限公司 | Temperature compensation active bias circuit |
Non-Patent Citations (2)
Title |
---|
童华清 等: "带有源偏置的系统级封装低噪声放大器模块", 《浙江大学学报(工学版)》 * |
许石义 等: "基于负反馈和有源偏置的宽带低噪放设计", 《浙江大学学报(工学版)》 * |
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