CN110971201B - Bias circuit of power amplifier - Google Patents
Bias circuit of power amplifier Download PDFInfo
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- CN110971201B CN110971201B CN201911405591.XA CN201911405591A CN110971201B CN 110971201 B CN110971201 B CN 110971201B CN 201911405591 A CN201911405591 A CN 201911405591A CN 110971201 B CN110971201 B CN 110971201B
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- bias
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- diode
- triode
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
Abstract
The application discloses a power amplifier bias circuit, which comprises a first bias network and a second bias network, wherein the first bias network comprises an LDO (low dropout regulator), a differential output driving circuit, a linearization bias circuit and a discharge loop circuit, the linearization bias circuit comprises a first triode, a first voltage division network and a voltage stabilizing filter network, the collector of the first triode is connected with an output port P of the differential output driving circuit through an isolation resistor, the emitter is connected with the base of a first amplifying tube core, and the voltage stabilizing filter network is connected between the collector and the base; the first voltage dividing network provides bias voltage for the first triode; in the second bias network, the input end of the bias driving circuit is connected with a power supply, and the output end of the bias driving circuit is connected with the base electrode of the second amplifying tube core through the second voltage division network. The circuit can reduce the sensitivity of the power amplifier to temperature change and/or reference voltage change, so that the amplifier can stably work, the modulation speed of the amplifier is improved, and the standby power consumption of the amplifier is reduced.
Description
Technical Field
The application belongs to the field of electronic communication, and particularly relates to a power amplifier bias circuit.
Background
In electronic communication systems, amplifiers are one of the most important devices, and have a wide range of applications in radar systems, microwave communication systems and measurement systems.
The base current of the amplifying tube core T1 of the power amplifier is gradually increased along with the increase of the output power or the increase of the device temperature, and a base resistor voltage dividing bias network adopted by the traditional structure is shown in figure 1; in fig. 1, in order to reduce the power consumption of the bias network, voltage dividing resistors Rb1 and Rb2 (as in fig. 1 (a)) or R0 to RN (as in fig. 1 (b)) with larger resistance are generally selected, but as the base current increases, the base bias voltage Vb decreases, so that the output power of the power amplifier decreases, and at the same time, the voltage dividing resistor can only perform voltage dividing function, and the voltage of Vb is sensitive to the voltage value of the Vb port.
In order to reduce the influence of the voltage drop of the resistor on the bias voltage Vb, the conventional active bias mostly uses two diodes D1 and D2 to generate a reference voltage in series, and then provides bias to the amplifying triode core T0 through the bias triode Tb 1; wherein the base current of the amplifying triode core T0 is supplied through the emitter of the triode Tb1, and no voltage drop loss caused by resistance exists; at the same time, when the temperature changes, the Vbe of the transistors Tb1 and T0 and the diodes D1 and D2 will change in the same direction, so that the bias circuit has a certain compensation effect on the temperature changes, but does not compensate enough. Meanwhile, after the bias network is added, when the modulation circuit is driven by external integration, as shown in fig. 2, when the amplifier is turned off, the bias voltage Vb0 of the amplifying device T0 cannot be quickly reduced to 0V due to the self-adaptive effect of the bias network voltage, so that the modulation speed of the amplifier is reduced.
Disclosure of Invention
The application aims to provide a power amplifier bias circuit which can obviously improve the output power of a common-emitter common-base power amplifier, a common-base amplifier or a common-emitter amplifier, reduce the sensitivity of the power amplifier to temperature change and/or reference voltage change, ensure that the amplifier works stably, obviously improve the modulation speed of the amplifier and reduce the standby power consumption of the amplifier.
In order to achieve the above object, the solution of the present application is:
a power amplifier bias circuit, the said power amplifier includes the first, second amplifier tube core, the collector of the first amplifier tube core connects the emitter of the second amplifier tube core, the collector of the second amplifier tube core connects the power; the bias circuit comprises a first bias network and a second bias network, the first bias network comprises an LDO, a differential output driving circuit, a linearization bias circuit and a discharging loop circuit, wherein the linearization bias circuit is used for providing bias current for a first amplifying tube core and comprises a first triode, a first voltage division network and a voltage stabilizing filter network, the collector of the first triode is connected with an output port P of the differential output driving circuit, the emitter of the first triode is connected with the base of the first amplifying tube core, and a voltage stabilizing filter network is connected between the emitter of the first triode and the base of the first amplifying tube core; the first voltage dividing network is connected with the base electrode of the first triode and provides bias voltage for the first triode;
the input end of the LDO is connected with a power supply, and the output end of the LDO is connected with a differential output driving circuit;
the discharging loop circuit comprises an MOS tube, wherein the grid electrode of the MOS tube is connected with an output port N of the differential output driving circuit, the source electrode of the MOS tube is grounded, and the drain electrode of the MOS tube is connected with the emitter electrode of the first triode;
the second bias network comprises a bias driving circuit and a second voltage division network, wherein the input end of the bias driving circuit is connected with a power supply and a modulation signal, and the output end of the bias driving circuit is connected with the base electrode of the second amplifying tube core through the second voltage division network.
The first voltage dividing network comprises a third voltage dividing resistor, a second voltage stabilizing diode, a third voltage stabilizing diode and a second filter capacitor, wherein one end of the third voltage dividing resistor is connected with an output port P of the differential output driving circuit, and the other end of the third voltage dividing resistor is connected with a base electrode of the first triode; one end of the second filter capacitor is connected with the base electrode of the first triode, and the other end of the second filter capacitor is grounded; the anode of the third zener diode is connected with the base electrode of the first triode, the cathode of the third zener diode is connected with the anode of the second zener diode, and the cathode of the second zener diode is grounded.
The first voltage dividing network further comprises a second voltage dividing resistor connected with the second filter capacitor in parallel.
The voltage stabilizing filter network comprises a voltage stabilizing diode and a first filter capacitor, wherein the anode of the voltage stabilizing diode is connected with the emitter of the first triode, and the cathode of the voltage stabilizing diode is grounded; one end of the first filter capacitor is connected with the emitter of the first triode, and the other end of the first filter capacitor is grounded.
The voltage stabilizing filter network further comprises a pull-down resistor connected with the first filter capacitor in parallel.
The second voltage division network comprises a bias voltage boosting diode and a bias voltage dropping diode, wherein the anode of the bias voltage dropping diode is connected with the output port P of the bias driving circuit, the cathode of the bias voltage dropping diode is connected with the anode of the bias voltage boosting diode, the connection point is used as a common point, the common point is connected with the base electrode of the second amplifying tube core, and the cathode of the bias voltage boosting diode is grounded.
The second voltage division network further comprises a first bias resistor and a second bias resistor, wherein the first bias resistor is connected between an output port P of the bias driving circuit and the bias buck diode or between the bias buck diode and a common point; the second bias resistor is connected between the common point and the bias boost diode or between the bias boost diode and ground.
The linearization bias circuit further comprises an isolation resistor, and the isolation resistor is connected between the collector electrode of the first triode and the output port P of the differential output driving circuit.
The discharging loop circuit further comprises a current limiting resistor, one end of the current limiting resistor is connected with the output port N of the differential output driving circuit, and the other end of the current limiting resistor is connected with the grid electrode of the MOS tube.
After the scheme is adopted, on the basis of the traditional resistor voltage dividing network and the active bias network, the LDO with temperature compensation characteristic of output voltage is introduced to adjust base bias voltage in high and low temperature environment, the voltage dividing resistance value is reduced, and the high and low temperature characteristic drift of the amplifier is improved; by introducing a diode D in the first biasing network b1 And an active bias die T b1 Ensuring a greater output power at the amplifier; meanwhile, in the second bias network, the resistance is changed into the combination of a diode and a resistance, so that the equivalent resistance of the voltage division network is reduced while the voltage division is realized, and the power amplifier is ensured to have larger output power; the voltage stabilizing diode and the voltage reducing diode in the bias circuit can obviously improve the consistency of the characteristics of the amplifier, and simultaneously reduce the sensitivity to temperature change and port voltage change, so that the power amplifier can keep a normal working state under different working environments.
Drawings
FIG. 1 is a schematic diagram of a prior art amplifier bias circuit employing resistive voltage division;
wherein (a) and (b) are two voltage dividing circuits respectively;
FIG. 2 is a schematic diagram of a conventional amplifier bias circuit employing active bias and modulation scheme of a conventional amplifier;
FIG. 3 is a circuit topology diagram of an embodiment of the present application;
FIG. 4 is a schematic diagram of comparing output power of an embodiment of the present application with output power using a conventional bias structure;
FIG. 5 is a schematic diagram of comparing output power with output power using a conventional bias structure in a high temperature environment according to an embodiment of the present application;
FIG. 6 is a graph showing a comparison of the difference between 25 degrees output power minus 85 degrees output power;
fig. 7 is a diagram showing a comparison of modulation speeds of the amplifier according to the embodiment of the present application and the amplifier bias voltage Vb0 of the structure in fig. 2.
Detailed Description
The present application is further illustrated in the accompanying drawings and detailed description which are to be understood as being merely illustrative of the application and not limiting of its scope, since various modifications of the application, which are equivalent to those skilled in the art, will fall within the scope of the application as defined in the appended claims after reading the application.
As shown in fig. 3, an embodiment of a power amplifier bias circuit according to the present application is a cascode amplifier structure, and the bias circuit is composed of a common emitter bias network 1 and a common base bias network 2, which are described below.
The bias network 1 is applied to a base bias port of a common emitter amplifying unit and comprises a low dropout linear regulator (LDO), a differential output driving circuit, a linearization bias circuit and a discharge loop circuit.
The linearization bias circuit comprises a triode T b1 To the amplifying die T 0 Providing a bias current; r is R b2 、R b3 、D b2 、D b3 And capacitor C b2 Forms a voltage-dividing network with voltage stabilizing function for the triode T b1 Providing a bias; diode D b1 Filter capacitor C b1 And pull-down resistor R b1 Connecting triode T b1 The emitter of the transistor plays a role in stabilizing the voltage and filtering pull-down potential; resistor R b4 Located in triode T b1 And LDO, and has isolation effect.
Specifically, an active bias transistor T b1 Through resistor R b4 Connected to the output port P of the differential output driving circuit, the resistor R b4 The effect of the isolation is achieved, the isolation effect is achieved,filtering out interference of the outside to the amplifier circuit, and resistor R b4 A negative temperature coefficient resistor can be adopted, and the consistency of the high-low temperature characteristics can be slightly adjusted; active bias triode T b1 V with emitter connected to amplifier die b0 At the end at T b1 Emitter and amplifier die T of (c) 0 V of (2) b0 Between which is formed by a voltage stabilizing diode D b1 Filter capacitor C b1 And pull-down resistor R b1 Forming a voltage stabilizing filter network, wherein D b1 Resistor R under high power condition with voltage stabilizing compensation b4 And (C) voltage consumption and uniformity improvement b1 Plays a role of filtering and isolating, and has positive temperature coefficient resistance R b1 Plays a role in pulling down and adjusting the consistency of high-low temperature characteristics; active bias triode T b1 Is connected to the base of R b2 And R is b3 D (D) b2 And D b3 The output end of the resistor voltage division circuit with voltage stabilization is formed, R b2 、R b3 、D b2 、D b3 And capacitor C b2 Forms a voltage-dividing network with voltage stabilizing function for the triode T b1 Providing bias, wherein R b3 Adopts smaller resistance value, and can adopt negative temperature coefficient characteristic resistance to adjust high-low temperature characteristic consistency, R b2 Positive temperature coefficient characteristic resistance is adopted; d (D) b2 And D b3 The functions of stabilizing voltage and improving consistency are achieved; c (C) b2 And C b3 And plays a role in filtering decoupling.
On-chip integrated LDO connection to V C1 The LDO output end is connected to R through a differential output driving circuit b3 、C b3 、R b4 The stable bias voltage is output, has certain temperature characteristics, and different temperature coefficients are designed according to different bias points of the amplifier, so that the high-low temperature gain change of the amplifier can be effectively restrained; meanwhile, the resistance R can be effectively reduced by reducing the output voltage of the LDO in the design b3 Is a value of (2). Reducing R b3 The main reason for the resistance is that the on-current of the diode and the voltage across the diode are exponentially related, since the current passes R b3 So that triode T b1 Voltage variation and R of the base electrode of the transistor under high and low temperature environment b3 The values are related, smaller R b3 The resistance value reduces the high-low temperature voltage variation, thereby further suppressing the amplifier high-low temperature gain variation. The on-chip LDO has an external configuration point, and the amplitude of the amplifier can be adjusted by adjusting the output voltage of the LDO through serial data or parallel data control.
The discharge loop circuit mainly comprises a resistor R f And MOS tube M 1 The output port N connected to the differential output driving circuit and the linearization bias circuit form a differential working mode to form T 0 Is set to be V b0 Optimum bleed-off path for base voltage V of amplifier die by incorporating delay capacitance or the like b0 The power-on time and the power-off time of the amplifier are basically consistent, thereby obviously improving the modulation speed of the amplifier.
The bias network 1 can avoid V b0 The drastic decrease of the bias voltage of the single-chip integrated circuit leads to the decrease of the linearity and the power of the amplifier, and simultaneously can realize the same power supply voltage of the single-chip integrated circuit, reduce the requirement on the outside and have convenient use.
The bias network 2 is applied to a base bias port of the common base amplifying unit and comprises a driving circuit and a voltage dividing network for forming voltage dividing and stabilizing functions, wherein the voltage dividing network consists of a diode and a resistor, D 1 A bias boosting diode D representing a common base amplifying unit 2 Bias buck diode representing common base amplifying unit, resistor R 1 And R is 2 Representing the equivalent bias resistance of the common base amplifying unit, the voltage divider network is used to ensure that the voltage divider impedance is reduced at lower bias power consumption. The number of the diodes is 0 or 1 or several according to specific bias voltage, ensuring the voltage drop and the resistance R 2 Transistor T 1 The base current of the amplifier is limited to be low, and the driving circuit is adopted to realize low standby power consumption of the amplifier.
Pull-down resistor R in the bias network 1 b1 、R b2 Isolation resistor R b4 And R in the bias network 2 1 And R is 2 Can be removed according to the actual use environment.
From T 1 The common base amplifying section may be constructed to repeatedly duplicate a plurality of common base amplifying units.
Fig. 4 is a graph of the output power of a power amplifier employing the bias network of the present application versus a power amplifier employing a conventional resistor divider and active bias network. (the voltage of static nodes of Vb0 and Vb1 are the same; the rest of the circuits are the same except the bias network). As can be seen from the figure, the bias network of the present application can significantly increase the maximum output power.
Fig. 5 is a graph of the output power at 85 degrees for a power amplifier employing the bias network of the present application versus a power amplifier employing a conventional resistor divider and active bias network. Fig. 6 is a comparison of the difference of 25 degrees output power minus 85 degrees output power. It can be seen from the figure that the high temperature output power of the power amplifier can be significantly improved by adopting the bias network of the application.
The modulation speed comparison of the amplifier bias Vb0 of the present application and the amplifier bias Vb0 using a conventional active bias network and external modulation is shown in fig. 7. As can be seen from the figure, the bias network of the present application can significantly reduce the discharge speed of the amplifier Vb0, thereby improving the modulation rate of the amplifier.
The diode D according to the above embodiment 1 、D b1 、D b2 And D b3 The emitter of the triode can be equivalent to the N pole of the diode by connecting the base electrode and the collector electrode of the triode to be equivalent to the P pole of the diode; the diode D 1 、D b1 、D b2 And D b3 The grid electrode and the drain electrode of the MOS tube are connected and equivalent to the P electrode of the diode, and the source electrode of the MOS tube is equivalent to the N electrode of the diode; in actual operation, the diode D 1 、D b1 、D b2 And D b3 The grid electrode and the source electrode of the MOS tube are connected and equivalent to the P electrode of the diode, and the drain electrode of the MOS tube is equivalent to the N electrode of the diode.
The above embodiments are only for illustrating the technical idea of the present application, and the protection scope of the present application is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present application falls within the protection scope of the present application.
Claims (3)
1. A power amplifier bias circuit, the said power amplifier includes the first, second amplifier tube core, the collector of the first amplifier tube core connects the emitter of the second amplifier tube core, the collector of the second amplifier tube core connects the power; the method is characterized in that: the bias circuit comprises a first bias network and a second bias network, the first bias network comprises a low-dropout linear voltage stabilizer, a differential output driving circuit, a linearization bias circuit and a discharging loop circuit, wherein the linearization bias circuit is used for providing bias current for a first amplifying tube core and comprises a first triode, a first voltage division network and a voltage stabilizing filter network, the collector of the first triode is connected with an output port P of the differential output driving circuit, the emitter of the first triode is connected with the base of the first amplifying tube core, and a voltage stabilizing filter network is connected between the emitter of the first triode and the base of the first amplifying tube core; the first voltage dividing network is connected with the base electrode of the first triode and provides bias voltage for the first triode;
the input end of the low-dropout linear voltage regulator is connected with a power supply, and the output end of the low-dropout linear voltage regulator is connected with a differential output driving circuit;
the discharging loop circuit comprises an MOS tube, wherein the grid electrode of the MOS tube is connected with an output port N of the differential output driving circuit, the source electrode of the MOS tube is grounded, and the drain electrode of the MOS tube is connected with the emitter electrode of the first triode;
the first voltage dividing network comprises a third voltage dividing resistor, a second voltage stabilizing diode, a third voltage stabilizing diode, a second filter capacitor and a second voltage dividing resistor, wherein one end of the third voltage dividing resistor is connected with an output port P of the differential output driving circuit, and the other end of the third voltage dividing resistor is connected with a base electrode of the first triode; one end of the second filter capacitor is connected with the base electrode of the first triode, and the other end of the second filter capacitor is grounded; the anode of the third zener diode is connected with the base electrode of the first triode, the cathode of the third zener diode is connected with the anode of the second zener diode, and the cathode of the second zener diode is grounded; the second voltage dividing resistor is connected with the second filter capacitor in parallel;
the voltage stabilizing filter network comprises a voltage stabilizing diode, a first filter capacitor and a pull-down resistor, wherein the anode of the voltage stabilizing diode is connected with the emitter of the first triode, and the cathode of the voltage stabilizing diode is grounded; one end of the first filter capacitor is connected with the emitter of the first triode, and the other end of the first filter capacitor is grounded; the pull-down resistor is connected with the first filter capacitor in parallel;
the second bias network comprises a bias driving circuit and a second voltage division network, the input end of the bias driving circuit is connected with a power supply and a modulation signal, and the output end of the bias driving circuit is connected with the base electrode of the second amplifying tube core through the second voltage division network;
the second voltage division network comprises a bias boost diode, a bias buck diode, a first bias resistor and a second bias resistor, wherein the anode of the bias buck diode is connected with an output port P of the bias drive circuit, the cathode of the bias buck diode is connected with the anode of the bias boost diode, and a connection point between the cathode of the bias buck diode and the anode of the bias boost diode is used as a common point, the common point is connected to the base electrode of the second amplifying tube core, and the cathode of the bias boost diode is grounded; the first bias resistor is connected between the output port P of the bias driving circuit and the bias buck diode or between the bias buck diode and the common point; the second bias resistor is connected between the common point and the bias boost diode or between the bias boost diode and ground.
2. A power amplifier biasing circuit as defined in claim 1, wherein: the linearization bias circuit further comprises an isolation resistor, and the isolation resistor is connected between the collector electrode of the first triode and the output port P of the differential output driving circuit.
3. A power amplifier biasing circuit as defined in claim 1, wherein: the discharging loop circuit further comprises a current limiting resistor, one end of the current limiting resistor is connected with the output port N of the differential output driving circuit, and the other end of the current limiting resistor is connected with the grid electrode of the MOS tube.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911405591.XA CN110971201B (en) | 2019-12-31 | 2019-12-31 | Bias circuit of power amplifier |
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| CN201911405591.XA CN110971201B (en) | 2019-12-31 | 2019-12-31 | Bias circuit of power amplifier |
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| CN110971201B true CN110971201B (en) | 2023-09-12 |
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| CN114295153A (en) * | 2021-12-24 | 2022-04-08 | 上海致景信息科技有限公司 | Warp knitting machine yield sampler and sampling method |
| CN115580241B (en) * | 2022-12-09 | 2023-02-24 | 三微电子科技(苏州)有限公司 | Power amplifier and bias circuit thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000223963A (en) * | 1999-01-29 | 2000-08-11 | Toshiba Corp | High frequency amplifier |
| CN108111135A (en) * | 2016-11-25 | 2018-06-01 | 株式会社村田制作所 | Power amplification circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6888410B1 (en) * | 2003-10-10 | 2005-05-03 | Broadcom Corp. | Power amplifier having low gate oxide stress |
| JP2018007029A (en) * | 2016-07-01 | 2018-01-11 | 株式会社村田製作所 | Bias circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000223963A (en) * | 1999-01-29 | 2000-08-11 | Toshiba Corp | High frequency amplifier |
| CN108111135A (en) * | 2016-11-25 | 2018-06-01 | 株式会社村田制作所 | Power amplification circuit |
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